Lines Matching refs:oct
219 struct octeon_device *oct = lio->oct_dev; in lio_get_link_ksettings() local
247 dev_dbg(&oct->pci_dev->dev, "ecmd->base.transceiver is XCVR_EXTERNAL\n"); in lio_get_link_ksettings()
250 dev_err(&oct->pci_dev->dev, "Unknown link interface mode: %d\n", in lio_get_link_ksettings()
260 if (oct->subsystem_id == OCTEON_CN2350_25GB_SUBSYS_ID || in lio_get_link_ksettings()
261 oct->subsystem_id == OCTEON_CN2360_25GB_SUBSYS_ID) { in lio_get_link_ksettings()
262 if (OCTEON_CN23XX_PF(oct)) { in lio_get_link_ksettings()
270 if (oct->no_speed_setting == 0) { in lio_get_link_ksettings()
282 if (oct->no_speed_setting == 0) { in lio_get_link_ksettings()
286 oct->speed_setting = 25; in lio_get_link_ksettings()
289 if (oct->speed_setting == 10) { in lio_get_link_ksettings()
300 if (oct->speed_setting == 25) { in lio_get_link_ksettings()
312 if (oct->no_speed_setting) in lio_get_link_ksettings()
320 if (oct->props[lio->ifidx].fec == 1) { in lio_get_link_ksettings()
400 struct octeon_device *oct; in lio_set_link_ksettings() local
402 oct = lio->oct_dev; in lio_set_link_ksettings()
406 if (!(oct->subsystem_id == OCTEON_CN2350_25GB_SUBSYS_ID || in lio_set_link_ksettings()
407 oct->subsystem_id == OCTEON_CN2360_25GB_SUBSYS_ID)) in lio_set_link_ksettings()
410 if (oct->no_speed_setting) { in lio_set_link_ksettings()
411 dev_err(&oct->pci_dev->dev, "%s: Changing speed is not supported\n", in lio_set_link_ksettings()
423 if ((oct->speed_boot == speed / 1000) && in lio_set_link_ksettings()
424 oct->speed_boot == oct->speed_setting) in lio_set_link_ksettings()
429 dev_dbg(&oct->pci_dev->dev, "Port speed is set to %dG\n", in lio_set_link_ksettings()
430 oct->speed_setting); in lio_set_link_ksettings()
439 struct octeon_device *oct; in lio_get_drvinfo() local
442 oct = lio->oct_dev; in lio_get_drvinfo()
446 strncpy(drvinfo->fw_version, oct->fw_info.liquidio_firmware_version, in lio_get_drvinfo()
448 strncpy(drvinfo->bus_info, pci_name(oct->pci_dev), 32); in lio_get_drvinfo()
454 struct octeon_device *oct; in lio_get_vf_drvinfo() local
458 oct = lio->oct_dev; in lio_get_vf_drvinfo()
462 strncpy(drvinfo->fw_version, oct->fw_info.liquidio_firmware_version, in lio_get_vf_drvinfo()
464 strncpy(drvinfo->bus_info, pci_name(oct->pci_dev), 32); in lio_get_vf_drvinfo()
471 struct octeon_device *oct = lio->oct_dev; in lio_send_queue_count_update() local
487 dev_err(&oct->pci_dev->dev, "Failed to send Queue reset command (ret: 0x%x)\n", in lio_send_queue_count_update()
500 struct octeon_device *oct = lio->oct_dev; in lio_ethtool_get_channels() local
504 if (OCTEON_CN6XXX(oct)) { in lio_ethtool_get_channels()
505 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx); in lio_ethtool_get_channels()
511 } else if (OCTEON_CN23XX_PF(oct)) { in lio_ethtool_get_channels()
512 if (oct->sriov_info.sriov_enabled) { in lio_ethtool_get_channels()
516 CHIP_CONF(oct, cn23xx_pf); in lio_ethtool_get_channels()
520 combined_count = oct->num_iqs; in lio_ethtool_get_channels()
521 } else if (OCTEON_CN23XX_VF(oct)) { in lio_ethtool_get_channels()
525 reg_val = octeon_read_csr64(oct, ctrl); in lio_ethtool_get_channels()
528 combined_count = oct->num_iqs; in lio_ethtool_get_channels()
540 lio_irq_reallocate_irqs(struct octeon_device *oct, uint32_t num_ioqs) in lio_irq_reallocate_irqs() argument
546 if (!oct->msix_on) in lio_irq_reallocate_irqs()
552 oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR); in lio_irq_reallocate_irqs()
554 if (oct->msix_on) { in lio_irq_reallocate_irqs()
555 if (OCTEON_CN23XX_PF(oct)) in lio_irq_reallocate_irqs()
556 num_msix_irqs = oct->num_msix_irqs - 1; in lio_irq_reallocate_irqs()
557 else if (OCTEON_CN23XX_VF(oct)) in lio_irq_reallocate_irqs()
558 num_msix_irqs = oct->num_msix_irqs; in lio_irq_reallocate_irqs()
560 msix_entries = (struct msix_entry *)oct->msix_entries; in lio_irq_reallocate_irqs()
562 if (oct->ioq_vector[i].vector) { in lio_irq_reallocate_irqs()
567 &oct->ioq_vector[i]); in lio_irq_reallocate_irqs()
568 oct->ioq_vector[i].vector = 0; in lio_irq_reallocate_irqs()
573 if (OCTEON_CN23XX_PF(oct)) in lio_irq_reallocate_irqs()
574 free_irq(msix_entries[i].vector, oct); in lio_irq_reallocate_irqs()
576 pci_disable_msix(oct->pci_dev); in lio_irq_reallocate_irqs()
577 kfree(oct->msix_entries); in lio_irq_reallocate_irqs()
578 oct->msix_entries = NULL; in lio_irq_reallocate_irqs()
581 kfree(oct->irq_name_storage); in lio_irq_reallocate_irqs()
582 oct->irq_name_storage = NULL; in lio_irq_reallocate_irqs()
584 if (octeon_allocate_ioq_vector(oct, num_ioqs)) { in lio_irq_reallocate_irqs()
585 dev_err(&oct->pci_dev->dev, "OCTEON: ioq vector allocation failed\n"); in lio_irq_reallocate_irqs()
589 if (octeon_setup_interrupt(oct, num_ioqs)) { in lio_irq_reallocate_irqs()
590 dev_info(&oct->pci_dev->dev, "Setup interrupt failed\n"); in lio_irq_reallocate_irqs()
595 oct->fn_list.enable_interrupt(oct, OCTEON_ALL_INTR); in lio_irq_reallocate_irqs()
606 struct octeon_device *oct = lio->oct_dev; in lio_ethtool_set_channels() local
609 if (strcmp(oct->fw_info.liquidio_firmware_version, "1.6.1") < 0) { in lio_ethtool_set_channels()
610 dev_err(&oct->pci_dev->dev, "Minimum firmware version required is 1.6.1\n"); in lio_ethtool_set_channels()
620 if (OCTEON_CN23XX_PF(oct)) { in lio_ethtool_set_channels()
621 if (oct->sriov_info.sriov_enabled) { in lio_ethtool_set_channels()
625 CHIP_CONF(oct, in lio_ethtool_set_channels()
631 } else if (OCTEON_CN23XX_VF(oct)) { in lio_ethtool_set_channels()
635 reg_val = octeon_read_csr64(oct, ctrl); in lio_ethtool_set_channels()
645 if (combined_count == oct->num_iqs) in lio_ethtool_set_channels()
706 struct octeon_device *oct = lio->oct_dev; in octnet_gpio_access() local
722 dev_err(&oct->pci_dev->dev, in octnet_gpio_access()
733 struct octeon_device *oct = lio->oct_dev; in octnet_id_active() local
748 dev_err(&oct->pci_dev->dev, in octnet_id_active()
832 struct octeon_device *oct = lio->oct_dev; in lio_set_phys_id() local
838 cur_ver = OCT_FW_VER(oct->fw_info.ver.maj, in lio_set_phys_id()
839 oct->fw_info.ver.min, in lio_set_phys_id()
840 oct->fw_info.ver.rev); in lio_set_phys_id()
844 if (oct->chip_id == OCTEON_CN66XX) { in lio_set_phys_id()
849 } else if (oct->chip_id == OCTEON_CN68XX) { in lio_set_phys_id()
877 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) { in lio_set_phys_id()
890 if (oct->chip_id == OCTEON_CN23XX_PF_VID && in lio_set_phys_id()
894 else if (oct->chip_id == OCTEON_CN66XX) in lio_set_phys_id()
903 if (oct->chip_id == OCTEON_CN23XX_PF_VID && in lio_set_phys_id()
907 else if (oct->chip_id == OCTEON_CN66XX) in lio_set_phys_id()
916 if (oct->chip_id == OCTEON_CN66XX) { in lio_set_phys_id()
919 } else if (oct->chip_id == OCTEON_CN68XX) { in lio_set_phys_id()
932 } else if (oct->chip_id == OCTEON_CN23XX_PF_VID) { in lio_set_phys_id()
955 struct octeon_device *oct = lio->oct_dev; in lio_ethtool_get_ringparam() local
962 if (OCTEON_CN6XXX(oct)) { in lio_ethtool_get_ringparam()
963 struct octeon_config *conf6x = CHIP_CONF(oct, cn6xxx); in lio_ethtool_get_ringparam()
969 } else if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) { in lio_ethtool_get_ringparam()
972 rx_pending = oct->droq[0]->max_count; in lio_ethtool_get_ringparam()
973 tx_pending = oct->instr_queue[0]->max_count; in lio_ethtool_get_ringparam()
988 struct octeon_device *oct = lio->oct_dev; in lio_23xx_reconfigure_queue_count() local
1001 octeon_alloc_soft_command(oct, data_size, in lio_23xx_reconfigure_queue_count()
1004 dev_err(&oct->pci_dev->dev, "%s: Failed to allocate soft command\n", in lio_23xx_reconfigure_queue_count()
1016 ifidx_or_pfnum = oct->pf_num; in lio_23xx_reconfigure_queue_count()
1019 if_cfg.s.num_iqueues = oct->sriov_info.num_pf_rings; in lio_23xx_reconfigure_queue_count()
1020 if_cfg.s.num_oqueues = oct->sriov_info.num_pf_rings; in lio_23xx_reconfigure_queue_count()
1021 if_cfg.s.base_queue = oct->sriov_info.pf_srn; in lio_23xx_reconfigure_queue_count()
1022 if_cfg.s.gmx_port_id = oct->pf_num; in lio_23xx_reconfigure_queue_count()
1025 octeon_prepare_soft_command(oct, sc, OPCODE_NIC, in lio_23xx_reconfigure_queue_count()
1032 retval = octeon_send_soft_command(oct, sc); in lio_23xx_reconfigure_queue_count()
1034 dev_err(&oct->pci_dev->dev, in lio_23xx_reconfigure_queue_count()
1037 octeon_free_soft_command(oct, sc); in lio_23xx_reconfigure_queue_count()
1041 retval = wait_for_sc_completion_timeout(oct, sc, 0); in lio_23xx_reconfigure_queue_count()
1047 dev_err(&oct->pci_dev->dev, in lio_23xx_reconfigure_queue_count()
1075 dev_info(&oct->pci_dev->dev, "Queue count updated to %d\n", in lio_23xx_reconfigure_queue_count()
1086 struct octeon_device *oct = lio->oct_dev; in lio_reset_queues() local
1093 if (wait_for_pending_requests(oct)) in lio_reset_queues()
1094 dev_err(&oct->pci_dev->dev, "There were pending requests\n"); in lio_reset_queues()
1096 if (lio_wait_for_instr_fetch(oct)) in lio_reset_queues()
1097 dev_err(&oct->pci_dev->dev, "IQ had pending instructions\n"); in lio_reset_queues()
1099 if (octeon_set_io_queues_off(oct)) { in lio_reset_queues()
1100 dev_err(&oct->pci_dev->dev, "Setting io queues off failed\n"); in lio_reset_queues()
1107 oct->fn_list.disable_io_queues(oct); in lio_reset_queues()
1112 if (num_qs != oct->num_iqs) { in lio_reset_queues()
1115 dev_err(&oct->pci_dev->dev, in lio_reset_queues()
1122 dev_err(&oct->pci_dev->dev, in lio_reset_queues()
1147 if ((OCTEON_CN23XX_PF(oct)) && !oct->sriov_info.sriov_enabled) in lio_reset_queues()
1148 oct->fn_list.free_mbox(oct); in lio_reset_queues()
1151 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) { in lio_reset_queues()
1152 if (!(oct->io_qmask.oq & BIT_ULL(i))) in lio_reset_queues()
1154 octeon_delete_droq(oct, i); in lio_reset_queues()
1157 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { in lio_reset_queues()
1158 if (!(oct->io_qmask.iq & BIT_ULL(i))) in lio_reset_queues()
1160 octeon_delete_instr_queue(oct, i); in lio_reset_queues()
1165 if ((OCTEON_CN23XX_PF(oct)) && in lio_reset_queues()
1166 !oct->sriov_info.sriov_enabled) { in lio_reset_queues()
1167 oct->sriov_info.num_pf_rings = num_qs; in lio_reset_queues()
1168 if (cn23xx_sriov_config(oct)) { in lio_reset_queues()
1169 dev_err(&oct->pci_dev->dev, in lio_reset_queues()
1174 num_qs = oct->sriov_info.num_pf_rings; in lio_reset_queues()
1178 if (oct->fn_list.setup_device_regs(oct)) { in lio_reset_queues()
1179 dev_err(&oct->pci_dev->dev, "Failed to configure device registers\n"); in lio_reset_queues()
1187 if (octeon_setup_instr_queues(oct)) in lio_reset_queues()
1190 if (octeon_setup_output_queues(oct)) in lio_reset_queues()
1194 if (OCTEON_CN23XX_PF(oct) && !oct->sriov_info.sriov_enabled) { in lio_reset_queues()
1195 if (oct->fn_list.setup_mbox(oct)) { in lio_reset_queues()
1196 dev_err(&oct->pci_dev->dev, "Mailbox setup failed\n"); in lio_reset_queues()
1204 if (lio_irq_reallocate_irqs(oct, num_qs)) { in lio_reset_queues()
1205 dev_err(&oct->pci_dev->dev, "IRQs could not be allocated\n"); in lio_reset_queues()
1210 if (oct->fn_list.enable_io_queues(oct)) { in lio_reset_queues()
1211 dev_err(&oct->pci_dev->dev, "Failed to enable input/output queues\n"); in lio_reset_queues()
1215 for (i = 0; i < oct->num_oqs; i++) in lio_reset_queues()
1216 writel(oct->droq[i]->max_count, in lio_reset_queues()
1217 oct->droq[i]->pkts_credit_reg); in lio_reset_queues()
1223 if (OCTEON_CN23XX_PF(oct) && !oct->sriov_info.sriov_enabled) { in lio_reset_queues()
1230 if (liquidio_setup_io_queues(oct, 0, num_qs, num_qs)) { in lio_reset_queues()
1231 dev_err(&oct->pci_dev->dev, "I/O queues creation failed\n"); in lio_reset_queues()
1236 if (lio_setup_glists(oct, lio, num_qs)) { in lio_reset_queues()
1237 dev_err(&oct->pci_dev->dev, "Gather list allocation failed\n"); in lio_reset_queues()
1242 dev_err(&oct->pci_dev->dev, "lio_setup_rx_oom_poll_fn failed\n"); in lio_reset_queues()
1249 if (oct->sriov_info.sriov_enabled || OCTEON_CN23XX_VF(oct)) in lio_reset_queues()
1265 struct octeon_device *oct = lio->oct_dev; in lio_ethtool_set_ringparam() local
1268 if (!OCTEON_CN23XX_PF(oct) && !OCTEON_CN23XX_VF(oct)) in lio_ethtool_set_ringparam()
1279 rx_count_old = oct->droq[0]->max_count; in lio_ethtool_set_ringparam()
1280 tx_count_old = oct->instr_queue[0]->max_count; in lio_ethtool_set_ringparam()
1294 CFG_SET_NUM_TX_DESCS_NIC_IF(octeon_get_conf(oct), lio->ifidx, in lio_ethtool_set_ringparam()
1297 CFG_SET_NUM_RX_DESCS_NIC_IF(octeon_get_conf(oct), lio->ifidx, in lio_ethtool_set_ringparam()
1300 if (lio_reset_queues(netdev, oct->num_iqs)) in lio_ethtool_set_ringparam()
1312 CFG_SET_NUM_TX_DESCS_NIC_IF(octeon_get_conf(oct), lio->ifidx, in lio_ethtool_set_ringparam()
1315 CFG_SET_NUM_RX_DESCS_NIC_IF(octeon_get_conf(oct), lio->ifidx, in lio_ethtool_set_ringparam()
1357 struct octeon_device *oct = lio->oct_dev; in lio_get_pauseparam() local
1361 pause->tx_pause = oct->tx_pause; in lio_get_pauseparam()
1362 pause->rx_pause = oct->rx_pause; in lio_get_pauseparam()
1372 struct octeon_device *oct = lio->oct_dev; in lio_set_pauseparam() local
1378 if (oct->chip_id != OCTEON_CN23XX_PF_VID) in lio_set_pauseparam()
1417 dev_err(&oct->pci_dev->dev, in lio_set_pauseparam()
1422 oct->rx_pause = pause->rx_pause; in lio_set_pauseparam()
1423 oct->tx_pause = pause->tx_pause; in lio_set_pauseparam()
2121 struct octeon_device *oct = lio->oct_dev; in lio_get_intr_coalesce() local
2128 switch (oct->chip_id) { in lio_get_intr_coalesce()
2132 intr_coal->rx_coalesce_usecs = oct->rx_coalesce_usecs; in lio_get_intr_coalesce()
2134 oct->rx_max_coalesced_frames; in lio_get_intr_coalesce()
2138 oct->tx_max_coalesced_frames; in lio_get_intr_coalesce()
2144 (struct octeon_cn6xxx *)oct->chip; in lio_get_intr_coalesce()
2152 iq = oct->instr_queue[lio->linfo.txpciq[0].s.q_no]; in lio_get_intr_coalesce()
2178 if ((OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct)) && in lio_get_intr_coalesce()
2229 struct octeon_device *oct = lio->oct_dev; in oct_cfg_rx_intrcnt() local
2233 switch (oct->chip_id) { in oct_cfg_rx_intrcnt()
2237 (struct octeon_cn6xxx *)oct->chip; in oct_cfg_rx_intrcnt()
2244 octeon_write_csr(oct, CN6XXX_SLI_OQ_INT_LEVEL_PKTS, in oct_cfg_rx_intrcnt()
2257 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrcnt()
2258 q_no += oct->sriov_info.pf_srn; in oct_cfg_rx_intrcnt()
2260 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no), in oct_cfg_rx_intrcnt()
2262 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no)) & in oct_cfg_rx_intrcnt()
2268 oct->rx_max_coalesced_frames = rx_max_coalesced_frames; in oct_cfg_rx_intrcnt()
2279 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrcnt()
2281 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), in oct_cfg_rx_intrcnt()
2283 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no)) & in oct_cfg_rx_intrcnt()
2289 oct->rx_max_coalesced_frames = rx_max_coalesced_frames; in oct_cfg_rx_intrcnt()
2302 struct octeon_device *oct = lio->oct_dev; in oct_cfg_rx_intrtime() local
2306 switch (oct->chip_id) { in oct_cfg_rx_intrtime()
2310 (struct octeon_cn6xxx *)oct->chip; in oct_cfg_rx_intrtime()
2316 time_threshold = lio_cn6xxx_get_oq_ticks(oct, in oct_cfg_rx_intrtime()
2318 octeon_write_csr(oct, in oct_cfg_rx_intrtime()
2334 cn23xx_pf_get_oq_ticks(oct, (u32)rx_coalesce_usecs); in oct_cfg_rx_intrtime()
2335 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrtime()
2336 q_no += oct->sriov_info.pf_srn; in oct_cfg_rx_intrtime()
2337 octeon_write_csr64(oct, in oct_cfg_rx_intrtime()
2344 oct->rx_coalesce_usecs = rx_coalesce_usecs; in oct_cfg_rx_intrtime()
2357 cn23xx_vf_get_oq_ticks(oct, (u32)rx_coalesce_usecs); in oct_cfg_rx_intrtime()
2358 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrtime()
2360 oct, CN23XX_VF_SLI_OQ_PKT_INT_LEVELS(q_no), in oct_cfg_rx_intrtime()
2366 oct->rx_coalesce_usecs = rx_coalesce_usecs; in oct_cfg_rx_intrtime()
2381 struct octeon_device *oct = lio->oct_dev; in oct_cfg_tx_intrcnt() local
2387 switch (oct->chip_id) { in oct_cfg_tx_intrcnt()
2401 for (q_no = 0; q_no < oct->num_iqs; q_no++) { in oct_cfg_tx_intrcnt()
2402 inst_cnt_reg = (oct->instr_queue[q_no])->inst_cnt_reg; in oct_cfg_tx_intrcnt()
2412 oct->tx_max_coalesced_frames = iq_intr_pkt; in oct_cfg_tx_intrcnt()
2428 struct octeon_device *oct = lio->oct_dev; in lio_set_intr_coalesce() local
2433 switch (oct->chip_id) { in lio_set_intr_coalesce()
2442 oct->instr_queue[q_no]->fill_threshold = in lio_set_intr_coalesce()
2446 dev_err(&oct->pci_dev->dev, in lio_set_intr_coalesce()
2462 intrmod.rx_frames = CFG_GET_OQ_INTR_PKT(octeon_get_conf(oct)); in lio_set_intr_coalesce()
2463 intrmod.rx_usecs = CFG_GET_OQ_INTR_TIME(octeon_get_conf(oct)); in lio_set_intr_coalesce()
2464 intrmod.tx_frames = CFG_GET_IQ_INTR_PKT(octeon_get_conf(oct)); in lio_set_intr_coalesce()
2477 oct->rx_coalesce_usecs = in lio_set_intr_coalesce()
2478 CFG_GET_OQ_INTR_TIME(octeon_get_conf(oct)); in lio_set_intr_coalesce()
2479 oct->rx_max_coalesced_frames = in lio_set_intr_coalesce()
2480 CFG_GET_OQ_INTR_PKT(octeon_get_conf(oct)); in lio_set_intr_coalesce()
2488 oct->tx_max_coalesced_frames = in lio_set_intr_coalesce()
2489 CFG_GET_IQ_INTR_PKT(octeon_get_conf(oct)); in lio_set_intr_coalesce()
2533 struct octeon_device *oct = lio->oct_dev; in lio_get_regs_len() local
2535 switch (oct->chip_id) { in lio_get_regs_len()
2545 static int cn23xx_read_csr_reg(char *s, struct octeon_device *oct) in cn23xx_read_csr_reg() argument
2548 u8 pf_num = oct->pf_num; in cn23xx_read_csr_reg()
2557 reg = CN23XX_SLI_PKT_MAC_RINFO64(oct->pcie_port, oct->pf_num); in cn23xx_read_csr_reg()
2560 reg, oct->pcie_port, oct->pf_num, in cn23xx_read_csr_reg()
2561 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2564 reg = CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num); in cn23xx_read_csr_reg()
2567 reg, oct->pcie_port, oct->pf_num, in cn23xx_read_csr_reg()
2568 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2571 reg = CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num); in cn23xx_read_csr_reg()
2574 reg, oct->pcie_port, oct->pf_num, in cn23xx_read_csr_reg()
2575 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2580 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2583 reg = 0x27300 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + in cn23xx_read_csr_reg()
2584 (oct->pf_num) * CN23XX_PF_INT_OFFSET; in cn23xx_read_csr_reg()
2587 oct->pcie_port, oct->pf_num, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2590 reg = 0x27200 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + in cn23xx_read_csr_reg()
2591 (oct->pf_num) * CN23XX_PF_INT_OFFSET; in cn23xx_read_csr_reg()
2594 reg, oct->pcie_port, oct->pf_num, in cn23xx_read_csr_reg()
2595 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2600 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2605 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2610 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2615 reg, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2620 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2626 (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2631 reg, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2639 reg, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2645 reg, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2652 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2660 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2668 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2676 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2685 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2693 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2701 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2708 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2716 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2724 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2733 i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2742 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2751 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2759 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_read_csr_reg()
2765 static int cn23xx_vf_read_csr_reg(char *s, struct octeon_device *oct) in cn23xx_vf_read_csr_reg() argument
2775 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2779 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2782 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2786 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2789 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2793 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2796 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2800 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2803 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2807 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2810 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2814 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2817 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2821 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2824 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2827 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2830 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2834 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2837 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2841 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2844 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2848 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2851 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2855 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2858 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2862 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2865 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2869 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2872 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2876 reg, i, (u64)octeon_read_csr64(oct, reg)); in cn23xx_vf_read_csr_reg()
2882 static int cn6xxx_read_csr_reg(char *s, struct octeon_device *oct) in cn6xxx_read_csr_reg() argument
2892 CN6XXX_WIN_WR_ADDR_LO, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2895 CN6XXX_WIN_WR_ADDR_HI, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2898 CN6XXX_WIN_RD_ADDR_LO, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2901 CN6XXX_WIN_RD_ADDR_HI, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2904 CN6XXX_WIN_WR_DATA_LO, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2907 CN6XXX_WIN_WR_DATA_HI, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2910 octeon_read_csr(oct, CN6XXX_WIN_WR_MASK_REG)); in cn6xxx_read_csr_reg()
2914 CN6XXX_SLI_INT_ENB64_PORT0, octeon_read_csr(oct, in cn6xxx_read_csr_reg()
2918 octeon_read_csr(oct, CN6XXX_SLI_INT_ENB64_PORT1)); in cn6xxx_read_csr_reg()
2920 octeon_read_csr(oct, CN6XXX_SLI_INT_SUM64)); in cn6xxx_read_csr_reg()
2923 for (i = 0; i < oct->num_oqs; i++) { in cn6xxx_read_csr_reg()
2926 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2929 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2933 reg, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2936 reg, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2944 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2947 reg, i, octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2954 octeon_read_csr(oct, CN6XXX_DMA_CNT(0))); in cn6xxx_read_csr_reg()
2957 CN6XXX_DMA_PKT_INT_LEVEL(0), octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2961 octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2965 octeon_read_csr(oct, CN6XXX_DMA_CNT(1))); in cn6xxx_read_csr_reg()
2969 octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2973 octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2980 reg = lio_pci_readq(oct, CN6XXX_BAR1_REG(i, oct->pcie_port)); in cn6xxx_read_csr_reg()
2982 CN6XXX_BAR1_REG(i, oct->pcie_port), i, reg); in cn6xxx_read_csr_reg()
2988 static int cn6xxx_read_config_reg(char *s, struct octeon_device *oct) in cn6xxx_read_config_reg() argument
2999 pci_read_config_dword(oct->pci_dev, (i * 4), &val); in cn6xxx_read_config_reg()
3005 pci_read_config_dword(oct->pci_dev, (i * 4), &val); in cn6xxx_read_config_reg()
3019 struct octeon_device *oct = lio->oct_dev; in lio_get_regs() local
3023 switch (oct->chip_id) { in lio_get_regs()
3026 len += cn23xx_read_csr_reg(regbuf + len, oct); in lio_get_regs()
3030 len += cn23xx_vf_read_csr_reg(regbuf + len, oct); in lio_get_regs()
3035 len += cn6xxx_read_csr_reg(regbuf + len, oct); in lio_get_regs()
3036 len += cn6xxx_read_config_reg(regbuf + len, oct); in lio_get_regs()
3039 dev_err(&oct->pci_dev->dev, "%s Unknown chipid: %d\n", in lio_get_regs()
3040 __func__, oct->chip_id); in lio_get_regs()
3065 struct octeon_device *oct = lio->oct_dev; in lio_get_fecparam() local
3070 if (oct->subsystem_id == OCTEON_CN2350_25GB_SUBSYS_ID || in lio_get_fecparam()
3071 oct->subsystem_id == OCTEON_CN2360_25GB_SUBSYS_ID) { in lio_get_fecparam()
3072 if (oct->no_speed_setting == 1) in lio_get_fecparam()
3077 if (oct->props[lio->ifidx].fec == 1) in lio_get_fecparam()
3090 struct octeon_device *oct = lio->oct_dev; in lio_set_fecparam() local
3092 if (oct->subsystem_id == OCTEON_CN2350_25GB_SUBSYS_ID || in lio_set_fecparam()
3093 oct->subsystem_id == OCTEON_CN2360_25GB_SUBSYS_ID) { in lio_set_fecparam()
3094 if (oct->no_speed_setting == 1) in lio_set_fecparam()
3176 struct octeon_device *oct = lio->oct_dev; in liquidio_set_ethtool_ops() local
3178 if (OCTEON_CN23XX_VF(oct)) in liquidio_set_ethtool_ops()