Lines Matching +full:0 +full:x27200
212 #define OCTNIC_NCMD_AUTONEG_ON 0x1
213 #define OCTNIC_NCMD_PHY_ON 0x2
270 if (oct->no_speed_setting == 0) { in lio_get_link_ksettings()
282 if (oct->no_speed_setting == 0) { in lio_get_link_ksettings()
391 return 0; in lio_get_link_ksettings()
425 return 0; in lio_set_link_ksettings()
432 return 0; in lio_set_link_ksettings()
444 memset(drvinfo, 0, sizeof(struct ethtool_drvinfo)); in lio_get_drvinfo()
460 memset(drvinfo, 0, sizeof(struct ethtool_drvinfo)); in lio_get_vf_drvinfo()
473 int ret = 0; in lio_send_queue_count_update()
475 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); in lio_send_queue_count_update()
477 nctrl.ncmd.u64 = 0; in lio_send_queue_count_update()
481 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; in lio_send_queue_count_update()
487 dev_err(&oct->pci_dev->dev, "Failed to send Queue reset command (ret: 0x%x)\n", in lio_send_queue_count_update()
492 return 0; in lio_send_queue_count_update()
501 u32 max_rx = 0, max_tx = 0, tx_count = 0, rx_count = 0; in lio_ethtool_get_channels()
502 u32 combined_count = 0, max_combined = 0; in lio_ethtool_get_channels()
522 u64 reg_val = 0ULL; in lio_ethtool_get_channels()
523 u64 ctrl = CN23XX_VF_SLI_IQ_PKT_CONTROL64(0); in lio_ethtool_get_channels()
543 int num_msix_irqs = 0; in lio_irq_reallocate_irqs()
547 return 0; in lio_irq_reallocate_irqs()
561 for (i = 0; i < num_msix_irqs; i++) { in lio_irq_reallocate_irqs()
568 oct->ioq_vector[i].vector = 0; in lio_irq_reallocate_irqs()
597 return 0; in lio_irq_reallocate_irqs()
607 int stopped = 0; in lio_ethtool_set_channels()
609 if (strcmp(oct->fw_info.liquidio_firmware_version, "1.6.1") < 0) { in lio_ethtool_set_channels()
632 u64 reg_val = 0ULL; in lio_ethtool_set_channels()
633 u64 ctrl = CN23XX_VF_SLI_IQ_PKT_CONTROL64(0); in lio_ethtool_set_channels()
646 return 0; in lio_ethtool_set_channels()
663 return 0; in lio_ethtool_set_channels()
700 return 0; in lio_get_eeprom()
708 int ret = 0; in octnet_gpio_access()
710 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); in octnet_gpio_access()
712 nctrl.ncmd.u64 = 0; in octnet_gpio_access()
716 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_gpio_access()
727 return 0; in octnet_gpio_access()
735 int ret = 0; in octnet_id_active()
737 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); in octnet_id_active()
739 nctrl.ncmd.u64 = 0; in octnet_id_active()
742 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_id_active()
753 return 0; in octnet_id_active()
766 int retval = 0; in octnet_mdio45_access()
771 sizeof(struct oct_mdio_cmd_resp), 0); in octnet_mdio45_access()
785 sc->iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_mdio45_access()
788 0, 0, 0); in octnet_mdio45_access()
804 retval = wait_for_sc_completion_timeout(oct_dev, sc, 0); in octnet_mdio45_access()
851 ret = octnet_mdio45_access(lio, 0, in lio_set_phys_id()
857 ret = octnet_mdio45_access(lio, 0, in lio_set_phys_id()
883 return 0; in lio_set_phys_id()
935 return 0; in lio_set_phys_id()
945 return 0; in lio_set_phys_id()
956 u32 tx_max_pending = 0, rx_max_pending = 0, tx_pending = 0, in lio_ethtool_get_ringparam()
957 rx_pending = 0; in lio_ethtool_get_ringparam()
972 rx_pending = oct->droq[0]->max_count; in lio_ethtool_get_ringparam()
973 tx_pending = oct->instr_queue[0]->max_count; in lio_ethtool_get_ringparam()
980 ering->rx_mini_pending = 0; in lio_ethtool_get_ringparam()
981 ering->rx_jumbo_pending = 0; in lio_ethtool_get_ringparam()
982 ering->rx_mini_max_pending = 0; in lio_ethtool_get_ringparam()
983 ering->rx_jumbo_max_pending = 0; in lio_ethtool_get_ringparam()
1002 resp_size, 0); in lio_23xx_reconfigure_queue_count()
1018 if_cfg.u64 = 0; in lio_23xx_reconfigure_queue_count()
1024 sc->iq_no = 0; in lio_23xx_reconfigure_queue_count()
1026 OPCODE_NIC_QCOUNT_UPDATE, 0, in lio_23xx_reconfigure_queue_count()
1027 if_cfg.u64, 0); in lio_23xx_reconfigure_queue_count()
1041 retval = wait_for_sc_completion_timeout(oct, sc, 0); in lio_23xx_reconfigure_queue_count()
1059 for (j = 0; j < lio->linfo.num_rxpciq; j++) { in lio_23xx_reconfigure_queue_count()
1064 for (j = 0; j < lio->linfo.num_txpciq; j++) { in lio_23xx_reconfigure_queue_count()
1072 lio->txq = lio->linfo.txpciq[0].s.q_no; in lio_23xx_reconfigure_queue_count()
1073 lio->rxq = lio->linfo.rxpciq[0].s.q_no; in lio_23xx_reconfigure_queue_count()
1080 return 0; in lio_23xx_reconfigure_queue_count()
1087 int i, queue_count_update = 0; in lio_reset_queues()
1151 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct); i++) { in lio_reset_queues()
1157 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct); i++) { in lio_reset_queues()
1215 for (i = 0; i < oct->num_oqs; i++) in lio_reset_queues()
1230 if (liquidio_setup_io_queues(oct, 0, num_qs, num_qs)) { in lio_reset_queues()
1254 return 0; in lio_reset_queues()
1266 int stopped = 0; in lio_ethtool_set_ringparam()
1279 rx_count_old = oct->droq[0]->max_count; in lio_ethtool_set_ringparam()
1280 tx_count_old = oct->instr_queue[0]->max_count; in lio_ethtool_set_ringparam()
1283 return 0; in lio_ethtool_set_ringparam()
1308 return 0; in lio_ethtool_set_ringparam()
1334 OCTNET_CMD_VERBOSE_ENABLE, 0); in lio_set_msglevel()
1337 OCTNET_CMD_VERBOSE_DISABLE, 0); in lio_set_msglevel()
1359 pause->autoneg = 0; in lio_get_pauseparam()
1376 int ret = 0; in lio_set_pauseparam()
1381 if (linfo->link.s.duplex == 0) { in lio_set_pauseparam()
1391 memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt)); in lio_set_pauseparam()
1393 nctrl.ncmd.u64 = 0; in lio_set_pauseparam()
1395 nctrl.iq_no = lio->linfo.txpciq[0].s.q_no; in lio_set_pauseparam()
1404 nctrl.ncmd.s.param1 = 0; in lio_set_pauseparam()
1412 nctrl.ncmd.s.param2 = 0; in lio_set_pauseparam()
1425 return 0; in lio_set_pauseparam()
1436 int i = 0, j; in lio_get_ethtool_stats()
1637 for (j = 0; j < MAX_OCTEON_INSTR_QUEUES(oct_dev); j++) { in lio_get_ethtool_stats()
1680 for (j = 0; j < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); j++) { in lio_get_ethtool_stats()
1725 int i = 0, j, vj; in lio_vf_get_ethtool_stats()
1759 for (vj = 0; vj < oct_dev->num_iqs; vj++) { in lio_vf_get_ethtool_stats()
1801 for (vj = 0; vj < oct_dev->num_oqs; vj++) { in lio_vf_get_ethtool_stats()
1838 for (i = 0; i < ARRAY_SIZE(oct_priv_flags_strings); i++) { in lio_get_priv_flags_strings()
1862 for (j = 0; j < num_stats; j++) { in lio_get_strings()
1868 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct_dev); i++) { in lio_get_strings()
1871 for (j = 0; j < num_iq_stats; j++) { in lio_get_strings()
1879 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); i++) { in lio_get_strings()
1882 for (j = 0; j < num_oq_stats; j++) { in lio_get_strings()
1910 for (j = 0; j < num_stats; j++) { in lio_vf_get_strings()
1916 for (i = 0; i < MAX_OCTEON_INSTR_QUEUES(oct_dev); i++) { in lio_vf_get_strings()
1919 for (j = 0; j < num_iq_stats; j++) { in lio_vf_get_strings()
1927 for (i = 0; i < MAX_OCTEON_OUTPUT_QUEUES(oct_dev); i++) { in lio_vf_get_strings()
1930 for (j = 0; j < num_oq_stats; j++) { in lio_vf_get_strings()
2010 0, in octnet_get_intrmod_cfg()
2011 sizeof(struct oct_intrmod_resp), 0); in octnet_get_intrmod_cfg()
2017 memset(resp, 0, sizeof(struct oct_intrmod_resp)); in octnet_get_intrmod_cfg()
2019 sc->iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_get_intrmod_cfg()
2022 OPCODE_NIC_INTRMOD_PARAMS, 0, 0, 0); in octnet_get_intrmod_cfg()
2036 retval = wait_for_sc_completion_timeout(oct_dev, sc, 0); in octnet_get_intrmod_cfg()
2052 return 0; in octnet_get_intrmod_cfg()
2068 16, 0); in octnet_set_intrmod_cfg()
2078 sc->iq_no = lio->linfo.txpciq[0].s.q_no; in octnet_set_intrmod_cfg()
2081 OPCODE_NIC_INTRMOD_CFG, 0, 0, 0); in octnet_set_intrmod_cfg()
2095 retval = wait_for_sc_completion_timeout(oct_dev, sc, 0); in octnet_set_intrmod_cfg()
2100 if (retval == 0) { in octnet_set_intrmod_cfg()
2106 return 0; in octnet_set_intrmod_cfg()
2152 iq = oct->instr_queue[lio->linfo.txpciq[0].s.q_no]; in lio_get_intr_coalesce()
2187 return 0; in lio_get_intr_coalesce()
2195 int ret = 0; in oct_cfg_adaptive_intr()
2257 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrcnt()
2263 (0x3fffff00000000UL)) | in oct_cfg_rx_intrcnt()
2279 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrcnt()
2284 (0x3fffff00000000UL)) | in oct_cfg_rx_intrcnt()
2295 return 0; in oct_cfg_rx_intrcnt()
2335 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrtime()
2358 for (q_no = 0; q_no < oct->num_oqs; q_no++) { in oct_cfg_rx_intrtime()
2373 return 0; in oct_cfg_rx_intrtime()
2401 for (q_no = 0; q_no < oct->num_iqs; q_no++) { in oct_cfg_tx_intrcnt()
2405 val = (val & 0xFFFF000000000000ULL) | in oct_cfg_tx_intrcnt()
2418 return 0; in oct_cfg_tx_intrcnt()
2429 struct oct_intrmod_cfg intrmod = {0}; in lio_set_intr_coalesce()
2440 for (j = 0; j < lio->linfo.num_txpciq; j++) { in lio_set_intr_coalesce()
2460 intrmod.rx_enable = intr_coal->use_adaptive_rx_coalesce ? 1 : 0; in lio_set_intr_coalesce()
2461 intrmod.tx_enable = intr_coal->use_adaptive_tx_coalesce ? 1 : 0; in lio_set_intr_coalesce()
2492 return 0; in lio_set_intr_coalesce()
2526 return 0; in lio_get_ts_info()
2549 int len = 0; in cn23xx_read_csr_reg()
2556 /*0x29030 or 0x29040*/ in cn23xx_read_csr_reg()
2563 /*0x27080 or 0x27090*/ in cn23xx_read_csr_reg()
2570 /*0x27000 or 0x27010*/ in cn23xx_read_csr_reg()
2577 /*0x29120*/ in cn23xx_read_csr_reg()
2578 reg = 0x29120; in cn23xx_read_csr_reg()
2582 /*0x27300*/ in cn23xx_read_csr_reg()
2583 reg = 0x27300 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + in cn23xx_read_csr_reg()
2589 /*0x27200*/ in cn23xx_read_csr_reg()
2590 reg = 0x27200 + oct->pcie_port * CN23XX_MAC_INT_OFFSET + in cn23xx_read_csr_reg()
2602 /*0x29140*/ in cn23xx_read_csr_reg()
2607 /*0x29160*/ in cn23xx_read_csr_reg()
2608 reg = 0x29160; in cn23xx_read_csr_reg()
2612 /*0x29180*/ in cn23xx_read_csr_reg()
2617 /*0x291E0*/ in cn23xx_read_csr_reg()
2622 /*0x29210*/ in cn23xx_read_csr_reg()
2628 /*0x29220*/ in cn23xx_read_csr_reg()
2629 reg = 0x29220; in cn23xx_read_csr_reg()
2634 if (pf_num == 0) { in cn23xx_read_csr_reg()
2635 /*0x29260*/ in cn23xx_read_csr_reg()
2641 /*0x29270*/ in cn23xx_read_csr_reg()
2648 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2655 /*0x10040*/ in cn23xx_read_csr_reg()
2656 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2663 /*0x10080*/ in cn23xx_read_csr_reg()
2664 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2671 /*0x10090*/ in cn23xx_read_csr_reg()
2672 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2679 /*0x10050*/ in cn23xx_read_csr_reg()
2680 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2688 /*0x10070*/ in cn23xx_read_csr_reg()
2689 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2696 /*0x100a0*/ in cn23xx_read_csr_reg()
2697 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2704 /*0x100b0*/ in cn23xx_read_csr_reg()
2705 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2711 /*0x100c0*/ in cn23xx_read_csr_reg()
2712 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2713 reg = 0x100c0 + i * CN23XX_OQ_OFFSET; in cn23xx_read_csr_reg()
2718 /*0x10000*/ in cn23xx_read_csr_reg()
2719 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2727 /*0x10010*/ in cn23xx_read_csr_reg()
2728 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2736 /*0x10020*/ in cn23xx_read_csr_reg()
2737 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2745 /*0x10030*/ in cn23xx_read_csr_reg()
2746 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) { in cn23xx_read_csr_reg()
2754 /*0x10040*/ in cn23xx_read_csr_reg()
2755 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) in cn23xx_read_csr_reg()
2767 int len = 0; in cn23xx_vf_read_csr_reg()
2775 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2782 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2789 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2796 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2803 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2810 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2817 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2824 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2830 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2831 reg = 0x100c0 + i * CN23XX_VF_OQ_OFFSET; in cn23xx_vf_read_csr_reg()
2837 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2838 reg = 0x100d0 + i * CN23XX_VF_IQ_OFFSET; in cn23xx_vf_read_csr_reg()
2844 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2851 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2858 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2865 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2872 for (i = 0; i < (oct->sriov_info.rings_per_vf); i++) { in cn23xx_vf_read_csr_reg()
2885 int i, len = 0; in cn6xxx_read_csr_reg()
2913 len += sprintf(s + len, "\n[%x] (INT_ENABLE PORT 0): %08x\n", in cn6xxx_read_csr_reg()
2923 for (i = 0; i < oct->num_oqs; i++) { in cn6xxx_read_csr_reg()
2939 for (i = 0; i <= 3; i++) { in cn6xxx_read_csr_reg()
2953 CN6XXX_DMA_CNT(0), in cn6xxx_read_csr_reg()
2954 octeon_read_csr(oct, CN6XXX_DMA_CNT(0))); in cn6xxx_read_csr_reg()
2955 reg = CN6XXX_DMA_PKT_INT_LEVEL(0); in cn6xxx_read_csr_reg()
2957 CN6XXX_DMA_PKT_INT_LEVEL(0), octeon_read_csr(oct, reg)); in cn6xxx_read_csr_reg()
2958 reg = CN6XXX_DMA_TIME_INT_LEVEL(0); in cn6xxx_read_csr_reg()
2960 CN6XXX_DMA_TIME_INT_LEVEL(0), in cn6xxx_read_csr_reg()
2979 for (i = 0; i < 16; i++) { in cn6xxx_read_csr_reg()
2991 int i, len = 0; in cn6xxx_read_config_reg()
2998 for (i = 0; i <= 13; i++) { in cn6xxx_read_config_reg()
3000 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n", in cn6xxx_read_config_reg()
3006 len += sprintf(s + len, "[0x%x] (Config[%d]): 0x%08x\n", in cn6xxx_read_config_reg()
3018 int len = 0; in lio_get_regs()
3025 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN_23XX); in lio_get_regs()
3029 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN_23XX_VF); in lio_get_regs()
3034 memset(regbuf, 0, OCT_ETHTOOL_REGDUMP_LEN); in lio_get_regs()
3054 bool intr_by_tx_bytes = !!(flags & (0x1 << OCT_PRIV_FLAG_TX_BYTES)); in lio_set_priv_flags()
3058 return 0; in lio_set_priv_flags()
3073 return 0; in lio_get_fecparam()
3083 return 0; in lio_get_fecparam()
3098 liquidio_set_fec(lio, 0); in lio_set_fecparam()
3107 return 0; in lio_set_fecparam()