Lines Matching refs:rb
49 static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb,
51 static enum bfa_status bfa_ioc_ct2_pll_init(void __iomem *rb,
251 void __iomem *rb; in bfa_ioc_ct_reg_init() local
254 rb = bfa_ioc_bar0(ioc); in bfa_ioc_ct_reg_init()
256 ioc->ioc_regs.hfn_mbox = rb + ct_fnreg[pcifn].hfn_mbox; in bfa_ioc_ct_reg_init()
257 ioc->ioc_regs.lpu_mbox = rb + ct_fnreg[pcifn].lpu_mbox; in bfa_ioc_ct_reg_init()
258 ioc->ioc_regs.host_page_num_fn = rb + ct_fnreg[pcifn].hfn_pgn; in bfa_ioc_ct_reg_init()
261 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; in bfa_ioc_ct_reg_init()
262 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; in bfa_ioc_ct_reg_init()
263 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG; in bfa_ioc_ct_reg_init()
264 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p0reg[pcifn].hfn; in bfa_ioc_ct_reg_init()
265 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p0reg[pcifn].lpu; in bfa_ioc_ct_reg_init()
266 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct_reg_init()
267 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct_reg_init()
269 ioc->ioc_regs.heartbeat = rb + BFA_IOC1_HBEAT_REG; in bfa_ioc_ct_reg_init()
270 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC1_STATE_REG; in bfa_ioc_ct_reg_init()
271 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG; in bfa_ioc_ct_reg_init()
272 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn; in bfa_ioc_ct_reg_init()
273 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu; in bfa_ioc_ct_reg_init()
274 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct_reg_init()
275 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct_reg_init()
281 ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG; in bfa_ioc_ct_reg_init()
282 ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG; in bfa_ioc_ct_reg_init()
283 ioc->ioc_regs.app_pll_fast_ctl_reg = rb + APP_PLL_LCLK_CTL_REG; in bfa_ioc_ct_reg_init()
284 ioc->ioc_regs.app_pll_slow_ctl_reg = rb + APP_PLL_SCLK_CTL_REG; in bfa_ioc_ct_reg_init()
289 ioc->ioc_regs.ioc_sem_reg = rb + HOST_SEM0_REG; in bfa_ioc_ct_reg_init()
290 ioc->ioc_regs.ioc_usage_sem_reg = rb + HOST_SEM1_REG; in bfa_ioc_ct_reg_init()
291 ioc->ioc_regs.ioc_init_sem_reg = rb + HOST_SEM2_REG; in bfa_ioc_ct_reg_init()
292 ioc->ioc_regs.ioc_usage_reg = rb + BFA_FW_USE_COUNT; in bfa_ioc_ct_reg_init()
293 ioc->ioc_regs.ioc_fail_sync = rb + BFA_IOC_FAIL_SYNC; in bfa_ioc_ct_reg_init()
298 ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START; in bfa_ioc_ct_reg_init()
304 ioc->ioc_regs.err_set = (rb + ERR_SET_REG); in bfa_ioc_ct_reg_init()
310 void __iomem *rb; in bfa_ioc_ct2_reg_init() local
313 rb = bfa_ioc_bar0(ioc); in bfa_ioc_ct2_reg_init()
315 ioc->ioc_regs.hfn_mbox = rb + ct2_reg[port].hfn_mbox; in bfa_ioc_ct2_reg_init()
316 ioc->ioc_regs.lpu_mbox = rb + ct2_reg[port].lpu_mbox; in bfa_ioc_ct2_reg_init()
317 ioc->ioc_regs.host_page_num_fn = rb + ct2_reg[port].hfn_pgn; in bfa_ioc_ct2_reg_init()
318 ioc->ioc_regs.hfn_mbox_cmd = rb + ct2_reg[port].hfn; in bfa_ioc_ct2_reg_init()
319 ioc->ioc_regs.lpu_mbox_cmd = rb + ct2_reg[port].lpu; in bfa_ioc_ct2_reg_init()
320 ioc->ioc_regs.lpu_read_stat = rb + ct2_reg[port].lpu_read; in bfa_ioc_ct2_reg_init()
323 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC0_HBEAT_REG; in bfa_ioc_ct2_reg_init()
324 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG; in bfa_ioc_ct2_reg_init()
325 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG; in bfa_ioc_ct2_reg_init()
326 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct2_reg_init()
327 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct2_reg_init()
329 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC1_HBEAT_REG; in bfa_ioc_ct2_reg_init()
330 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG; in bfa_ioc_ct2_reg_init()
331 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG; in bfa_ioc_ct2_reg_init()
332 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct2_reg_init()
333 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct2_reg_init()
339 ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG; in bfa_ioc_ct2_reg_init()
340 ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG; in bfa_ioc_ct2_reg_init()
341 ioc->ioc_regs.app_pll_fast_ctl_reg = rb + CT2_APP_PLL_LCLK_CTL_REG; in bfa_ioc_ct2_reg_init()
342 ioc->ioc_regs.app_pll_slow_ctl_reg = rb + CT2_APP_PLL_SCLK_CTL_REG; in bfa_ioc_ct2_reg_init()
347 ioc->ioc_regs.ioc_sem_reg = rb + CT2_HOST_SEM0_REG; in bfa_ioc_ct2_reg_init()
348 ioc->ioc_regs.ioc_usage_sem_reg = rb + CT2_HOST_SEM1_REG; in bfa_ioc_ct2_reg_init()
349 ioc->ioc_regs.ioc_init_sem_reg = rb + CT2_HOST_SEM2_REG; in bfa_ioc_ct2_reg_init()
350 ioc->ioc_regs.ioc_usage_reg = rb + CT2_BFA_FW_USE_COUNT; in bfa_ioc_ct2_reg_init()
351 ioc->ioc_regs.ioc_fail_sync = rb + CT2_BFA_IOC_FAIL_SYNC; in bfa_ioc_ct2_reg_init()
356 ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START; in bfa_ioc_ct2_reg_init()
362 ioc->ioc_regs.err_set = rb + ERR_SET_REG; in bfa_ioc_ct2_reg_init()
371 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct_map_port() local
377 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_map_port()
386 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct2_map_port() local
389 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0); in bfa_ioc_ct2_map_port()
397 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct_isr_mode_set() local
400 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
419 writel(r32, rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
447 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_nw_ioc_ct2_poweron() local
450 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_nw_ioc_ct2_poweron()
453 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR); in bfa_nw_ioc_ct2_poweron()
459 rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_nw_ioc_ct2_poweron()
461 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR); in bfa_nw_ioc_ct2_poweron()
601 bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) in bfa_ioc_ct_pll_init() argument
616 writel(0, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
620 (rb + ETH_MAC_SER_REG)); in bfa_ioc_ct_pll_init()
622 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
624 (rb + ETH_MAC_SER_REG)); in bfa_ioc_ct_pll_init()
626 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); in bfa_ioc_ct_pll_init()
627 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); in bfa_ioc_ct_pll_init()
628 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); in bfa_ioc_ct_pll_init()
629 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); in bfa_ioc_ct_pll_init()
630 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); in bfa_ioc_ct_pll_init()
631 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); in bfa_ioc_ct_pll_init()
632 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); in bfa_ioc_ct_pll_init()
633 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); in bfa_ioc_ct_pll_init()
636 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
639 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
642 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
645 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
646 readl(rb + HOSTFN0_INT_MSK); in bfa_ioc_ct_pll_init()
648 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); in bfa_ioc_ct_pll_init()
649 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); in bfa_ioc_ct_pll_init()
652 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
655 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
658 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0)); in bfa_ioc_ct_pll_init()
659 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1)); in bfa_ioc_ct_pll_init()
661 r32 = readl(rb + PSS_CTL_REG); in bfa_ioc_ct_pll_init()
663 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct_pll_init()
666 writel(0, (rb + PMM_1T_RESET_REG_P0)); in bfa_ioc_ct_pll_init()
667 writel(0, (rb + PMM_1T_RESET_REG_P1)); in bfa_ioc_ct_pll_init()
670 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
672 r32 = readl(rb + MBIST_STAT_REG); in bfa_ioc_ct_pll_init()
673 writel(0, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
678 bfa_ioc_ct2_sclk_init(void __iomem *rb) in bfa_ioc_ct2_sclk_init() argument
685 r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_sclk_init()
689 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
695 r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_sclk_init()
697 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
702 r32 = readl(rb + CT2_CHIP_MISC_PRG); in bfa_ioc_ct2_sclk_init()
704 rb + CT2_CHIP_MISC_PRG); in bfa_ioc_ct2_sclk_init()
706 r32 = readl(rb + CT2_PCIE_MISC_REG); in bfa_ioc_ct2_sclk_init()
708 rb + CT2_PCIE_MISC_REG); in bfa_ioc_ct2_sclk_init()
713 r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_sclk_init()
716 writel(r32 | 0x1061731b, rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_sclk_init()
730 bfa_ioc_ct2_lclk_init(void __iomem *rb) in bfa_ioc_ct2_lclk_init() argument
737 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_lclk_init()
741 writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_lclk_init()
746 r32 = readl(rb + CT2_CHIP_MISC_PRG); in bfa_ioc_ct2_lclk_init()
747 writel(r32, (rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_lclk_init()
752 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_lclk_init()
753 writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_lclk_init()
758 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_lclk_init()
761 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
770 bfa_ioc_ct2_mem_init(void __iomem *rb) in bfa_ioc_ct2_mem_init() argument
774 r32 = readl(rb + PSS_CTL_REG); in bfa_ioc_ct2_mem_init()
776 writel(r32, rb + PSS_CTL_REG); in bfa_ioc_ct2_mem_init()
779 writel(__EDRAM_BISTR_START, rb + CT2_MBIST_CTL_REG); in bfa_ioc_ct2_mem_init()
781 writel(0, rb + CT2_MBIST_CTL_REG); in bfa_ioc_ct2_mem_init()
785 bfa_ioc_ct2_mac_reset(void __iomem *rb) in bfa_ioc_ct2_mac_reset() argument
789 bfa_ioc_ct2_sclk_init(rb); in bfa_ioc_ct2_mac_reset()
790 bfa_ioc_ct2_lclk_init(rb); in bfa_ioc_ct2_mac_reset()
795 r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_mac_reset()
797 rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_mac_reset()
802 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_mac_reset()
804 rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_mac_reset()
808 rb + CT2_CSI_MAC_CONTROL_REG(0)); in bfa_ioc_ct2_mac_reset()
810 rb + CT2_CSI_MAC_CONTROL_REG(1)); in bfa_ioc_ct2_mac_reset()
818 bfa_ioc_ct2_nfc_halted(void __iomem *rb) in bfa_ioc_ct2_nfc_halted() argument
822 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_halted()
830 bfa_ioc_ct2_nfc_resume(void __iomem *rb) in bfa_ioc_ct2_nfc_resume() argument
835 writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_CLR_REG); in bfa_ioc_ct2_nfc_resume()
837 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_resume()
846 bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) in bfa_ioc_ct2_pll_init() argument
851 wgn = readl(rb + CT2_WGN_STATUS); in bfa_ioc_ct2_pll_init()
853 nfc_ver = readl(rb + CT2_RSC_GPR15_REG); in bfa_ioc_ct2_pll_init()
857 if (bfa_ioc_ct2_nfc_halted(rb)) in bfa_ioc_ct2_pll_init()
858 bfa_ioc_ct2_nfc_resume(rb); in bfa_ioc_ct2_pll_init()
860 rb + CT2_CSI_FW_CTL_SET_REG); in bfa_ioc_ct2_pll_init()
863 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
870 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
877 r32 = readl(rb + CT2_CSI_FW_CTL_REG); in bfa_ioc_ct2_pll_init()
880 writel(__HALT_NFC_CONTROLLER, (rb + CT2_NFC_CSR_SET_REG)); in bfa_ioc_ct2_pll_init()
882 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_pll_init()
888 bfa_ioc_ct2_mac_reset(rb); in bfa_ioc_ct2_pll_init()
889 bfa_ioc_ct2_sclk_init(rb); in bfa_ioc_ct2_pll_init()
890 bfa_ioc_ct2_lclk_init(rb); in bfa_ioc_ct2_pll_init()
893 r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
895 rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
896 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
898 rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
903 r32 = readl(rb + PSS_GPIO_OUT_REG); in bfa_ioc_ct2_pll_init()
904 writel(r32 & ~1, rb + PSS_GPIO_OUT_REG); in bfa_ioc_ct2_pll_init()
905 r32 = readl(rb + PSS_GPIO_OE_REG); in bfa_ioc_ct2_pll_init()
906 writel(r32 | 1, rb + PSS_GPIO_OE_REG); in bfa_ioc_ct2_pll_init()
913 writel(1, rb + CT2_LPU0_HOSTFN_MBOX0_MSK); in bfa_ioc_ct2_pll_init()
914 writel(1, rb + CT2_LPU1_HOSTFN_MBOX0_MSK); in bfa_ioc_ct2_pll_init()
917 r32 = readl(rb + HOST_SEM5_REG); in bfa_ioc_ct2_pll_init()
919 r32 = readl(rb + CT2_LPU0_HOSTFN_CMD_STAT); in bfa_ioc_ct2_pll_init()
921 writel(1, rb + CT2_LPU0_HOSTFN_CMD_STAT); in bfa_ioc_ct2_pll_init()
922 readl(rb + CT2_LPU0_HOSTFN_CMD_STAT); in bfa_ioc_ct2_pll_init()
924 r32 = readl(rb + CT2_LPU1_HOSTFN_CMD_STAT); in bfa_ioc_ct2_pll_init()
926 writel(1, rb + CT2_LPU1_HOSTFN_CMD_STAT); in bfa_ioc_ct2_pll_init()
927 readl(rb + CT2_LPU1_HOSTFN_CMD_STAT); in bfa_ioc_ct2_pll_init()
931 bfa_ioc_ct2_mem_init(rb); in bfa_ioc_ct2_pll_init()
933 writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC0_STATE_REG); in bfa_ioc_ct2_pll_init()
934 writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC1_STATE_REG); in bfa_ioc_ct2_pll_init()