ethernet/broadcom/tg3.c

622 #define tw32_f(reg, val)		_tw32_flush(tp, (reg), (val), 0)
642 		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
643 		tw32_f(TG3PCI_MEM_WIN_DATA, val);
646 		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
669 		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
673 		tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
1126 		tw32_f(MAC_MI_MODE,
1141 	tw32_f(MAC_MI_COM, frame_val);
1163 		tw32_f(MAC_MI_MODE, tp->mi_mode);
1189 		tw32_f(MAC_MI_MODE,
1203 	tw32_f(MAC_MI_COM, frame_val);
1222 		tw32_f(MAC_MI_MODE, tp->mi_mode);
1497 	tw32_f(MAC_MI_MODE, tp->mi_mode);
1621 	tw32_f(GRC_RX_CPU_EVENT, val);
1989 		tw32_f(MAC_RX_MODE, tp->rx_mode);
1997 		tw32_f(MAC_TX_MODE, tp->tx_mode);
2044 		tw32_f(MAC_MODE, tp->mac_mode);
2636 		tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
2685 			tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3079 		tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
3124 		tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
3160 			tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
3532 		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
3569 		tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
3605 	tw32_f(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
3621 	tw32_f(cpu_base + CPU_MODE,  0x00000000);
3768 	tw32_f(cpu_base + CPU_PC, pc);
3775 		tw32_f(cpu_base + CPU_PC, pc);
4178 		tw32_f(MAC_MODE, mac_mode);
4181 		tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
4731 	tw32_f(MAC_STATUS,
4748 	tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL, val);
4750 	tw32_f(TG3_CPMU_EEE_CTRL,
4764 	tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0);
4766 	tw32_f(TG3_CPMU_EEE_DBTMR1,
4770 	tw32_f(TG3_CPMU_EEE_DBTMR2,
4787 		tw32_f(MAC_MI_MODE,
5041 		tw32_f(MAC_MI_MODE, tp->mi_mode);
5045 	tw32_f(MAC_MODE, tp->mac_mode);
5052 		tw32_f(MAC_EVENT, 0);
5054 		tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5063 		tw32_f(MAC_STATUS,
5233 		tw32_f(MAC_MODE, tp->mac_mode);
5262 		tw32_f(MAC_MODE, tp->mac_mode);
5277 		tw32_f(MAC_MODE, tp->mac_mode);
5363 		tw32_f(MAC_MODE, tp->mac_mode);
5412 	tw32_f(MAC_TX_AUTO_NEG, 0);
5415 	tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
5418 	tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
5435 	tw32_f(MAC_MODE, tp->mac_mode);
5534 				tw32_f(MAC_SERDES_CFG, val);
5537 			tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5567 			tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
5568 		tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
5570 		tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
5612 					tw32_f(MAC_SERDES_CFG, val);
5615 				tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
5676 			tw32_f(MAC_STATUS,
5697 		tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
5700 		tw32_f(MAC_MODE, tp->mac_mode);
5731 			tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5737 	tw32_f(MAC_TX_AUTO_NEG, 0);
5741 	tw32_f(MAC_MODE, tp->mac_mode);
5748 	tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5764 		tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
5778 			tw32_f(MAC_MODE, (tp->mac_mode |
5781 			tw32_f(MAC_MODE, tp->mac_mode);
5850 		tw32_f(MAC_MODE, tp->mac_mode);
5859 	tw32_f(MAC_MODE, tp->mac_mode);
5900 			tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
5992 	tw32_f(MAC_MODE, tp->mac_mode);
5995 	tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
6151 	tw32_f(TG3_EAV_REF_CLCK_CTL, clock_ctl | TG3_EAV_REF_CLCK_CTL_RESUME);
7024 				tw32_f(MAC_STATUS,
7206 			tw32_f(HOSTCC_MODE, tp->coal_now);
8255 		tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8257 		tw32_f(MAC_RX_MODE, tp->rx_mode);
8845 	tw32_f(ofs, val);
8887 	tw32_f(MAC_RX_MODE, tp->rx_mode);
8906 	tw32_f(MAC_MODE, tp->mac_mode);
8910 	tw32_f(MAC_TX_MODE, tp->tx_mode);
9277 	tw32_f(MAC_MODE, val);
9807 		tw32_f(MAC_RX_MODE, rx_mode);
10006 		tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
10424 		tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10437 	tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
10468 	tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
10482 		tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
10511 	tw32_f(WDMAC_MODE, val);
10530 	tw32_f(RDMAC_MODE, rdmac_mode);
10606 	tw32_f(MAC_TX_MODE, tp->tx_mode);
10635 	tw32_f(MAC_RX_MODE, tp->rx_mode);
10642 		tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10645 	tw32_f(MAC_RX_MODE, tp->rx_mode);
10669 	tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
11061 					tw32_f(MAC_MODE,
11065 					tw32_f(MAC_MODE, tp->mac_mode);
11308 	tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13516 	tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
13543 		tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
14998 	tw32_f(GRC_EEPROM_ADDR,
15006 	tw32_f(GRC_LOCAL_CTRL,
16972 			tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
17206 		tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
17211 		tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);