Lines Matching refs:tp
92 #define tg3_flag(tp, flag) \ argument
93 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
94 #define tg3_flag_set(tp, flag) \ argument
95 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
96 #define tg3_flag_clear(tp, flag) \ argument
97 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
130 #define TG3_MAX_MTU(tp) \ argument
131 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
137 #define TG3_RX_STD_RING_SIZE(tp) \ argument
138 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 #define TG3_RX_JMB_RING_SIZE(tp) \ argument
142 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
156 #define TG3_RX_STD_RING_BYTES(tp) \ argument
157 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
158 #define TG3_RX_JMB_RING_BYTES(tp) \ argument
159 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
160 #define TG3_RX_RCB_RING_BYTES(tp) \ argument
161 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
176 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ argument
177 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
179 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ argument
180 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
195 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD argument
197 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) argument
201 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset) argument
203 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD) argument
213 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3) argument
214 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1) argument
470 static void tg3_write32(struct tg3 *tp, u32 off, u32 val) in tg3_write32() argument
472 writel(val, tp->regs + off); in tg3_write32()
475 static u32 tg3_read32(struct tg3 *tp, u32 off) in tg3_read32() argument
477 return readl(tp->regs + off); in tg3_read32()
480 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) in tg3_ape_write32() argument
482 writel(val, tp->aperegs + off); in tg3_ape_write32()
485 static u32 tg3_ape_read32(struct tg3 *tp, u32 off) in tg3_ape_read32() argument
487 return readl(tp->aperegs + off); in tg3_ape_read32()
490 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) in tg3_write_indirect_reg32() argument
494 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
495 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
497 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
500 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) in tg3_write_flush_reg32() argument
502 writel(val, tp->regs + off); in tg3_write_flush_reg32()
503 readl(tp->regs + off); in tg3_write_flush_reg32()
506 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) in tg3_read_indirect_reg32() argument
511 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
512 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
513 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
514 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
518 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) in tg3_write_indirect_mbox() argument
523 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
528 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
533 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
534 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
536 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
543 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
544 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
548 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) in tg3_read_indirect_mbox() argument
553 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
554 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
555 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
556 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
565 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) in _tw32_flush() argument
567 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) in _tw32_flush()
569 tp->write32(tp, off, val); in _tw32_flush()
572 tg3_write32(tp, off, val); in _tw32_flush()
575 tp->read32(tp, off); in _tw32_flush()
584 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) in tw32_mailbox_flush() argument
586 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
587 if (tg3_flag(tp, FLUSH_POSTED_WRITES) || in tw32_mailbox_flush()
588 (!tg3_flag(tp, MBOX_WRITE_REORDER) && in tw32_mailbox_flush()
589 !tg3_flag(tp, ICH_WORKAROUND))) in tw32_mailbox_flush()
590 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
593 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) in tg3_write32_tx_mbox() argument
595 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
597 if (tg3_flag(tp, TXD_MBOX_HWBUG)) in tg3_write32_tx_mbox()
599 if (tg3_flag(tp, MBOX_WRITE_REORDER) || in tg3_write32_tx_mbox()
600 tg3_flag(tp, FLUSH_POSTED_WRITES)) in tg3_write32_tx_mbox()
604 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) in tg3_read32_mbox_5906() argument
606 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
609 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) in tg3_write32_mbox_5906() argument
611 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
614 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
615 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
616 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
617 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
618 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
620 #define tw32(reg, val) tp->write32(tp, reg, val)
621 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
622 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
623 #define tr32(reg) tp->read32(tp, reg)
625 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) in tg3_write_mem() argument
629 if (tg3_asic_rev(tp) == ASIC_REV_5906 && in tg3_write_mem()
633 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
634 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_write_mem()
635 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
639 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
647 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
650 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) in tg3_read_mem() argument
654 if (tg3_asic_rev(tp) == ASIC_REV_5906 && in tg3_read_mem()
660 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
661 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_read_mem()
662 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
663 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
666 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
674 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
677 static void tg3_ape_lock_init(struct tg3 *tp) in tg3_ape_lock_init() argument
682 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_lock_init()
697 if (!tp->pci_fn) in tg3_ape_lock_init()
700 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
702 tg3_ape_write32(tp, regbase + 4 * i, bit); in tg3_ape_lock_init()
707 static int tg3_ape_lock(struct tg3 *tp, int locknum) in tg3_ape_lock() argument
713 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_lock()
718 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_lock()
723 if (!tp->pci_fn) in tg3_ape_lock()
726 bit = 1 << tp->pci_fn; in tg3_ape_lock()
738 if (tg3_asic_rev(tp) == ASIC_REV_5761) { in tg3_ape_lock()
748 tg3_ape_write32(tp, req + off, bit); in tg3_ape_lock()
752 status = tg3_ape_read32(tp, gnt + off); in tg3_ape_lock()
755 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
763 tg3_ape_write32(tp, gnt + off, bit); in tg3_ape_lock()
770 static void tg3_ape_unlock(struct tg3 *tp, int locknum) in tg3_ape_unlock() argument
774 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_unlock()
779 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_unlock()
784 if (!tp->pci_fn) in tg3_ape_unlock()
787 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
799 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_unlock()
804 tg3_ape_write32(tp, gnt + 4 * locknum, bit); in tg3_ape_unlock()
807 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us) in tg3_ape_event_lock() argument
812 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) in tg3_ape_event_lock()
815 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); in tg3_ape_event_lock()
819 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_event_lock()
829 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us) in tg3_ape_wait_for_event() argument
834 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); in tg3_ape_wait_for_event()
845 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, in tg3_ape_scratchpad_read() argument
851 if (!tg3_flag(tp, APE_HAS_NCSI)) in tg3_ape_scratchpad_read()
854 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_ape_scratchpad_read()
858 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_scratchpad_read()
862 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) + in tg3_ape_scratchpad_read()
865 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN); in tg3_ape_scratchpad_read()
874 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_scratchpad_read()
879 err = tg3_ape_event_lock(tp, 1000); in tg3_ape_scratchpad_read()
886 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata); in tg3_ape_scratchpad_read()
888 tg3_ape_write32(tp, bufoff, base_off); in tg3_ape_scratchpad_read()
889 tg3_ape_write32(tp, bufoff + sizeof(u32), length); in tg3_ape_scratchpad_read()
891 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_scratchpad_read()
892 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); in tg3_ape_scratchpad_read()
896 if (tg3_ape_wait_for_event(tp, 30000)) in tg3_ape_scratchpad_read()
900 u32 val = tg3_ape_read32(tp, msgoff + i); in tg3_ape_scratchpad_read()
910 static int tg3_ape_send_event(struct tg3 *tp, u32 event) in tg3_ape_send_event() argument
915 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_ape_send_event()
919 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_send_event()
924 err = tg3_ape_event_lock(tp, 20000); in tg3_ape_send_event()
928 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, in tg3_ape_send_event()
931 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_send_event()
932 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); in tg3_ape_send_event()
937 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) in tg3_ape_driver_state_change() argument
942 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_driver_state_change()
947 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_ape_driver_state_change()
948 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, in tg3_ape_driver_state_change()
950 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, in tg3_ape_driver_state_change()
952 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); in tg3_ape_driver_state_change()
953 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); in tg3_ape_driver_state_change()
954 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, in tg3_ape_driver_state_change()
956 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, in tg3_ape_driver_state_change()
958 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, in tg3_ape_driver_state_change()
964 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
965 tg3_flag(tp, WOL_ENABLE)) { in tg3_ape_driver_state_change()
966 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, in tg3_ape_driver_state_change()
972 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); in tg3_ape_driver_state_change()
982 tg3_ape_send_event(tp, event); in tg3_ape_driver_state_change()
985 static void tg3_send_ape_heartbeat(struct tg3 *tp, in tg3_send_ape_heartbeat() argument
989 if (!tg3_flag(tp, ENABLE_APE) || in tg3_send_ape_heartbeat()
990 time_before(jiffies, tp->ape_hb_jiffies + interval)) in tg3_send_ape_heartbeat()
993 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_send_ape_heartbeat()
994 tp->ape_hb_jiffies = jiffies; in tg3_send_ape_heartbeat()
997 static void tg3_disable_ints(struct tg3 *tp) in tg3_disable_ints() argument
1002 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
1003 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1004 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1007 static void tg3_enable_ints(struct tg3 *tp) in tg3_enable_ints() argument
1011 tp->irq_sync = 0; in tg3_enable_ints()
1015 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1017 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1018 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1019 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1022 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_enable_ints()
1025 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1029 if (!tg3_flag(tp, TAGGED_STATUS) && in tg3_enable_ints()
1030 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1031 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1033 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1035 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1040 struct tg3 *tp = tnapi->tp; in tg3_has_work() local
1045 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_has_work()
1069 struct tg3 *tp = tnapi->tp; in tg3_int_reenable() local
1077 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) in tg3_int_reenable()
1078 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1082 static void tg3_switch_clocks(struct tg3 *tp) in tg3_switch_clocks() argument
1087 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) in tg3_switch_clocks()
1096 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1098 if (tg3_flag(tp, 5705_PLUS)) { in tg3_switch_clocks()
1117 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, in __tg3_readphy() argument
1124 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1126 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1130 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1161 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1162 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1166 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1171 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) in tg3_readphy() argument
1173 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1176 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, in __tg3_writephy() argument
1183 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1187 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1189 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1193 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1220 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1221 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1225 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1230 static int tg3_writephy(struct tg3 *tp, int reg, u32 val) in tg3_writephy() argument
1232 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1235 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) in tg3_phy_cl45_write() argument
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_write()
1243 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_write()
1247 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_write()
1252 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_write()
1258 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) in tg3_phy_cl45_read() argument
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_read()
1266 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_read()
1270 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_read()
1275 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_read()
1281 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) in tg3_phydsp_read() argument
1285 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_read()
1287 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_read()
1292 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) in tg3_phydsp_write() argument
1296 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_write()
1298 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write()
1303 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) in tg3_phy_auxctl_read() argument
1307 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, in tg3_phy_auxctl_read()
1311 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); in tg3_phy_auxctl_read()
1316 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) in tg3_phy_auxctl_write() argument
1321 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); in tg3_phy_auxctl_write()
1324 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable) in tg3_phy_toggle_auxctl_smdsp() argument
1329 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); in tg3_phy_toggle_auxctl_smdsp()
1339 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_toggle_auxctl_smdsp()
1345 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val) in tg3_phy_shdw_write() argument
1347 return tg3_writephy(tp, MII_TG3_MISC_SHDW, in tg3_phy_shdw_write()
1351 static int tg3_bmcr_reset(struct tg3 *tp) in tg3_bmcr_reset() argument
1360 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
1366 err = tg3_readphy(tp, MII_BMCR, &phy_control); in tg3_bmcr_reset()
1384 struct tg3 *tp = bp->priv; in tg3_mdio_read() local
1387 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1389 if (__tg3_readphy(tp, mii_id, reg, &val)) in tg3_mdio_read()
1392 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1399 struct tg3 *tp = bp->priv; in tg3_mdio_write() local
1402 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1404 if (__tg3_writephy(tp, mii_id, reg, val)) in tg3_mdio_write()
1407 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1412 static void tg3_mdio_config_5785(struct tg3 *tp) in tg3_mdio_config_5785() argument
1417 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_config_5785()
1448 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) in tg3_mdio_config_5785()
1461 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1462 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1464 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1479 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1480 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1485 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1493 static void tg3_mdio_start(struct tg3 *tp) in tg3_mdio_start() argument
1495 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1496 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1499 if (tg3_flag(tp, MDIOBUS_INITED) && in tg3_mdio_start()
1500 tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_mdio_start()
1501 tg3_mdio_config_5785(tp); in tg3_mdio_start()
1504 static int tg3_mdio_init(struct tg3 *tp) in tg3_mdio_init() argument
1510 if (tg3_flag(tp, 5717_PLUS)) { in tg3_mdio_init()
1513 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1515 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) in tg3_mdio_init()
1521 tp->phy_addr += 7; in tg3_mdio_init()
1522 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) { in tg3_mdio_init()
1525 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1528 tp->phy_addr = addr; in tg3_mdio_init()
1530 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1532 tg3_mdio_start(tp); in tg3_mdio_init()
1534 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) in tg3_mdio_init()
1537 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1538 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1541 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1542 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(tp->pdev)); in tg3_mdio_init()
1543 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1544 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1545 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1546 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1547 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1554 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) in tg3_mdio_init()
1555 tg3_bmcr_reset(tp); in tg3_mdio_init()
1557 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1559 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1560 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1564 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_init()
1567 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1568 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1569 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1592 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1596 tg3_flag_set(tp, MDIOBUS_INITED); in tg3_mdio_init()
1598 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_mdio_init()
1599 tg3_mdio_config_5785(tp); in tg3_mdio_init()
1604 static void tg3_mdio_fini(struct tg3 *tp) in tg3_mdio_fini() argument
1606 if (tg3_flag(tp, MDIOBUS_INITED)) { in tg3_mdio_fini()
1607 tg3_flag_clear(tp, MDIOBUS_INITED); in tg3_mdio_fini()
1608 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1609 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1614 static inline void tg3_generate_fw_event(struct tg3 *tp) in tg3_generate_fw_event() argument
1622 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1628 static void tg3_wait_for_event_ack(struct tg3 *tp) in tg3_wait_for_event_ack() argument
1635 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1650 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1658 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data) in tg3_phy_gather_ump_data() argument
1663 if (!tg3_readphy(tp, MII_BMCR, ®)) in tg3_phy_gather_ump_data()
1665 if (!tg3_readphy(tp, MII_BMSR, ®)) in tg3_phy_gather_ump_data()
1670 if (!tg3_readphy(tp, MII_ADVERTISE, ®)) in tg3_phy_gather_ump_data()
1672 if (!tg3_readphy(tp, MII_LPA, ®)) in tg3_phy_gather_ump_data()
1677 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1678 if (!tg3_readphy(tp, MII_CTRL1000, ®)) in tg3_phy_gather_ump_data()
1680 if (!tg3_readphy(tp, MII_STAT1000, ®)) in tg3_phy_gather_ump_data()
1685 if (!tg3_readphy(tp, MII_PHYADDR, ®)) in tg3_phy_gather_ump_data()
1693 static void tg3_ump_link_report(struct tg3 *tp) in tg3_ump_link_report() argument
1697 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) in tg3_ump_link_report()
1700 tg3_phy_gather_ump_data(tp, data); in tg3_ump_link_report()
1702 tg3_wait_for_event_ack(tp); in tg3_ump_link_report()
1704 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); in tg3_ump_link_report()
1705 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); in tg3_ump_link_report()
1706 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]); in tg3_ump_link_report()
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]); in tg3_ump_link_report()
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]); in tg3_ump_link_report()
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]); in tg3_ump_link_report()
1711 tg3_generate_fw_event(tp); in tg3_ump_link_report()
1715 static void tg3_stop_fw(struct tg3 *tp) in tg3_stop_fw() argument
1717 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_stop_fw()
1719 tg3_wait_for_event_ack(tp); in tg3_stop_fw()
1721 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); in tg3_stop_fw()
1723 tg3_generate_fw_event(tp); in tg3_stop_fw()
1726 tg3_wait_for_event_ack(tp); in tg3_stop_fw()
1731 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) in tg3_write_sig_pre_reset() argument
1733 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, in tg3_write_sig_pre_reset()
1736 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_pre_reset()
1739 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1744 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1749 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1760 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) in tg3_write_sig_post_reset() argument
1762 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_post_reset()
1765 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_post_reset()
1770 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_post_reset()
1781 static void tg3_write_sig_legacy(struct tg3 *tp, int kind) in tg3_write_sig_legacy() argument
1783 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_write_sig_legacy()
1786 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1791 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1796 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1806 static int tg3_poll_fw(struct tg3 *tp) in tg3_poll_fw() argument
1811 if (tg3_flag(tp, NO_FWARE_REPORTED)) in tg3_poll_fw()
1814 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_poll_fw()
1819 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_poll_fw()
1824 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1834 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); in tg3_poll_fw()
1837 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1838 if (!tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1839 tg3_flag_set(tp, NO_FWARE_REPORTED); in tg3_poll_fw()
1840 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1854 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1855 tg3_flag_set(tp, NO_FWARE_REPORTED); in tg3_poll_fw()
1857 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1860 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { in tg3_poll_fw()
1870 static void tg3_link_report(struct tg3 *tp) in tg3_link_report() argument
1872 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1873 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1874 tg3_ump_link_report(tp); in tg3_link_report()
1875 } else if (netif_msg_link(tp)) { in tg3_link_report()
1876 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1877 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1879 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1881 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1884 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1885 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1887 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1890 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1891 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1892 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1894 tg3_ump_link_report(tp); in tg3_link_report()
1897 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1960 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) in tg3_setup_flow_control() argument
1964 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1965 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1967 if (tg3_flag(tp, USE_PHYLIB)) in tg3_setup_flow_control()
1968 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; in tg3_setup_flow_control()
1970 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1972 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_setup_flow_control()
1973 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1978 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1980 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
1983 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1985 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1987 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1988 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
1991 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1993 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1995 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
1996 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2003 struct tg3 *tp = netdev_priv(dev); in tg3_adjust_link() local
2004 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_adjust_link()
2006 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2008 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2011 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2020 tg3_asic_rev(tp) != ASIC_REV_5785) in tg3_adjust_link()
2029 tp->link_config.flowctrl); in tg3_adjust_link()
2037 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); in tg3_adjust_link()
2041 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2042 tp->mac_mode = mac_mode; in tg3_adjust_link()
2043 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2047 if (tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_adjust_link()
2067 if (phydev->link != tp->old_link || in tg3_adjust_link()
2068 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2069 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2070 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2073 tp->old_link = phydev->link; in tg3_adjust_link()
2074 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2075 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2077 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2080 tg3_link_report(tp); in tg3_adjust_link()
2083 static int tg3_phy_init(struct tg3 *tp) in tg3_phy_init() argument
2087 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2091 tg3_bmcr_reset(tp); in tg3_phy_init()
2093 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_init()
2096 phydev = phy_connect(tp->dev, phydev_name(phydev), in tg3_phy_init()
2099 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2107 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2118 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_init()
2122 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2129 static void tg3_phy_start(struct tg3 *tp) in tg3_phy_start() argument
2133 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2136 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_start()
2138 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2139 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2140 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2141 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2142 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2144 phydev->advertising, tp->link_config.advertising); in tg3_phy_start()
2152 static void tg3_phy_stop(struct tg3 *tp) in tg3_phy_stop() argument
2154 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2157 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_stop()
2160 static void tg3_phy_fini(struct tg3 *tp) in tg3_phy_fini() argument
2162 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2163 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_fini()
2164 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2168 static int tg3_phy_set_extloopbk(struct tg3 *tp) in tg3_phy_set_extloopbk() argument
2173 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2176 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2178 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2185 err = tg3_phy_auxctl_read(tp, in tg3_phy_set_extloopbk()
2191 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2198 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) in tg3_phy_fet_toggle_apd() argument
2202 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_phy_fet_toggle_apd()
2205 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_fet_toggle_apd()
2207 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { in tg3_phy_fet_toggle_apd()
2212 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); in tg3_phy_fet_toggle_apd()
2214 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_phy_fet_toggle_apd()
2218 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) in tg3_phy_toggle_apd() argument
2222 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_apd()
2223 (tg3_flag(tp, 5717_PLUS) && in tg3_phy_toggle_apd()
2224 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2227 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2228 tg3_phy_fet_toggle_apd(tp, enable); in tg3_phy_toggle_apd()
2236 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable) in tg3_phy_toggle_apd()
2239 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg); in tg3_phy_toggle_apd()
2246 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg); in tg3_phy_toggle_apd()
2249 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable) in tg3_phy_toggle_automdix() argument
2253 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_automdix()
2254 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2257 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2260 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { in tg3_phy_toggle_automdix()
2263 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_toggle_automdix()
2265 if (!tg3_readphy(tp, reg, &phy)) { in tg3_phy_toggle_automdix()
2270 tg3_writephy(tp, reg, phy); in tg3_phy_toggle_automdix()
2272 tg3_writephy(tp, MII_TG3_FET_TEST, ephy); in tg3_phy_toggle_automdix()
2277 ret = tg3_phy_auxctl_read(tp, in tg3_phy_toggle_automdix()
2284 tg3_phy_auxctl_write(tp, in tg3_phy_toggle_automdix()
2290 static void tg3_phy_set_wirespeed(struct tg3 *tp) in tg3_phy_set_wirespeed() argument
2295 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2298 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
2300 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
2304 static void tg3_phy_apply_otp(struct tg3 *tp) in tg3_phy_apply_otp() argument
2308 if (!tp->phy_otp) in tg3_phy_apply_otp()
2311 otp = tp->phy_otp; in tg3_phy_apply_otp()
2313 if (tg3_phy_toggle_auxctl_smdsp(tp, true)) in tg3_phy_apply_otp()
2318 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); in tg3_phy_apply_otp()
2322 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); in tg3_phy_apply_otp()
2326 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); in tg3_phy_apply_otp()
2329 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); in tg3_phy_apply_otp()
2332 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); in tg3_phy_apply_otp()
2336 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); in tg3_phy_apply_otp()
2338 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_apply_otp()
2341 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee) in tg3_eee_pull_config() argument
2344 struct ethtool_eee *dest = &tp->eee; in tg3_eee_pull_config()
2346 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2352 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val)) in tg3_eee_pull_config()
2363 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val)) in tg3_eee_pull_config()
2368 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val)) in tg3_eee_pull_config()
2381 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up) in tg3_phy_eee_adjust() argument
2385 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2388 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2390 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2392 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2393 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2394 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2397 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2404 tg3_eee_pull_config(tp, NULL); in tg3_phy_eee_adjust()
2405 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2406 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2409 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2411 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_eee_adjust()
2412 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); in tg3_phy_eee_adjust()
2413 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_eee_adjust()
2421 static void tg3_phy_eee_enable(struct tg3 *tp) in tg3_phy_eee_enable() argument
2425 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2426 (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_phy_eee_enable()
2427 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_phy_eee_enable()
2428 tg3_flag(tp, 57765_CLASS)) && in tg3_phy_eee_enable()
2429 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_eee_enable()
2432 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); in tg3_phy_eee_enable()
2433 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_eee_enable()
2440 static int tg3_wait_macro_done(struct tg3 *tp) in tg3_wait_macro_done() argument
2447 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { in tg3_wait_macro_done()
2458 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) in tg3_phy_write_and_check_testpat() argument
2471 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2473 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2476 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
2479 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2480 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2485 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2487 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2488 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2493 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2494 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2502 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || in tg3_phy_write_and_check_testpat()
2503 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || in tg3_phy_write_and_check_testpat()
2504 tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2512 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); in tg3_phy_write_and_check_testpat()
2513 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
2514 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
2524 static int tg3_phy_reset_chanpat(struct tg3 *tp) in tg3_phy_reset_chanpat() argument
2531 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_reset_chanpat()
2533 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2535 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
2536 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2537 if (tg3_wait_macro_done(tp)) in tg3_phy_reset_chanpat()
2544 static int tg3_phy_reset_5703_4_5(struct tg3 *tp) in tg3_phy_reset_5703_4_5() argument
2553 err = tg3_bmcr_reset(tp); in tg3_phy_reset_5703_4_5()
2560 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) in tg3_phy_reset_5703_4_5()
2564 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2567 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
2571 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) in tg3_phy_reset_5703_4_5()
2574 tg3_writephy(tp, MII_CTRL1000, in tg3_phy_reset_5703_4_5()
2577 err = tg3_phy_toggle_auxctl_smdsp(tp, true); in tg3_phy_reset_5703_4_5()
2582 tg3_phydsp_write(tp, 0x8005, 0x0800); in tg3_phy_reset_5703_4_5()
2584 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); in tg3_phy_reset_5703_4_5()
2589 err = tg3_phy_reset_chanpat(tp); in tg3_phy_reset_5703_4_5()
2593 tg3_phydsp_write(tp, 0x8005, 0x0000); in tg3_phy_reset_5703_4_5()
2595 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); in tg3_phy_reset_5703_4_5()
2596 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
2598 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset_5703_4_5()
2600 tg3_writephy(tp, MII_CTRL1000, phy9_orig); in tg3_phy_reset_5703_4_5()
2602 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32); in tg3_phy_reset_5703_4_5()
2607 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2612 static void tg3_carrier_off(struct tg3 *tp) in tg3_carrier_off() argument
2614 netif_carrier_off(tp->dev); in tg3_carrier_off()
2615 tp->link_up = false; in tg3_carrier_off()
2618 static void tg3_warn_mgmt_link_flap(struct tg3 *tp) in tg3_warn_mgmt_link_flap() argument
2620 if (tg3_flag(tp, ENABLE_ASF)) in tg3_warn_mgmt_link_flap()
2621 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2628 static int tg3_phy_reset(struct tg3 *tp) in tg3_phy_reset() argument
2633 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_phy_reset()
2638 err = tg3_readphy(tp, MII_BMSR, &val); in tg3_phy_reset()
2639 err |= tg3_readphy(tp, MII_BMSR, &val); in tg3_phy_reset()
2643 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2644 netif_carrier_off(tp->dev); in tg3_phy_reset()
2645 tg3_link_report(tp); in tg3_phy_reset()
2648 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_phy_reset()
2649 tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_phy_reset()
2650 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_phy_reset()
2651 err = tg3_phy_reset_5703_4_5(tp); in tg3_phy_reset()
2658 if (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_phy_reset()
2659 tg3_chip_rev(tp) != CHIPREV_5784_AX) { in tg3_phy_reset()
2666 err = tg3_bmcr_reset(tp); in tg3_phy_reset()
2672 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); in tg3_phy_reset()
2677 if (tg3_chip_rev(tp) == CHIPREV_5784_AX || in tg3_phy_reset()
2678 tg3_chip_rev(tp) == CHIPREV_5761_AX) { in tg3_phy_reset()
2688 if (tg3_flag(tp, 5717_PLUS) && in tg3_phy_reset()
2689 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2692 tg3_phy_apply_otp(tp); in tg3_phy_reset()
2694 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2695 tg3_phy_toggle_apd(tp, true); in tg3_phy_reset()
2697 tg3_phy_toggle_apd(tp, false); in tg3_phy_reset()
2700 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2701 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2702 tg3_phydsp_write(tp, 0x201f, 0x2aaa); in tg3_phy_reset()
2703 tg3_phydsp_write(tp, 0x000a, 0x0323); in tg3_phy_reset()
2704 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2707 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2708 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2709 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2712 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2713 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2714 tg3_phydsp_write(tp, 0x000a, 0x310b); in tg3_phy_reset()
2715 tg3_phydsp_write(tp, 0x201f, 0x9506); in tg3_phy_reset()
2716 tg3_phydsp_write(tp, 0x401f, 0x14e2); in tg3_phy_reset()
2717 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2719 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2720 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2721 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); in tg3_phy_reset()
2722 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2723 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset()
2724 tg3_writephy(tp, MII_TG3_TEST1, in tg3_phy_reset()
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); in tg3_phy_reset()
2729 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2735 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2737 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_phy_reset()
2738 } else if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2740 err = tg3_phy_auxctl_read(tp, in tg3_phy_reset()
2743 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_reset()
2750 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2751 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) in tg3_phy_reset()
2752 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_reset()
2756 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_phy_reset()
2758 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); in tg3_phy_reset()
2761 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0) in tg3_phy_reset()
2762 tg3_phydsp_write(tp, 0xffb, 0x4000); in tg3_phy_reset()
2764 tg3_phy_toggle_automdix(tp, true); in tg3_phy_reset()
2765 tg3_phy_set_wirespeed(tp); in tg3_phy_reset()
2785 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) in tg3_set_function_status() argument
2789 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_function_status()
2790 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_set_function_status()
2791 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); in tg3_set_function_status()
2795 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2799 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_function_status()
2800 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_set_function_status()
2801 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); in tg3_set_function_status()
2808 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) in tg3_pwrsrc_switch_to_vmain() argument
2810 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vmain()
2813 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_pwrsrc_switch_to_vmain()
2814 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_pwrsrc_switch_to_vmain()
2815 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_pwrsrc_switch_to_vmain()
2816 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_pwrsrc_switch_to_vmain()
2819 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); in tg3_pwrsrc_switch_to_vmain()
2821 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2824 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); in tg3_pwrsrc_switch_to_vmain()
2826 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2833 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) in tg3_pwrsrc_die_with_vmain() argument
2837 if (!tg3_flag(tp, IS_NIC) || in tg3_pwrsrc_die_with_vmain()
2838 tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_pwrsrc_die_with_vmain()
2839 tg3_asic_rev(tp) == ASIC_REV_5701) in tg3_pwrsrc_die_with_vmain()
2842 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2857 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) in tg3_pwrsrc_switch_to_vaux() argument
2859 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vaux()
2862 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_pwrsrc_switch_to_vaux()
2863 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_pwrsrc_switch_to_vaux()
2864 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2871 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2872 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2879 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2895 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_pwrsrc_switch_to_vaux()
2897 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2903 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2916 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2922 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2928 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2934 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) in tg3_frob_aux_power_5717() argument
2939 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_frob_aux_power_5717()
2942 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) in tg3_frob_aux_power_5717()
2945 msg = tg3_set_function_status(tp, msg); in tg3_frob_aux_power_5717()
2951 tg3_pwrsrc_switch_to_vaux(tp); in tg3_frob_aux_power_5717()
2953 tg3_pwrsrc_die_with_vmain(tp); in tg3_frob_aux_power_5717()
2956 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); in tg3_frob_aux_power_5717()
2959 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) in tg3_frob_aux_power() argument
2964 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) in tg3_frob_aux_power()
2967 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_frob_aux_power()
2968 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_frob_aux_power()
2969 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_frob_aux_power()
2970 tg3_frob_aux_power_5717(tp, include_wol ? in tg3_frob_aux_power()
2971 tg3_flag(tp, WOL_ENABLE) != 0 : 0); in tg3_frob_aux_power()
2975 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2978 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
2993 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || in tg3_frob_aux_power()
2994 tg3_flag(tp, ENABLE_ASF)) in tg3_frob_aux_power()
2998 tg3_pwrsrc_switch_to_vaux(tp); in tg3_frob_aux_power()
3000 tg3_pwrsrc_die_with_vmain(tp); in tg3_frob_aux_power()
3003 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) in tg3_5700_link_polarity() argument
3005 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3007 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3016 static bool tg3_phy_power_bug(struct tg3 *tp) in tg3_phy_power_bug() argument
3018 switch (tg3_asic_rev(tp)) { in tg3_phy_power_bug()
3023 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3027 if (!tp->pci_fn) in tg3_phy_power_bug()
3032 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3033 !tp->pci_fn) in tg3_phy_power_bug()
3041 static bool tg3_phy_led_bug(struct tg3 *tp) in tg3_phy_led_bug() argument
3043 switch (tg3_asic_rev(tp)) { in tg3_phy_led_bug()
3046 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3047 !tp->pci_fn) in tg3_phy_led_bug()
3055 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) in tg3_power_down_phy() argument
3059 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3062 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3063 if (tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_power_down_phy()
3075 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_phy()
3076 tg3_bmcr_reset(tp); in tg3_power_down_phy()
3081 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3083 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_power_down_phy()
3086 tg3_writephy(tp, MII_ADVERTISE, 0); in tg3_power_down_phy()
3087 tg3_writephy(tp, MII_BMCR, in tg3_power_down_phy()
3090 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_power_down_phy()
3092 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { in tg3_power_down_phy()
3094 tg3_writephy(tp, in tg3_power_down_phy()
3098 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_power_down_phy()
3102 if (!tg3_phy_led_bug(tp)) in tg3_power_down_phy()
3103 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_power_down_phy()
3109 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); in tg3_power_down_phy()
3115 if (tg3_phy_power_bug(tp)) in tg3_power_down_phy()
3118 if (tg3_chip_rev(tp) == CHIPREV_5784_AX || in tg3_power_down_phy()
3119 tg3_chip_rev(tp) == CHIPREV_5761_AX) { in tg3_power_down_phy()
3126 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); in tg3_power_down_phy()
3130 static int tg3_nvram_lock(struct tg3 *tp) in tg3_nvram_lock() argument
3132 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_lock()
3135 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3147 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3153 static void tg3_nvram_unlock(struct tg3 *tp) in tg3_nvram_unlock() argument
3155 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_unlock()
3156 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3157 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3158 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3164 static void tg3_enable_nvram_access(struct tg3 *tp) in tg3_enable_nvram_access() argument
3166 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_enable_nvram_access()
3174 static void tg3_disable_nvram_access(struct tg3 *tp) in tg3_disable_nvram_access() argument
3176 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_disable_nvram_access()
3183 static int tg3_nvram_read_using_eeprom(struct tg3 *tp, in tg3_nvram_read_using_eeprom() argument
3225 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) in tg3_nvram_exec_cmd() argument
3244 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) in tg3_nvram_phys_addr() argument
3246 if (tg3_flag(tp, NVRAM) && in tg3_nvram_phys_addr()
3247 tg3_flag(tp, NVRAM_BUFFERED) && in tg3_nvram_phys_addr()
3248 tg3_flag(tp, FLASH) && in tg3_nvram_phys_addr()
3249 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && in tg3_nvram_phys_addr()
3250 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3252 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3254 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3259 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) in tg3_nvram_logical_addr() argument
3261 if (tg3_flag(tp, NVRAM) && in tg3_nvram_logical_addr()
3262 tg3_flag(tp, NVRAM_BUFFERED) && in tg3_nvram_logical_addr()
3263 tg3_flag(tp, FLASH) && in tg3_nvram_logical_addr()
3264 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && in tg3_nvram_logical_addr()
3265 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3268 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3280 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) in tg3_nvram_read() argument
3284 if (!tg3_flag(tp, NVRAM)) in tg3_nvram_read()
3285 return tg3_nvram_read_using_eeprom(tp, offset, val); in tg3_nvram_read()
3287 offset = tg3_nvram_phys_addr(tp, offset); in tg3_nvram_read()
3292 ret = tg3_nvram_lock(tp); in tg3_nvram_read()
3296 tg3_enable_nvram_access(tp); in tg3_nvram_read()
3299 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | in tg3_nvram_read()
3305 tg3_disable_nvram_access(tp); in tg3_nvram_read()
3307 tg3_nvram_unlock(tp); in tg3_nvram_read()
3313 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) in tg3_nvram_read_be32() argument
3316 int res = tg3_nvram_read(tp, offset, &v); in tg3_nvram_read_be32()
3322 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, in tg3_nvram_write_block_using_eeprom() argument
3372 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, in tg3_nvram_write_block_unbuffered() argument
3376 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3392 ret = tg3_nvram_read_be32(tp, phy_addr + j, in tg3_nvram_write_block_unbuffered()
3411 tg3_enable_nvram_access(tp); in tg3_nvram_write_block_unbuffered()
3419 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3428 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3434 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3454 ret = tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_unbuffered()
3463 tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_unbuffered()
3471 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, in tg3_nvram_write_block_buffered() argument
3483 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3485 phy_addr = tg3_nvram_phys_addr(tp, offset); in tg3_nvram_write_block_buffered()
3491 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3498 !tg3_flag(tp, FLASH) || in tg3_nvram_write_block_buffered()
3499 !tg3_flag(tp, 57765_PLUS)) in tg3_nvram_write_block_buffered()
3502 if (tg3_asic_rev(tp) != ASIC_REV_5752 && in tg3_nvram_write_block_buffered()
3503 !tg3_flag(tp, 5755_PLUS) && in tg3_nvram_write_block_buffered()
3504 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3509 ret = tg3_nvram_exec_cmd(tp, cmd); in tg3_nvram_write_block_buffered()
3513 if (!tg3_flag(tp, FLASH)) { in tg3_nvram_write_block_buffered()
3518 ret = tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_buffered()
3526 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) in tg3_nvram_write_block() argument
3530 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
3531 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3536 if (!tg3_flag(tp, NVRAM)) { in tg3_nvram_write_block()
3537 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); in tg3_nvram_write_block()
3541 ret = tg3_nvram_lock(tp); in tg3_nvram_write_block()
3545 tg3_enable_nvram_access(tp); in tg3_nvram_write_block()
3546 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) in tg3_nvram_write_block()
3552 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { in tg3_nvram_write_block()
3553 ret = tg3_nvram_write_block_buffered(tp, offset, len, in tg3_nvram_write_block()
3556 ret = tg3_nvram_write_block_unbuffered(tp, offset, len, in tg3_nvram_write_block()
3563 tg3_disable_nvram_access(tp); in tg3_nvram_write_block()
3564 tg3_nvram_unlock(tp); in tg3_nvram_write_block()
3567 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
3568 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3581 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base) in tg3_pause_cpu() argument
3591 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3599 static int tg3_rxcpu_pause(struct tg3 *tp) in tg3_rxcpu_pause() argument
3601 int rc = tg3_pause_cpu(tp, RX_CPU_BASE); in tg3_rxcpu_pause()
3611 static int tg3_txcpu_pause(struct tg3 *tp) in tg3_txcpu_pause() argument
3613 return tg3_pause_cpu(tp, TX_CPU_BASE); in tg3_txcpu_pause()
3617 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base) in tg3_resume_cpu() argument
3624 static void tg3_rxcpu_resume(struct tg3 *tp) in tg3_rxcpu_resume() argument
3626 tg3_resume_cpu(tp, RX_CPU_BASE); in tg3_rxcpu_resume()
3630 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base) in tg3_halt_cpu() argument
3634 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); in tg3_halt_cpu()
3636 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_halt_cpu()
3643 rc = tg3_rxcpu_pause(tp); in tg3_halt_cpu()
3649 if (tg3_flag(tp, IS_SSB_CORE)) in tg3_halt_cpu()
3652 rc = tg3_txcpu_pause(tp); in tg3_halt_cpu()
3656 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3662 if (tg3_flag(tp, NVRAM)) in tg3_halt_cpu()
3667 static int tg3_fw_data_len(struct tg3 *tp, in tg3_fw_data_len() argument
3686 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3689 fw_len = tp->fw->size; in tg3_fw_data_len()
3695 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, in tg3_load_firmware_cpu() argument
3701 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3703 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { in tg3_load_firmware_cpu()
3704 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3710 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766) in tg3_load_firmware_cpu()
3715 if (tg3_asic_rev(tp) != ASIC_REV_57766) { in tg3_load_firmware_cpu()
3719 int lock_err = tg3_nvram_lock(tp); in tg3_load_firmware_cpu()
3720 err = tg3_halt_cpu(tp, cpu_base); in tg3_load_firmware_cpu()
3722 tg3_nvram_unlock(tp); in tg3_load_firmware_cpu()
3727 write_op(tp, cpu_scratch_base + i, 0); in tg3_load_firmware_cpu()
3741 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++) in tg3_load_firmware_cpu()
3742 write_op(tp, cpu_scratch_base + in tg3_load_firmware_cpu()
3761 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc) in tg3_pause_cpu_and_set_pc() argument
3782 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) in tg3_load_5701_a0_firmware_fix() argument
3787 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3795 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3801 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3808 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3811 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3818 tg3_rxcpu_resume(tp); in tg3_load_5701_a0_firmware_fix()
3823 static int tg3_validate_rxcpu_state(struct tg3 *tp) in tg3_validate_rxcpu_state() argument
3840 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3844 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE); in tg3_validate_rxcpu_state()
3846 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3855 static void tg3_load_57766_firmware(struct tg3 *tp) in tg3_load_57766_firmware() argument
3859 if (!tg3_flag(tp, NO_NVRAM)) in tg3_load_57766_firmware()
3862 if (tg3_validate_rxcpu_state(tp)) in tg3_load_57766_firmware()
3865 if (!tp->fw) in tg3_load_57766_firmware()
3882 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3886 if (tg3_rxcpu_pause(tp)) in tg3_load_57766_firmware()
3890 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr); in tg3_load_57766_firmware()
3892 tg3_rxcpu_resume(tp); in tg3_load_57766_firmware()
3896 static int tg3_load_tso_firmware(struct tg3 *tp) in tg3_load_tso_firmware() argument
3902 if (!tg3_flag(tp, FW_TSO)) in tg3_load_tso_firmware()
3905 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3913 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3915 if (tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_load_tso_firmware()
3924 err = tg3_load_firmware_cpu(tp, cpu_base, in tg3_load_tso_firmware()
3931 err = tg3_pause_cpu_and_set_pc(tp, cpu_base, in tg3_load_tso_firmware()
3934 netdev_err(tp->dev, in tg3_load_tso_firmware()
3941 tg3_resume_cpu(tp, cpu_base); in tg3_load_tso_firmware()
3946 static void __tg3_set_one_mac_addr(struct tg3 *tp, const u8 *mac_addr, in __tg3_set_one_mac_addr() argument
3966 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1) in __tg3_set_mac_addr() argument
3974 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3977 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in __tg3_set_mac_addr()
3978 tg3_asic_rev(tp) == ASIC_REV_5704) { in __tg3_set_mac_addr()
3980 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3983 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
3984 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
3985 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
3986 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
3987 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
3988 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
3993 static void tg3_enable_register_access(struct tg3 *tp) in tg3_enable_register_access() argument
3999 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
4000 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4003 static int tg3_power_up(struct tg3 *tp) in tg3_power_up() argument
4007 tg3_enable_register_access(tp); in tg3_power_up()
4009 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4012 tg3_pwrsrc_switch_to_vmain(tp); in tg3_power_up()
4014 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4022 static int tg3_power_down_prepare(struct tg3 *tp) in tg3_power_down_prepare() argument
4027 tg3_enable_register_access(tp); in tg3_power_down_prepare()
4030 if (tg3_flag(tp, CLKREQ_BUG)) in tg3_power_down_prepare()
4031 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4038 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4039 tg3_flag(tp, WOL_ENABLE); in tg3_power_down_prepare()
4041 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_power_down_prepare()
4043 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4044 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4049 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_power_down_prepare()
4051 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4053 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4054 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4055 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4057 &tp->link_config.advertising, in tg3_power_down_prepare()
4068 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { in tg3_power_down_prepare()
4069 if (tg3_flag(tp, WOL_SPEED_100MB)) { in tg3_power_down_prepare()
4097 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4098 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4100 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4101 tg3_setup_phy(tp, false); in tg3_power_down_prepare()
4104 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_prepare()
4109 } else if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
4114 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); in tg3_power_down_prepare()
4120 if (tg3_flag(tp, WOL_CAP)) in tg3_power_down_prepare()
4121 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | in tg3_power_down_prepare()
4129 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4131 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4132 tg3_phy_auxctl_write(tp, in tg3_power_down_prepare()
4140 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4142 else if (tp->phy_flags & in tg3_power_down_prepare()
4144 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4151 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4152 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_power_down_prepare()
4153 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? in tg3_power_down_prepare()
4155 if (tg3_5700_link_polarity(tp, speed)) in tg3_power_down_prepare()
4164 if (!tg3_flag(tp, 5750_PLUS)) in tg3_power_down_prepare()
4165 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4168 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && in tg3_power_down_prepare()
4169 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) in tg3_power_down_prepare()
4172 if (tg3_flag(tp, ENABLE_APE)) in tg3_power_down_prepare()
4184 if (!tg3_flag(tp, WOL_SPEED_100MB) && in tg3_power_down_prepare()
4185 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4186 tg3_asic_rev(tp) == ASIC_REV_5701)) { in tg3_power_down_prepare()
4189 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4195 } else if (tg3_flag(tp, 5780_CLASS) || in tg3_power_down_prepare()
4196 tg3_flag(tp, CPMU_PRESENT) || in tg3_power_down_prepare()
4197 tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_prepare()
4199 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { in tg3_power_down_prepare()
4202 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4203 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_power_down_prepare()
4208 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
4216 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4219 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4222 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
4225 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4226 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_power_down_prepare()
4235 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4239 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) in tg3_power_down_prepare()
4240 tg3_power_down_phy(tp, do_low_power); in tg3_power_down_prepare()
4242 tg3_frob_aux_power(tp, true); in tg3_power_down_prepare()
4245 if ((!tg3_flag(tp, IS_SSB_CORE)) && in tg3_power_down_prepare()
4246 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) || in tg3_power_down_prepare()
4247 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) { in tg3_power_down_prepare()
4252 if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
4255 err = tg3_nvram_lock(tp); in tg3_power_down_prepare()
4256 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_power_down_prepare()
4258 tg3_nvram_unlock(tp); in tg3_power_down_prepare()
4262 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); in tg3_power_down_prepare()
4264 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN); in tg3_power_down_prepare()
4269 static void tg3_power_down(struct tg3 *tp) in tg3_power_down() argument
4271 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4272 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4275 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex) in tg3_aux_stat_to_speed_duplex() argument
4309 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4322 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) in tg3_phy_autoneg_cfg() argument
4331 err = tg3_writephy(tp, MII_ADVERTISE, new_adv); in tg3_phy_autoneg_cfg()
4335 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4338 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_phy_autoneg_cfg()
4339 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) in tg3_phy_autoneg_cfg()
4342 err = tg3_writephy(tp, MII_CTRL1000, new_adv); in tg3_phy_autoneg_cfg()
4347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4353 err = tg3_phy_toggle_auxctl_smdsp(tp, true); in tg3_phy_autoneg_cfg()
4365 if (!tp->eee.eee_enabled) { in tg3_phy_autoneg_cfg()
4367 tp->eee.advertised = 0; in tg3_phy_autoneg_cfg()
4369 tp->eee.advertised = advertise & in tg3_phy_autoneg_cfg()
4374 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); in tg3_phy_autoneg_cfg()
4378 switch (tg3_asic_rev(tp)) { in tg3_phy_autoneg_cfg()
4388 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); in tg3_phy_autoneg_cfg()
4392 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) in tg3_phy_autoneg_cfg()
4393 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | in tg3_phy_autoneg_cfg()
4397 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_autoneg_cfg()
4406 static void tg3_phy_copper_begin(struct tg3 *tp) in tg3_phy_copper_begin() argument
4408 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4409 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4412 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4413 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4416 if (tg3_flag(tp, WOL_SPEED_100MB)) in tg3_phy_copper_begin()
4419 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4420 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4428 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4429 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4433 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4436 tg3_phy_autoneg_cfg(tp, adv, fc); in tg3_phy_copper_begin()
4438 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4439 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4447 tg3_writephy(tp, MII_BMCR, in tg3_phy_copper_begin()
4453 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4454 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4456 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_phy_copper_begin()
4461 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL); in tg3_phy_copper_begin()
4465 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4479 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4482 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && in tg3_phy_copper_begin()
4484 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); in tg3_phy_copper_begin()
4489 if (tg3_readphy(tp, MII_BMSR, &tmp) || in tg3_phy_copper_begin()
4490 tg3_readphy(tp, MII_BMSR, &tmp)) in tg3_phy_copper_begin()
4497 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_copper_begin()
4503 static int tg3_phy_pull_config(struct tg3 *tp) in tg3_phy_pull_config() argument
4508 err = tg3_readphy(tp, MII_BMCR, &val); in tg3_phy_pull_config()
4513 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4514 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4515 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_phy_pull_config()
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4524 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4527 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4530 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4533 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4534 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4543 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4545 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4547 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4553 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4554 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4555 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_phy_pull_config()
4557 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4560 err = tg3_readphy(tp, MII_ADVERTISE, &val); in tg3_phy_pull_config()
4565 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4567 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4569 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4572 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4575 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4576 err = tg3_readphy(tp, MII_CTRL1000, &val); in tg3_phy_pull_config()
4582 err = tg3_readphy(tp, MII_ADVERTISE, &val); in tg3_phy_pull_config()
4587 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4593 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4600 static int tg3_init_5401phy_dsp(struct tg3 *tp) in tg3_init_5401phy_dsp() argument
4606 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_init_5401phy_dsp()
4608 err |= tg3_phydsp_write(tp, 0x0012, 0x1804); in tg3_init_5401phy_dsp()
4609 err |= tg3_phydsp_write(tp, 0x0013, 0x1204); in tg3_init_5401phy_dsp()
4610 err |= tg3_phydsp_write(tp, 0x8006, 0x0132); in tg3_init_5401phy_dsp()
4611 err |= tg3_phydsp_write(tp, 0x8006, 0x0232); in tg3_init_5401phy_dsp()
4612 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); in tg3_init_5401phy_dsp()
4619 static bool tg3_phy_eee_config_ok(struct tg3 *tp) in tg3_phy_eee_config_ok() argument
4623 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4626 tg3_eee_pull_config(tp, &eee); in tg3_phy_eee_config_ok()
4628 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4629 if (tp->eee.advertised != eee.advertised || in tg3_phy_eee_config_ok()
4630 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4631 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4642 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) in tg3_phy_copper_an_config_ok() argument
4646 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4650 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4651 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4655 if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) in tg3_phy_copper_an_config_ok()
4661 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4666 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) in tg3_phy_copper_an_config_ok()
4670 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_phy_copper_an_config_ok()
4671 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) { in tg3_phy_copper_an_config_ok()
4686 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) in tg3_phy_copper_fetch_rmtadv() argument
4690 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4693 if (tg3_readphy(tp, MII_STAT1000, &val)) in tg3_phy_copper_fetch_rmtadv()
4699 if (tg3_readphy(tp, MII_LPA, rmtadv)) in tg3_phy_copper_fetch_rmtadv()
4703 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4708 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up) in tg3_test_and_report_link_chg() argument
4710 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4712 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4714 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4715 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4716 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4719 tg3_link_report(tp); in tg3_test_and_report_link_chg()
4726 static void tg3_clear_mac_status(struct tg3 *tp) in tg3_clear_mac_status() argument
4738 static void tg3_setup_eee(struct tg3 *tp) in tg3_setup_eee() argument
4744 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) in tg3_setup_eee()
4753 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4757 if (tg3_asic_rev(tp) != ASIC_REV_5717) in tg3_setup_eee()
4760 if (tg3_flag(tp, ENABLE_APE)) in tg3_setup_eee()
4763 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4767 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4774 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset) in tg3_setup_copper_phy() argument
4783 tg3_clear_mac_status(tp); in tg3_setup_copper_phy()
4785 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4787 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4791 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); in tg3_setup_copper_phy()
4796 if ((tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_setup_copper_phy()
4797 tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_setup_copper_phy()
4798 tg3_asic_rev(tp) == ASIC_REV_5705) && in tg3_setup_copper_phy()
4799 tp->link_up) { in tg3_setup_copper_phy()
4800 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4801 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4806 tg3_phy_reset(tp); in tg3_setup_copper_phy()
4808 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4809 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4810 if (tg3_readphy(tp, MII_BMSR, &bmsr) || in tg3_setup_copper_phy()
4811 !tg3_flag(tp, INIT_COMPLETE)) in tg3_setup_copper_phy()
4815 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
4819 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4822 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4829 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4832 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4833 err = tg3_phy_reset(tp); in tg3_setup_copper_phy()
4835 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
4840 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_setup_copper_phy()
4841 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) { in tg3_setup_copper_phy()
4843 tg3_writephy(tp, 0x15, 0x0a75); in tg3_setup_copper_phy()
4844 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4845 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_setup_copper_phy()
4846 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4850 tg3_readphy(tp, MII_TG3_ISTAT, &val); in tg3_setup_copper_phy()
4851 tg3_readphy(tp, MII_TG3_ISTAT, &val); in tg3_setup_copper_phy()
4853 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4854 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); in tg3_setup_copper_phy()
4855 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4856 tg3_writephy(tp, MII_TG3_IMASK, ~0); in tg3_setup_copper_phy()
4858 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_setup_copper_phy()
4859 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_setup_copper_phy()
4860 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4861 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_setup_copper_phy()
4864 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); in tg3_setup_copper_phy()
4870 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4871 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4873 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4874 err = tg3_phy_auxctl_read(tp, in tg3_setup_copper_phy()
4878 tg3_phy_auxctl_write(tp, in tg3_setup_copper_phy()
4887 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4888 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4897 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); in tg3_setup_copper_phy()
4900 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && in tg3_setup_copper_phy()
4905 tg3_aux_stat_to_speed_duplex(tp, aux_stat, in tg3_setup_copper_phy()
4911 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
4912 if (tg3_readphy(tp, MII_BMCR, &bmcr)) in tg3_setup_copper_phy()
4922 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4923 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4925 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4926 bool eee_config_ok = tg3_phy_eee_config_ok(tp); in tg3_setup_copper_phy()
4930 tg3_phy_copper_an_config_ok(tp, &lcl_adv) && in tg3_setup_copper_phy()
4931 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) in tg3_setup_copper_phy()
4939 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4941 tg3_setup_eee(tp); in tg3_setup_copper_phy()
4942 tg3_phy_reset(tp); in tg3_setup_copper_phy()
4946 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4947 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4953 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4956 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4964 if (!tg3_readphy(tp, reg, &val) && (val & bit)) in tg3_setup_copper_phy()
4965 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4967 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); in tg3_setup_copper_phy()
4972 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4973 tg3_phy_copper_begin(tp); in tg3_setup_copper_phy()
4975 if (tg3_flag(tp, ROBOSWITCH)) { in tg3_setup_copper_phy()
4980 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4981 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4984 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4985 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || in tg3_setup_copper_phy()
4986 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
4990 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
4992 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4993 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4996 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4997 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
4998 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
5000 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5005 if (tg3_flag(tp, RGMII_MODE)) { in tg3_setup_copper_phy()
5009 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5011 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5014 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5022 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5023 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5024 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5026 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_setup_copper_phy()
5028 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5029 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5031 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5037 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5038 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) { in tg3_setup_copper_phy()
5039 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5040 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5044 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5047 tg3_phy_eee_adjust(tp, current_link_up); in tg3_setup_copper_phy()
5049 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_setup_copper_phy()
5057 if (tg3_asic_rev(tp) == ASIC_REV_5700 && in tg3_setup_copper_phy()
5059 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5060 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { in tg3_setup_copper_phy()
5066 tg3_write_mem(tp, in tg3_setup_copper_phy()
5072 if (tg3_flag(tp, CLKREQ_BUG)) { in tg3_setup_copper_phy()
5073 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5074 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5075 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5078 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5082 tg3_test_and_report_link_chg(tp, current_link_up); in tg3_setup_copper_phy()
5151 static int tg3_fiber_aneg_smachine(struct tg3 *tp, in tg3_fiber_aneg_smachine() argument
5231 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5232 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5254 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5260 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5261 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5275 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5276 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5361 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5362 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5403 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) in fiber_autoneg() argument
5413 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5417 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5426 status = tg3_fiber_aneg_smachine(tp, &aninfo); in fiber_autoneg()
5433 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5434 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5448 static void tg3_init_bcm8002(struct tg3 *tp) in tg3_init_bcm8002() argument
5454 if (tg3_flag(tp, INIT_COMPLETE) && in tg3_init_bcm8002()
5459 tg3_writephy(tp, 0x16, 0x8007); in tg3_init_bcm8002()
5462 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_init_bcm8002()
5470 tg3_writephy(tp, 0x10, 0x8411); in tg3_init_bcm8002()
5473 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5475 tg3_writephy(tp, 0x18, 0x00a0); in tg3_init_bcm8002()
5476 tg3_writephy(tp, 0x16, 0x41ff); in tg3_init_bcm8002()
5479 tg3_writephy(tp, 0x13, 0x0400); in tg3_init_bcm8002()
5481 tg3_writephy(tp, 0x13, 0x0000); in tg3_init_bcm8002()
5483 tg3_writephy(tp, 0x11, 0x0a50); in tg3_init_bcm8002()
5485 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5495 tg3_writephy(tp, 0x10, 0x8011); in tg3_init_bcm8002()
5498 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) in tg3_setup_fiber_hw_autoneg() argument
5511 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 && in tg3_setup_fiber_hw_autoneg()
5512 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) { in tg3_setup_fiber_hw_autoneg()
5524 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5539 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5548 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5555 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5556 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5560 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5571 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5572 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5592 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5595 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_hw_autoneg()
5597 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5598 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5600 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5601 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5623 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5625 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5627 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5634 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5635 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5642 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) in tg3_setup_fiber_by_hand() argument
5649 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5653 if (fiber_autoneg(tp, &txflags, &rxflags)) { in tg3_setup_fiber_by_hand()
5666 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5669 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_by_hand()
5691 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_by_hand()
5696 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5699 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5707 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset) in tg3_setup_fiber_phy() argument
5716 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5717 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5718 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5720 if (!tg3_flag(tp, HW_AUTONEG) && in tg3_setup_fiber_phy()
5721 tp->link_up && in tg3_setup_fiber_phy()
5722 tg3_flag(tp, INIT_COMPLETE)) { in tg3_setup_fiber_phy()
5738 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5739 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5740 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5743 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5744 tg3_init_bcm8002(tp); in tg3_setup_fiber_phy()
5750 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5753 if (tg3_flag(tp, HW_AUTONEG)) in tg3_setup_fiber_phy()
5754 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); in tg3_setup_fiber_phy()
5756 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); in tg3_setup_fiber_phy()
5758 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5760 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5775 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5776 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5777 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5780 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5785 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5786 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5787 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5791 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5792 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5793 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5798 if (!tg3_test_and_report_link_chg(tp, current_link_up)) { in tg3_setup_fiber_phy()
5799 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5801 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5802 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5803 tg3_link_report(tp); in tg3_setup_fiber_phy()
5809 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset) in tg3_setup_fiber_mii_phy() argument
5818 if ((tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_setup_fiber_mii_phy()
5819 tg3_asic_rev(tp) == ASIC_REV_5720) && in tg3_setup_fiber_mii_phy()
5820 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) && in tg3_setup_fiber_mii_phy()
5824 tg3_phy_reset(tp); in tg3_setup_fiber_mii_phy()
5826 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5829 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5834 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5837 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5840 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5849 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5852 tg3_clear_mac_status(tp); in tg3_setup_fiber_mii_phy()
5857 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5858 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5861 tg3_clear_mac_status(tp); in tg3_setup_fiber_mii_phy()
5864 tg3_phy_reset(tp); in tg3_setup_fiber_mii_phy()
5866 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5868 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5869 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5870 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
5877 err |= tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_fiber_mii_phy()
5879 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5880 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5882 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5885 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5891 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5892 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5895 tg3_writephy(tp, MII_ADVERTISE, newadv); in tg3_setup_fiber_mii_phy()
5897 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_setup_fiber_mii_phy()
5900 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5901 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5911 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5921 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5924 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5928 tg3_writephy(tp, MII_ADVERTISE, adv); in tg3_setup_fiber_mii_phy()
5929 tg3_writephy(tp, MII_BMCR, bmcr | in tg3_setup_fiber_mii_phy()
5933 tg3_carrier_off(tp); in tg3_setup_fiber_mii_phy()
5935 tg3_writephy(tp, MII_BMCR, new_bmcr); in tg3_setup_fiber_mii_phy()
5937 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5938 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5939 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
5945 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5963 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); in tg3_setup_fiber_mii_phy()
5964 err |= tg3_readphy(tp, MII_LPA, &remote_adv); in tg3_setup_fiber_mii_phy()
5973 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5975 } else if (!tg3_flag(tp, 5780_CLASS)) { in tg3_setup_fiber_mii_phy()
5985 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_mii_phy()
5987 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5988 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
5989 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5991 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5996 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
5997 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
5999 tg3_test_and_report_link_chg(tp, current_link_up); in tg3_setup_fiber_mii_phy()
6003 static void tg3_serdes_parallel_detect(struct tg3 *tp) in tg3_serdes_parallel_detect() argument
6005 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
6007 tp->serdes_counter--; in tg3_serdes_parallel_detect()
6011 if (!tp->link_up && in tg3_serdes_parallel_detect()
6012 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6015 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_serdes_parallel_detect()
6020 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); in tg3_serdes_parallel_detect()
6021 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); in tg3_serdes_parallel_detect()
6024 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6026 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6027 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6037 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_serdes_parallel_detect()
6038 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6041 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6042 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6043 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6047 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6049 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6054 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_serdes_parallel_detect()
6055 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); in tg3_serdes_parallel_detect()
6057 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6063 static int tg3_setup_phy(struct tg3 *tp, bool force_reset) in tg3_setup_phy() argument
6068 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6069 err = tg3_setup_fiber_phy(tp, force_reset); in tg3_setup_phy()
6070 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6071 err = tg3_setup_fiber_mii_phy(tp, force_reset); in tg3_setup_phy()
6073 err = tg3_setup_copper_phy(tp, force_reset); in tg3_setup_phy()
6075 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { in tg3_setup_phy()
6093 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_setup_phy()
6094 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_setup_phy()
6099 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6100 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6107 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_setup_phy()
6108 if (tp->link_up) { in tg3_setup_phy()
6110 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6116 if (tg3_flag(tp, ASPM_WORKAROUND)) { in tg3_setup_phy()
6118 if (!tp->link_up) in tg3_setup_phy()
6120 tp->pwrmgmt_thresh; in tg3_setup_phy()
6130 static u64 tg3_refclk_read(struct tg3 *tp, struct ptp_system_timestamp *sts) in tg3_refclk_read() argument
6143 static void tg3_refclk_write(struct tg3 *tp, u64 newval) in tg3_refclk_write() argument
6153 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6154 static inline void tg3_full_unlock(struct tg3 *tp);
6157 struct tg3 *tp = netdev_priv(dev); in tg3_get_ts_info() local
6163 if (tg3_flag(tp, PTP_CAPABLE)) { in tg3_get_ts_info()
6169 if (tp->ptp_clock) in tg3_get_ts_info()
6170 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6185 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_adjfine() local
6196 tg3_full_lock(tp, 0); in tg3_ptp_adjfine()
6206 tg3_full_unlock(tp); in tg3_ptp_adjfine()
6213 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_adjtime() local
6215 tg3_full_lock(tp, 0); in tg3_ptp_adjtime()
6216 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6217 tg3_full_unlock(tp); in tg3_ptp_adjtime()
6226 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_gettimex() local
6228 tg3_full_lock(tp, 0); in tg3_ptp_gettimex()
6229 ns = tg3_refclk_read(tp, sts); in tg3_ptp_gettimex()
6230 ns += tp->ptp_adjust; in tg3_ptp_gettimex()
6231 tg3_full_unlock(tp); in tg3_ptp_gettimex()
6242 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_settime() local
6246 tg3_full_lock(tp, 0); in tg3_ptp_settime()
6247 tg3_refclk_write(tp, ns); in tg3_ptp_settime()
6248 tp->ptp_adjust = 0; in tg3_ptp_settime()
6249 tg3_full_unlock(tp); in tg3_ptp_settime()
6257 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_enable() local
6270 tg3_full_lock(tp, 0); in tg3_ptp_enable()
6281 netdev_warn(tp->dev, in tg3_ptp_enable()
6288 netdev_warn(tp->dev, in tg3_ptp_enable()
6307 tg3_full_unlock(tp); in tg3_ptp_enable()
6333 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock, in tg3_hwclock_to_timestamp() argument
6338 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6342 static void tg3_ptp_init(struct tg3 *tp) in tg3_ptp_init() argument
6344 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_ptp_init()
6348 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real())); in tg3_ptp_init()
6349 tp->ptp_adjust = 0; in tg3_ptp_init()
6350 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6354 static void tg3_ptp_resume(struct tg3 *tp) in tg3_ptp_resume() argument
6356 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_ptp_resume()
6359 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6360 tp->ptp_adjust = 0; in tg3_ptp_resume()
6363 static void tg3_ptp_fini(struct tg3 *tp) in tg3_ptp_fini() argument
6365 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6368 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6369 tp->ptp_clock = NULL; in tg3_ptp_fini()
6370 tp->ptp_adjust = 0; in tg3_ptp_fini()
6373 static inline int tg3_irq_sync(struct tg3 *tp) in tg3_irq_sync() argument
6375 return tp->irq_sync; in tg3_irq_sync()
6378 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) in tg3_rd32_loop() argument
6387 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) in tg3_dump_legacy_regs() argument
6389 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); in tg3_dump_legacy_regs()
6390 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); in tg3_dump_legacy_regs()
6391 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); in tg3_dump_legacy_regs()
6392 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); in tg3_dump_legacy_regs()
6393 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); in tg3_dump_legacy_regs()
6394 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); in tg3_dump_legacy_regs()
6395 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); in tg3_dump_legacy_regs()
6396 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); in tg3_dump_legacy_regs()
6397 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); in tg3_dump_legacy_regs()
6398 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); in tg3_dump_legacy_regs()
6399 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); in tg3_dump_legacy_regs()
6400 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); in tg3_dump_legacy_regs()
6401 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); in tg3_dump_legacy_regs()
6402 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); in tg3_dump_legacy_regs()
6403 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); in tg3_dump_legacy_regs()
6404 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); in tg3_dump_legacy_regs()
6405 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); in tg3_dump_legacy_regs()
6406 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); in tg3_dump_legacy_regs()
6407 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); in tg3_dump_legacy_regs()
6409 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_dump_legacy_regs()
6410 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); in tg3_dump_legacy_regs()
6412 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); in tg3_dump_legacy_regs()
6413 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); in tg3_dump_legacy_regs()
6414 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6415 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6416 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6417 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6418 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6419 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); in tg3_dump_legacy_regs()
6421 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_dump_legacy_regs()
6422 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6423 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6424 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6427 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); in tg3_dump_legacy_regs()
6428 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); in tg3_dump_legacy_regs()
6429 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); in tg3_dump_legacy_regs()
6430 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); in tg3_dump_legacy_regs()
6431 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); in tg3_dump_legacy_regs()
6433 if (tg3_flag(tp, NVRAM)) in tg3_dump_legacy_regs()
6434 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); in tg3_dump_legacy_regs()
6437 static void tg3_dump_state(struct tg3 *tp) in tg3_dump_state() argument
6445 if (tp->pdev->error_state != pci_channel_io_normal) { in tg3_dump_state()
6446 netdev_err(tp->dev, "PCI channel ERROR!\n"); in tg3_dump_state()
6454 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_dump_state()
6459 tg3_dump_legacy_regs(tp, regs); in tg3_dump_state()
6466 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6473 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6474 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6477 netdev_err(tp->dev, in tg3_dump_state()
6488 netdev_err(tp->dev, in tg3_dump_state()
6507 static void tg3_tx_recover(struct tg3 *tp) in tg3_tx_recover() argument
6509 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || in tg3_tx_recover()
6510 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6512 netdev_warn(tp->dev, in tg3_tx_recover()
6518 tg3_flag_set(tp, TX_RECOVERY_PENDING); in tg3_tx_recover()
6535 struct tg3 *tp = tnapi->tp; in tg3_tx() local
6539 int index = tnapi - tp->napi; in tg3_tx()
6542 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx()
6545 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6553 tg3_tx_recover(tp); in tg3_tx()
6562 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp); in tg3_tx()
6567 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), in tg3_tx()
6585 dma_unmap_page(&tp->pdev->dev, in tg3_tx()
6605 tg3_tx_recover(tp); in tg3_tx()
6639 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) in tg3_rx_data_free() argument
6641 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) + in tg3_rx_data_free()
6647 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), map_sz, in tg3_rx_data_free()
6665 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, in tg3_alloc_rx_data() argument
6677 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6680 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6684 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6700 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) + in tg3_alloc_rx_data()
6712 mapping = dma_map_single(&tp->pdev->dev, data + TG3_RX_OFFSET(tp), in tg3_alloc_rx_data()
6714 if (unlikely(dma_mapping_error(&tp->pdev->dev, mapping))) { in tg3_alloc_rx_data()
6737 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx() local
6740 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6745 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6753 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6804 struct tg3 *tp = tnapi->tp; in tg3_rx() local
6835 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6841 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6860 prefetch(data + TG3_RX_OFFSET(tp)); in tg3_rx()
6872 if (len > TG3_RX_COPY_THRESH(tp)) { in tg3_rx()
6876 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key, in tg3_rx()
6881 dma_unmap_single(&tp->pdev->dev, dma_addr, skb_size, in tg3_rx()
6899 skb_reserve(skb, TG3_RX_OFFSET(tp)); in tg3_rx()
6904 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6910 dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr, len, in tg3_rx()
6913 data + TG3_RX_OFFSET(tp), in tg3_rx()
6915 dma_sync_single_for_device(&tp->pdev->dev, dma_addr, in tg3_rx()
6921 tg3_hwclock_to_timestamp(tp, tstamp, in tg3_rx()
6924 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6932 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6934 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6942 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6954 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6956 tp->rx_std_ring_mask; in tg3_rx()
6964 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
6978 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_rx()
6984 tp->rx_std_ring_mask; in tg3_rx()
6990 tp->rx_jmb_ring_mask; in tg3_rx()
7000 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
7001 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
7003 if (tnapi != &tp->napi[1]) { in tg3_rx()
7004 tp->rx_refill = true; in tg3_rx()
7005 napi_schedule(&tp->napi[1].napi); in tg3_rx()
7012 static void tg3_poll_link(struct tg3 *tp) in tg3_poll_link() argument
7015 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_poll_link()
7016 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7021 spin_lock(&tp->lock); in tg3_poll_link()
7022 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_poll_link()
7030 tg3_setup_phy(tp, false); in tg3_poll_link()
7031 spin_unlock(&tp->lock); in tg3_poll_link()
7036 static int tg3_rx_prodring_xfer(struct tg3 *tp, in tg3_rx_prodring_xfer() argument
7057 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7061 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7096 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7098 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7115 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7119 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7154 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7156 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7164 struct tg3 *tp = tnapi->tp; in tg3_poll_work() local
7169 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_work()
7183 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7184 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7189 tp->rx_refill = false; in tg3_poll_work()
7190 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7191 err |= tg3_rx_prodring_xfer(tp, dpr, in tg3_poll_work()
7192 &tp->napi[i].prodring); in tg3_poll_work()
7205 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7211 static inline void tg3_reset_task_schedule(struct tg3 *tp) in tg3_reset_task_schedule() argument
7213 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7214 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7217 static inline void tg3_reset_task_cancel(struct tg3 *tp) in tg3_reset_task_cancel() argument
7219 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_cancel()
7220 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7221 tg3_flag_clear(tp, TX_RECOVERY_PENDING); in tg3_reset_task_cancel()
7227 struct tg3 *tp = tnapi->tp; in tg3_poll_msix() local
7234 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_msix()
7255 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7265 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7266 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7274 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1); in tg3_poll_msix()
7280 tg3_reset_task_schedule(tp); in tg3_poll_msix()
7284 static void tg3_process_error(struct tg3 *tp) in tg3_process_error() argument
7289 if (tg3_flag(tp, ERROR_PROCESSED)) in tg3_process_error()
7295 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7300 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7305 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7312 tg3_dump_state(tp); in tg3_process_error()
7314 tg3_flag_set(tp, ERROR_PROCESSED); in tg3_process_error()
7315 tg3_reset_task_schedule(tp); in tg3_process_error()
7321 struct tg3 *tp = tnapi->tp; in tg3_poll() local
7327 tg3_process_error(tp); in tg3_poll()
7329 tg3_poll_link(tp); in tg3_poll()
7333 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll()
7339 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_poll()
7357 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1); in tg3_poll()
7363 tg3_reset_task_schedule(tp); in tg3_poll()
7367 static void tg3_napi_disable(struct tg3 *tp) in tg3_napi_disable() argument
7371 for (i = tp->irq_cnt - 1; i >= 0; i--) in tg3_napi_disable()
7372 napi_disable(&tp->napi[i].napi); in tg3_napi_disable()
7375 static void tg3_napi_enable(struct tg3 *tp) in tg3_napi_enable() argument
7379 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_enable()
7380 napi_enable(&tp->napi[i].napi); in tg3_napi_enable()
7383 static void tg3_napi_init(struct tg3 *tp) in tg3_napi_init() argument
7387 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll); in tg3_napi_init()
7388 for (i = 1; i < tp->irq_cnt; i++) in tg3_napi_init()
7389 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix); in tg3_napi_init()
7392 static void tg3_napi_fini(struct tg3 *tp) in tg3_napi_fini() argument
7396 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7397 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7400 static inline void tg3_netif_stop(struct tg3 *tp) in tg3_netif_stop() argument
7402 netif_trans_update(tp->dev); /* prevent tx timeout */ in tg3_netif_stop()
7403 tg3_napi_disable(tp); in tg3_netif_stop()
7404 netif_carrier_off(tp->dev); in tg3_netif_stop()
7405 netif_tx_disable(tp->dev); in tg3_netif_stop()
7409 static inline void tg3_netif_start(struct tg3 *tp) in tg3_netif_start() argument
7411 tg3_ptp_resume(tp); in tg3_netif_start()
7417 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7419 if (tp->link_up) in tg3_netif_start()
7420 netif_carrier_on(tp->dev); in tg3_netif_start()
7422 tg3_napi_enable(tp); in tg3_netif_start()
7423 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7424 tg3_enable_ints(tp); in tg3_netif_start()
7427 static void tg3_irq_quiesce(struct tg3 *tp) in tg3_irq_quiesce() argument
7428 __releases(tp->lock) in tg3_irq_quiesce()
7429 __acquires(tp->lock) in tg3_irq_quiesce()
7433 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7435 tp->irq_sync = 1; in tg3_irq_quiesce()
7438 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7440 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7441 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7443 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7451 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) in tg3_full_lock() argument
7453 spin_lock_bh(&tp->lock); in tg3_full_lock()
7455 tg3_irq_quiesce(tp); in tg3_full_lock()
7458 static inline void tg3_full_unlock(struct tg3 *tp) in tg3_full_unlock() argument
7460 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7469 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot() local
7475 if (likely(!tg3_irq_sync(tp))) in tg3_msi_1shot()
7488 struct tg3 *tp = tnapi->tp; in tg3_msi() local
7501 if (likely(!tg3_irq_sync(tp))) in tg3_msi()
7510 struct tg3 *tp = tnapi->tp; in tg3_interrupt() local
7520 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt()
7539 if (tg3_irq_sync(tp)) in tg3_interrupt()
7559 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged() local
7569 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt_tagged()
7597 if (tg3_irq_sync(tp)) in tg3_interrupt_tagged()
7612 struct tg3 *tp = tnapi->tp; in tg3_test_isr() local
7617 tg3_disable_ints(tp); in tg3_test_isr()
7627 struct tg3 *tp = netdev_priv(dev); in tg3_poll_controller() local
7629 if (tg3_irq_sync(tp)) in tg3_poll_controller()
7632 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7633 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7639 struct tg3 *tp = netdev_priv(dev); in tg3_tx_timeout() local
7641 if (netif_msg_tx_err(tp)) { in tg3_tx_timeout()
7643 tg3_dump_state(tp); in tg3_tx_timeout()
7646 tg3_reset_task_schedule(tp); in tg3_tx_timeout()
7660 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping, in tg3_4g_tso_overflow_test() argument
7663 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) { in tg3_4g_tso_overflow_test()
7672 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, in tg3_40bit_overflow_test() argument
7676 if (tg3_flag(tp, 40BIT_DMA_BUG)) in tg3_40bit_overflow_test()
7698 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set() local
7701 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) in tg3_tx_frag_set()
7707 if (tg3_4g_tso_overflow_test(tp, map, len, mss)) in tg3_tx_frag_set()
7710 if (tg3_40bit_overflow_test(tp, map, len)) in tg3_tx_frag_set()
7713 if (tp->dma_limit) { in tg3_tx_frag_set()
7716 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7717 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7718 len -= tp->dma_limit; in tg3_tx_frag_set()
7722 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7723 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7766 dma_unmap_single(&tnapi->tp->pdev->dev, dma_unmap_addr(txb, mapping), in tg3_tx_skb_unmap()
7781 dma_unmap_page(&tnapi->tp->pdev->dev, in tg3_tx_skb_unmap()
7799 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround() local
7804 if (tg3_asic_rev(tp) != ASIC_REV_5701) in tigon3_dma_hwbug_workaround()
7818 new_addr = dma_map_single(&tp->pdev->dev, new_skb->data, in tigon3_dma_hwbug_workaround()
7821 if (dma_mapping_error(&tp->pdev->dev, new_addr)) { in tigon3_dma_hwbug_workaround()
7861 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi, in tg3_tso_bug() argument
7883 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7892 tg3_start_xmit(seg, tp->dev); in tg3_tso_bug()
7904 struct tg3 *tp = netdev_priv(dev); in tg3_start_xmit() local
7918 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in tg3_start_xmit()
7919 if (tg3_flag(tp, ENABLE_TSS)) in tg3_start_xmit()
7961 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
7967 tg3_flag(tp, TSO_BUG)) { in tg3_start_xmit()
7969 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
7984 if (tg3_flag(tp, HW_TSO_1) || in tg3_start_xmit()
7985 tg3_flag(tp, HW_TSO_2) || in tg3_start_xmit()
7986 tg3_flag(tp, HW_TSO_3)) { in tg3_start_xmit()
7994 if (tg3_flag(tp, HW_TSO_3)) { in tg3_start_xmit()
7999 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_start_xmit()
8001 else if (tg3_flag(tp, HW_TSO_1) || in tg3_start_xmit()
8002 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_start_xmit()
8030 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in tg3_start_xmit()
8040 tg3_flag(tp, TX_TSTAMP_EN)) { in tg3_start_xmit()
8047 mapping = dma_map_single(&tp->pdev->dev, skb->data, len, in tg3_start_xmit()
8049 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8058 if (tg3_flag(tp, 5701_DMA_BUG)) in tg3_start_xmit()
8068 if (!tg3_flag(tp, HW_TSO_1) && in tg3_start_xmit()
8069 !tg3_flag(tp, HW_TSO_2) && in tg3_start_xmit()
8070 !tg3_flag(tp, HW_TSO_3)) in tg3_start_xmit()
8081 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in tg3_start_xmit()
8087 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8113 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
8163 static void tg3_mac_loopback(struct tg3 *tp, bool enable) in tg3_mac_loopback() argument
8166 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8169 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8171 if (!tg3_flag(tp, 5705_PLUS)) in tg3_mac_loopback()
8172 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8174 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8175 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8177 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8179 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8181 if (tg3_flag(tp, 5705_PLUS) || in tg3_mac_loopback()
8182 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8183 tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_mac_loopback()
8184 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8187 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8191 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) in tg3_phy_lpbk_set() argument
8195 tg3_phy_toggle_apd(tp, false); in tg3_phy_lpbk_set()
8196 tg3_phy_toggle_automdix(tp, false); in tg3_phy_lpbk_set()
8198 if (extlpbk && tg3_phy_set_extloopbk(tp)) in tg3_phy_lpbk_set()
8210 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8220 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8221 tg3_readphy(tp, MII_CTRL1000, &val); in tg3_phy_lpbk_set()
8224 tg3_writephy(tp, MII_CTRL1000, val); in tg3_phy_lpbk_set()
8228 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); in tg3_phy_lpbk_set()
8233 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_lpbk_set()
8236 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8237 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_phy_lpbk_set()
8241 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8242 tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_phy_lpbk_set()
8243 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | in tg3_phy_lpbk_set()
8248 tg3_readphy(tp, MII_TG3_FET_PTEST, &val); in tg3_phy_lpbk_set()
8252 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8253 tg3_flag(tp, 5780_CLASS)) { in tg3_phy_lpbk_set()
8256 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8259 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8266 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_phy_lpbk_set()
8267 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8274 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_lpbk_set()
8286 struct tg3 *tp = netdev_priv(dev); in tg3_set_loopback() local
8289 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8292 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8293 tg3_mac_loopback(tp, true); in tg3_set_loopback()
8294 netif_carrier_on(tp->dev); in tg3_set_loopback()
8295 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8298 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8301 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8302 tg3_mac_loopback(tp, false); in tg3_set_loopback()
8304 tg3_setup_phy(tp, true); in tg3_set_loopback()
8305 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8313 struct tg3 *tp = netdev_priv(dev); in tg3_fix_features() local
8315 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8331 static void tg3_rx_prodring_free(struct tg3 *tp, in tg3_rx_prodring_free() argument
8336 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8338 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8339 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8340 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8342 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_rx_prodring_free()
8345 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8346 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8354 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8355 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8356 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8358 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_free()
8359 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8360 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8372 static int tg3_rx_prodring_alloc(struct tg3 *tp, in tg3_rx_prodring_alloc() argument
8382 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8384 TG3_RX_STD_BUFF_RING_SIZE(tp)); in tg3_rx_prodring_alloc()
8387 TG3_RX_JMB_BUFF_RING_SIZE(tp)); in tg3_rx_prodring_alloc()
8392 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8395 if (tg3_flag(tp, 5780_CLASS) && in tg3_rx_prodring_alloc()
8396 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8398 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8404 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8415 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8418 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i, in tg3_rx_prodring_alloc()
8420 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8423 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8426 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8431 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_rx_prodring_alloc()
8434 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8436 if (!tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_rx_prodring_alloc()
8439 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8450 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8453 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i, in tg3_rx_prodring_alloc()
8455 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8458 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8461 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8470 tg3_rx_prodring_free(tp, tpr); in tg3_rx_prodring_alloc()
8474 static void tg3_rx_prodring_fini(struct tg3 *tp, in tg3_rx_prodring_fini() argument
8482 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8487 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8493 static int tg3_rx_prodring_init(struct tg3 *tp, in tg3_rx_prodring_init() argument
8496 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8501 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8502 TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_init()
8508 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_init()
8509 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8514 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8515 TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_init()
8525 tg3_rx_prodring_fini(tp, tpr); in tg3_rx_prodring_init()
8536 static void tg3_free_rings(struct tg3 *tp) in tg3_free_rings() argument
8540 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8541 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8543 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8559 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8570 static int tg3_init_rings(struct tg3 *tp) in tg3_init_rings() argument
8575 tg3_free_rings(tp); in tg3_init_rings()
8577 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8578 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8593 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8596 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8597 tg3_free_rings(tp); in tg3_init_rings()
8605 static void tg3_mem_tx_release(struct tg3 *tp) in tg3_mem_tx_release() argument
8609 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8610 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8613 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8623 static int tg3_mem_tx_acquire(struct tg3 *tp) in tg3_mem_tx_acquire() argument
8626 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8631 if (tg3_flag(tp, ENABLE_TSS)) in tg3_mem_tx_acquire()
8634 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8641 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8652 tg3_mem_tx_release(tp); in tg3_mem_tx_acquire()
8656 static void tg3_mem_rx_release(struct tg3 *tp) in tg3_mem_rx_release() argument
8660 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8661 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8663 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8668 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8669 TG3_RX_RCB_RING_BYTES(tp), in tg3_mem_rx_release()
8676 static int tg3_mem_rx_acquire(struct tg3 *tp) in tg3_mem_rx_acquire() argument
8680 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8685 if (tg3_flag(tp, ENABLE_RSS)) in tg3_mem_rx_acquire()
8689 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8691 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8698 if (!i && tg3_flag(tp, ENABLE_RSS)) in tg3_mem_rx_acquire()
8701 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8702 TG3_RX_RCB_RING_BYTES(tp), in tg3_mem_rx_acquire()
8712 tg3_mem_rx_release(tp); in tg3_mem_rx_acquire()
8720 static void tg3_free_consistent(struct tg3 *tp) in tg3_free_consistent() argument
8724 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8725 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8728 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8735 tg3_mem_rx_release(tp); in tg3_free_consistent()
8736 tg3_mem_tx_release(tp); in tg3_free_consistent()
8742 if (tp->hw_stats) { in tg3_free_consistent()
8743 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8744 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8745 tp->hw_stats = NULL; in tg3_free_consistent()
8753 static int tg3_alloc_consistent(struct tg3 *tp) in tg3_alloc_consistent() argument
8757 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8759 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8760 if (!tp->hw_stats) in tg3_alloc_consistent()
8763 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8764 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8767 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8776 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_alloc_consistent()
8805 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp)) in tg3_alloc_consistent()
8811 tg3_free_consistent(tp); in tg3_alloc_consistent()
8820 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent) in tg3_stop_block() argument
8825 if (tg3_flag(tp, 5705_PLUS)) { in tg3_stop_block()
8847 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8848 dev_err(&tp->pdev->dev, in tg3_stop_block()
8862 dev_err(&tp->pdev->dev, in tg3_stop_block()
8872 static int tg3_abort_hw(struct tg3 *tp, bool silent) in tg3_abort_hw() argument
8876 tg3_disable_ints(tp); in tg3_abort_hw()
8878 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8879 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8880 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8885 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8886 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
8889 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8890 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); in tg3_abort_hw()
8891 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); in tg3_abort_hw()
8892 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8893 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); in tg3_abort_hw()
8894 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); in tg3_abort_hw()
8896 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); in tg3_abort_hw()
8897 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8898 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); in tg3_abort_hw()
8899 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8900 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); in tg3_abort_hw()
8901 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8902 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); in tg3_abort_hw()
8904 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8905 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
8908 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
8909 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
8917 dev_err(&tp->pdev->dev, in tg3_abort_hw()
8923 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); in tg3_abort_hw()
8924 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8925 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); in tg3_abort_hw()
8930 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); in tg3_abort_hw()
8931 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); in tg3_abort_hw()
8934 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
8935 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
8944 static void tg3_save_pci_state(struct tg3 *tp) in tg3_save_pci_state() argument
8946 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
8950 static void tg3_restore_pci_state(struct tg3 *tp) in tg3_restore_pci_state() argument
8955 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
8956 tp->misc_host_ctrl); in tg3_restore_pci_state()
8960 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && in tg3_restore_pci_state()
8961 tg3_flag(tp, PCIX_MODE)) in tg3_restore_pci_state()
8964 if (tg3_flag(tp, ENABLE_APE)) in tg3_restore_pci_state()
8968 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
8970 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
8972 if (!tg3_flag(tp, PCI_EXPRESS)) { in tg3_restore_pci_state()
8973 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
8974 tp->pci_cacheline_sz); in tg3_restore_pci_state()
8975 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
8976 tp->pci_lat_timer); in tg3_restore_pci_state()
8980 if (tg3_flag(tp, PCIX_MODE)) { in tg3_restore_pci_state()
8983 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8986 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8990 if (tg3_flag(tp, 5780_CLASS)) { in tg3_restore_pci_state()
8995 if (tg3_flag(tp, USING_MSI)) { in tg3_restore_pci_state()
8998 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
8999 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9001 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
9002 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9010 static void tg3_override_clk(struct tg3 *tp) in tg3_override_clk() argument
9014 switch (tg3_asic_rev(tp)) { in tg3_override_clk()
9031 static void tg3_restore_clk(struct tg3 *tp) in tg3_restore_clk() argument
9035 switch (tg3_asic_rev(tp)) { in tg3_restore_clk()
9054 static int tg3_chip_reset(struct tg3 *tp) in tg3_chip_reset() argument
9055 __releases(tp->lock) in tg3_chip_reset()
9056 __acquires(tp->lock) in tg3_chip_reset()
9062 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9065 tg3_nvram_lock(tp); in tg3_chip_reset()
9067 tg3_ape_lock(tp, TG3_APE_LOCK_GRC); in tg3_chip_reset()
9072 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9078 tg3_save_pci_state(tp); in tg3_chip_reset()
9080 if (tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_chip_reset()
9081 tg3_flag(tp, 5755_PLUS)) in tg3_chip_reset()
9090 write_op = tp->write32; in tg3_chip_reset()
9092 tp->write32 = tg3_write32; in tg3_chip_reset()
9100 tg3_flag_set(tp, CHIP_RESETTING); in tg3_chip_reset()
9101 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9102 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9112 tg3_full_unlock(tp); in tg3_chip_reset()
9114 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9115 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9117 tg3_full_lock(tp, 0); in tg3_chip_reset()
9119 if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_chip_reset()
9127 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_chip_reset()
9129 if (tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_chip_reset()
9130 !tg3_flag(tp, 57765_PLUS) && in tg3_chip_reset()
9135 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) { in tg3_chip_reset()
9141 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_chip_reset()
9152 tg3_override_clk(tp); in tg3_chip_reset()
9155 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
9161 tp->write32 = write_op; in tg3_chip_reset()
9184 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9188 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9191 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) { in tg3_chip_reset()
9199 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9200 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9210 if (!tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
9212 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9215 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9222 tg3_restore_pci_state(tp); in tg3_chip_reset()
9224 tg3_flag_clear(tp, CHIP_RESETTING); in tg3_chip_reset()
9225 tg3_flag_clear(tp, ERROR_PROCESSED); in tg3_chip_reset()
9228 if (tg3_flag(tp, 5780_CLASS)) in tg3_chip_reset()
9232 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) { in tg3_chip_reset()
9233 tg3_stop_fw(tp); in tg3_chip_reset()
9237 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_chip_reset()
9243 tg3_stop_fw(tp); in tg3_chip_reset()
9244 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_chip_reset()
9247 err = tg3_poll_fw(tp); in tg3_chip_reset()
9251 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9253 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) { in tg3_chip_reset()
9259 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9260 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_chip_reset()
9261 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9262 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) in tg3_chip_reset()
9263 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9264 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9267 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9268 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9269 val = tp->mac_mode; in tg3_chip_reset()
9270 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9271 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9272 val = tp->mac_mode; in tg3_chip_reset()
9279 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); in tg3_chip_reset()
9281 tg3_mdio_start(tp); in tg3_chip_reset()
9283 if (tg3_flag(tp, PCI_EXPRESS) && in tg3_chip_reset()
9284 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && in tg3_chip_reset()
9285 tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_chip_reset()
9286 !tg3_flag(tp, 57765_PLUS)) { in tg3_chip_reset()
9292 tg3_restore_clk(tp); in tg3_chip_reset()
9297 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_chip_reset()
9304 tg3_flag_clear(tp, ENABLE_ASF); in tg3_chip_reset()
9305 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9308 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); in tg3_chip_reset()
9309 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); in tg3_chip_reset()
9313 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); in tg3_chip_reset()
9315 tg3_flag_set(tp, ENABLE_ASF); in tg3_chip_reset()
9316 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9317 if (tg3_flag(tp, 5750_PLUS)) in tg3_chip_reset()
9318 tg3_flag_set(tp, ASF_NEW_HANDSHAKE); in tg3_chip_reset()
9320 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg); in tg3_chip_reset()
9322 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9324 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9336 static int tg3_halt(struct tg3 *tp, int kind, bool silent) in tg3_halt() argument
9340 tg3_stop_fw(tp); in tg3_halt()
9342 tg3_write_sig_pre_reset(tp, kind); in tg3_halt()
9344 tg3_abort_hw(tp, silent); in tg3_halt()
9345 err = tg3_chip_reset(tp); in tg3_halt()
9347 __tg3_set_mac_addr(tp, false); in tg3_halt()
9349 tg3_write_sig_legacy(tp, kind); in tg3_halt()
9350 tg3_write_sig_post_reset(tp, kind); in tg3_halt()
9352 if (tp->hw_stats) { in tg3_halt()
9354 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9355 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9358 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9361 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_halt()
9373 struct tg3 *tp = netdev_priv(dev); in tg3_set_mac_addr() local
9386 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_set_mac_addr()
9399 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9400 __tg3_set_mac_addr(tp, skip_mac_1); in tg3_set_mac_addr()
9402 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9408 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, in tg3_set_bdinfo() argument
9412 tg3_write_mem(tp, in tg3_set_bdinfo()
9415 tg3_write_mem(tp, in tg3_set_bdinfo()
9418 tg3_write_mem(tp, in tg3_set_bdinfo()
9422 if (!tg3_flag(tp, 5705_PLUS)) in tg3_set_bdinfo()
9423 tg3_write_mem(tp, in tg3_set_bdinfo()
9429 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec) in tg3_coal_tx_init() argument
9433 if (!tg3_flag(tp, ENABLE_TSS)) { in tg3_coal_tx_init()
9442 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9454 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9461 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec) in tg3_coal_rx_init() argument
9464 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9466 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_coal_rx_init()
9488 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9495 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) in __tg3_set_coalesce() argument
9497 tg3_coal_tx_init(tp, ec); in __tg3_set_coalesce()
9498 tg3_coal_rx_init(tp, ec); in __tg3_set_coalesce()
9500 if (!tg3_flag(tp, 5705_PLUS)) { in __tg3_set_coalesce()
9506 if (!tp->link_up) in __tg3_set_coalesce()
9514 static void tg3_tx_rcbs_disable(struct tg3 *tp) in tg3_tx_rcbs_disable() argument
9519 if (!tg3_flag(tp, 5705_PLUS)) in tg3_tx_rcbs_disable()
9521 else if (tg3_flag(tp, 5717_PLUS)) in tg3_tx_rcbs_disable()
9523 else if (tg3_flag(tp, 57765_CLASS) || in tg3_tx_rcbs_disable()
9524 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_tx_rcbs_disable()
9531 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, in tg3_tx_rcbs_disable()
9536 static void tg3_tx_rcbs_init(struct tg3 *tp) in tg3_tx_rcbs_init() argument
9541 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx_rcbs_init()
9544 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9545 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9550 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9557 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp) in tg3_rx_ret_rcbs_disable() argument
9562 if (tg3_flag(tp, 5717_PLUS)) in tg3_rx_ret_rcbs_disable()
9564 else if (!tg3_flag(tp, 5705_PLUS)) in tg3_rx_ret_rcbs_disable()
9566 else if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_rx_ret_rcbs_disable()
9567 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_rx_ret_rcbs_disable()
9568 tg3_flag(tp, 57765_CLASS)) in tg3_rx_ret_rcbs_disable()
9575 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, in tg3_rx_ret_rcbs_disable()
9580 static void tg3_rx_ret_rcbs_init(struct tg3 *tp) in tg3_rx_ret_rcbs_init() argument
9585 if (tg3_flag(tp, ENABLE_RSS)) in tg3_rx_ret_rcbs_init()
9588 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9589 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9594 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9595 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9601 static void tg3_rings_reset(struct tg3 *tp) in tg3_rings_reset() argument
9605 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9607 tg3_tx_rcbs_disable(tp); in tg3_rings_reset()
9609 tg3_rx_ret_rcbs_disable(tp); in tg3_rings_reset()
9612 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9613 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9614 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9615 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9618 if (tg3_flag(tp, SUPPORT_MSIX)) { in tg3_rings_reset()
9619 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9620 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9621 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9622 if (tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
9623 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9624 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9625 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9626 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9627 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9628 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9630 if (!tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
9631 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9633 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9634 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9635 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9636 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9640 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_rings_reset()
9657 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9667 tg3_tx_rcbs_init(tp); in tg3_rings_reset()
9668 tg3_rx_ret_rcbs_init(tp); in tg3_rings_reset()
9671 static void tg3_setup_rxbd_thresholds(struct tg3 *tp) in tg3_setup_rxbd_thresholds() argument
9675 if (!tg3_flag(tp, 5750_PLUS) || in tg3_setup_rxbd_thresholds()
9676 tg3_flag(tp, 5780_CLASS) || in tg3_setup_rxbd_thresholds()
9677 tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_setup_rxbd_thresholds()
9678 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_setup_rxbd_thresholds()
9679 tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9681 else if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_setup_rxbd_thresholds()
9682 tg3_asic_rev(tp) == ASIC_REV_5787) in tg3_setup_rxbd_thresholds()
9687 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9688 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9693 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9696 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_setup_rxbd_thresholds()
9701 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9706 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9734 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) in tg3_set_multi() argument
9745 struct tg3 *tp = netdev_priv(dev); in __tg3_set_rx_mode() local
9748 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9755 if (!tg3_flag(tp, ENABLE_ASF)) in __tg3_set_rx_mode()
9764 tg3_set_multi(tp, 1); in __tg3_set_rx_mode()
9767 tg3_set_multi(tp, 0); in __tg3_set_rx_mode()
9790 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) { in __tg3_set_rx_mode()
9798 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9799 i + TG3_UCAST_ADDR_IDX(tp)); in __tg3_set_rx_mode()
9804 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9805 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9811 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt) in tg3_rss_init_dflt_indir_tbl() argument
9816 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9819 static void tg3_rss_check_indir_tbl(struct tg3 *tp) in tg3_rss_check_indir_tbl() argument
9823 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_rss_check_indir_tbl()
9826 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9827 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9833 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9838 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9841 static void tg3_rss_write_indir_tbl(struct tg3 *tp) in tg3_rss_write_indir_tbl() argument
9847 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9851 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9858 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp) in tg3_lso_rd_dma_workaround_bit() argument
9860 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_lso_rd_dma_workaround_bit()
9867 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) in tg3_reset_hw() argument
9871 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9873 tg3_disable_ints(tp); in tg3_reset_hw()
9875 tg3_stop_fw(tp); in tg3_reset_hw()
9877 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); in tg3_reset_hw()
9879 if (tg3_flag(tp, INIT_COMPLETE)) in tg3_reset_hw()
9880 tg3_abort_hw(tp, 1); in tg3_reset_hw()
9882 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9883 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9884 tg3_phy_pull_config(tp); in tg3_reset_hw()
9885 tg3_eee_pull_config(tp, NULL); in tg3_reset_hw()
9886 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9890 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
9891 tg3_setup_eee(tp); in tg3_reset_hw()
9894 tg3_phy_reset(tp); in tg3_reset_hw()
9896 err = tg3_chip_reset(tp); in tg3_reset_hw()
9900 tg3_write_sig_legacy(tp, RESET_KIND_INIT); in tg3_reset_hw()
9902 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { in tg3_reset_hw()
9923 if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_reset_hw()
9938 if (tg3_flag(tp, L1PLLPD_EN)) { in tg3_reset_hw()
9952 if (tg3_flag(tp, 57765_CLASS)) { in tg3_reset_hw()
9953 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { in tg3_reset_hw()
9968 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) { in tg3_reset_hw()
10002 if (!tg3_flag(tp, CPMU_PRESENT)) { in tg3_reset_hw()
10003 if (!tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
10004 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
10005 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
10008 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && in tg3_reset_hw()
10009 tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
10015 if (tg3_flag(tp, ENABLE_APE)) { in tg3_reset_hw()
10026 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) { in tg3_reset_hw()
10038 err = tg3_init_rings(tp); in tg3_reset_hw()
10042 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10045 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) in tg3_reset_hw()
10047 if (!tg3_flag(tp, 57765_CLASS) && in tg3_reset_hw()
10048 tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_reset_hw()
10049 tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_reset_hw()
10051 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10052 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 && in tg3_reset_hw()
10053 tg3_asic_rev(tp) != ASIC_REV_5761) { in tg3_reset_hw()
10057 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10060 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10064 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10072 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10075 if (tp->rxptpctl) in tg3_reset_hw()
10077 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10079 if (tg3_flag(tp, PTP_CAPABLE)) in tg3_reset_hw()
10082 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10088 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_reset_hw()
10089 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) { in tg3_reset_hw()
10101 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
10103 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) { in tg3_reset_hw()
10105 if (tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_reset_hw()
10111 } else if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10114 fw_len = tp->fw_len; in tg3_reset_hw()
10122 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10124 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10126 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10128 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10131 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10133 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10135 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10138 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10140 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10143 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_reset_hw()
10145 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_reset_hw()
10146 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_reset_hw()
10147 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10148 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) in tg3_reset_hw()
10157 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10161 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1) in tg3_reset_hw()
10164 tg3_setup_rxbd_thresholds(tp); in tg3_reset_hw()
10187 if (!tg3_flag(tp, 5717_PLUS)) in tg3_reset_hw()
10192 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10199 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10200 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { in tg3_reset_hw()
10202 if (tg3_flag(tp, JUMBO_RING_ENABLE)) { in tg3_reset_hw()
10207 val = TG3_RX_JMB_RING_SIZE(tp) << in tg3_reset_hw()
10211 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || in tg3_reset_hw()
10212 tg3_flag(tp, 57765_CLASS) || in tg3_reset_hw()
10213 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10221 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10222 val = TG3_RX_STD_RING_SIZE(tp); in tg3_reset_hw()
10232 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10236 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10239 tg3_rings_reset(tp); in tg3_reset_hw()
10242 __tg3_set_mac_addr(tp, false); in tg3_reset_hw()
10246 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10255 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10256 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10276 if (tg3_asic_rev(tp) == ASIC_REV_5717) in tg3_reset_hw()
10279 if (tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_reset_hw()
10280 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10281 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_reset_hw()
10286 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_reset_hw()
10287 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_reset_hw()
10288 if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10291 !tg3_flag(tp, IS_5788)) { in tg3_reset_hw()
10296 if (tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
10299 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_reset_hw()
10300 tp->dma_limit = 0; in tg3_reset_hw()
10301 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10303 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10307 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
10308 tg3_flag(tp, HW_TSO_2) || in tg3_reset_hw()
10309 tg3_flag(tp, HW_TSO_3)) in tg3_reset_hw()
10312 if (tg3_flag(tp, 57765_PLUS) || in tg3_reset_hw()
10313 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10314 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_reset_hw()
10317 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10318 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10321 if (tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_reset_hw()
10322 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_reset_hw()
10323 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10324 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_reset_hw()
10325 tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10328 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10334 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10335 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10346 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_reset_hw()
10347 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10348 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10351 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10363 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
10368 tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10389 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10391 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
10397 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10399 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10408 tg3_write_mem(tp, i, 0); in tg3_reset_hw()
10413 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10417 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10420 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10421 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10427 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10430 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
10431 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10432 if (!tg3_flag(tp, 5705_PLUS) && in tg3_reset_hw()
10433 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10434 tg3_asic_rev(tp) != ASIC_REV_5700) in tg3_reset_hw()
10435 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10436 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10445 if (!tg3_flag(tp, IS_NIC)) { in tg3_reset_hw()
10452 if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_reset_hw()
10456 if (tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_reset_hw()
10459 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10460 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10463 if (tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_reset_hw()
10464 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10467 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10470 if (tg3_flag(tp, USING_MSIX)) { in tg3_reset_hw()
10473 if (tp->irq_cnt > 1) in tg3_reset_hw()
10475 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_reset_hw()
10480 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
10491 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_reset_hw()
10492 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_reset_hw()
10493 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_reset_hw()
10494 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 || in tg3_reset_hw()
10495 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) { in tg3_reset_hw()
10498 !tg3_flag(tp, IS_5788)) { in tg3_reset_hw()
10504 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
10507 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_reset_hw()
10513 if (tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
10516 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10518 if (tg3_asic_rev(tp) == ASIC_REV_5703) { in tg3_reset_hw()
10521 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_reset_hw()
10525 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10532 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_reset_hw()
10533 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_reset_hw()
10535 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) in tg3_reset_hw()
10540 val |= tg3_lso_rd_dma_workaround_bit(tp); in tg3_reset_hw()
10542 tg3_flag_set(tp, 5719_5720_RDMA_BUG); in tg3_reset_hw()
10547 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10550 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_reset_hw()
10559 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_reset_hw()
10563 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
10564 tg3_flag(tp, HW_TSO_2) || in tg3_reset_hw()
10565 tg3_flag(tp, HW_TSO_3)) in tg3_reset_hw()
10568 if (tg3_flag(tp, ENABLE_TSS)) in tg3_reset_hw()
10573 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { in tg3_reset_hw()
10574 err = tg3_load_5701_a0_firmware_fix(tp); in tg3_reset_hw()
10579 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_reset_hw()
10583 tg3_load_57766_firmware(tp); in tg3_reset_hw()
10586 if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10587 err = tg3_load_tso_firmware(tp); in tg3_reset_hw()
10592 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10594 if (tg3_flag(tp, 5755_PLUS) || in tg3_reset_hw()
10595 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_reset_hw()
10596 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10598 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10599 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10601 tp->tx_mode &= ~val; in tg3_reset_hw()
10602 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10605 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10608 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_reset_hw()
10611 tg3_rss_write_indir_tbl(tp); in tg3_reset_hw()
10619 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10620 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
10621 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10623 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10624 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10626 if (tg3_flag(tp, ENABLE_RSS)) in tg3_reset_hw()
10627 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10634 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10637 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10640 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10644 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10647 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10648 if ((tg3_asic_rev(tp) == ASIC_REV_5704) && in tg3_reset_hw()
10649 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10657 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) in tg3_reset_hw()
10664 if (tg3_flag(tp, 57765_CLASS)) in tg3_reset_hw()
10670 if (tg3_asic_rev(tp) == ASIC_REV_5704 && in tg3_reset_hw()
10671 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10673 tg3_flag_set(tp, HW_AUTONEG); in tg3_reset_hw()
10676 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10677 tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_reset_hw()
10682 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10683 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10684 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10687 if (!tg3_flag(tp, USE_PHYLIB)) { in tg3_reset_hw()
10688 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10689 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10691 err = tg3_setup_phy(tp, false); in tg3_reset_hw()
10695 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10696 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10700 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { in tg3_reset_hw()
10701 tg3_writephy(tp, MII_TG3_TEST1, in tg3_reset_hw()
10703 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); in tg3_reset_hw()
10708 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10716 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) in tg3_reset_hw()
10720 if (tg3_flag(tp, ENABLE_ASF)) in tg3_reset_hw()
10770 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
10772 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, in tg3_reset_hw()
10775 tg3_write_sig_post_reset(tp, RESET_KIND_INIT); in tg3_reset_hw()
10783 static int tg3_init_hw(struct tg3 *tp, bool reset_phy) in tg3_init_hw() argument
10789 tg3_enable_register_access(tp); in tg3_init_hw()
10790 tg3_poll_fw(tp); in tg3_init_hw()
10792 tg3_switch_clocks(tp); in tg3_init_hw()
10796 return tg3_reset_hw(tp, reset_phy); in tg3_init_hw()
10800 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir) in tg3_sd_scan_scratchpad() argument
10806 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len); in tg3_sd_scan_scratchpad()
10819 struct tg3 *tp = dev_get_drvdata(dev); in tg3_show_temp() local
10822 spin_lock_bh(&tp->lock); in tg3_show_temp()
10823 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10825 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10845 static void tg3_hwmon_close(struct tg3 *tp) in tg3_hwmon_close() argument
10847 if (tp->hwmon_dev) { in tg3_hwmon_close()
10848 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10849 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10853 static void tg3_hwmon_open(struct tg3 *tp) in tg3_hwmon_open() argument
10857 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10860 tg3_sd_scan_scratchpad(tp, ocirs); in tg3_hwmon_open()
10873 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10874 tp, tg3_groups); in tg3_hwmon_open()
10875 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10876 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10881 static inline void tg3_hwmon_close(struct tg3 *tp) { } in tg3_hwmon_close() argument
10882 static inline void tg3_hwmon_open(struct tg3 *tp) { } in tg3_hwmon_open() argument
10893 static void tg3_periodic_fetch_stats(struct tg3 *tp) in tg3_periodic_fetch_stats() argument
10895 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10897 if (!tp->link_up) in tg3_periodic_fetch_stats()
10913 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) && in tg3_periodic_fetch_stats()
10919 val &= ~tg3_lso_rd_dma_workaround_bit(tp); in tg3_periodic_fetch_stats()
10921 tg3_flag_clear(tp, 5719_5720_RDMA_BUG); in tg3_periodic_fetch_stats()
10940 if (tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_periodic_fetch_stats()
10941 tg3_asic_rev(tp) != ASIC_REV_5762 && in tg3_periodic_fetch_stats()
10942 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 && in tg3_periodic_fetch_stats()
10943 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) { in tg3_periodic_fetch_stats()
10959 static void tg3_chk_missed_msi(struct tg3 *tp) in tg3_chk_missed_msi() argument
10963 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
10964 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
10984 struct tg3 *tp = from_timer(tp, t, timer); in tg3_timer() local
10986 spin_lock(&tp->lock); in tg3_timer()
10988 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
10989 spin_unlock(&tp->lock); in tg3_timer()
10993 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_timer()
10994 tg3_flag(tp, 57765_CLASS)) in tg3_timer()
10995 tg3_chk_missed_msi(tp); in tg3_timer()
10997 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { in tg3_timer()
11002 if (!tg3_flag(tp, TAGGED_STATUS)) { in tg3_timer()
11007 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
11009 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
11011 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11016 spin_unlock(&tp->lock); in tg3_timer()
11017 tg3_reset_task_schedule(tp); in tg3_timer()
11023 if (!--tp->timer_counter) { in tg3_timer()
11024 if (tg3_flag(tp, 5705_PLUS)) in tg3_timer()
11025 tg3_periodic_fetch_stats(tp); in tg3_timer()
11027 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
11028 tg3_phy_eee_enable(tp); in tg3_timer()
11030 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_timer()
11037 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
11044 tg3_setup_phy(tp, false); in tg3_timer()
11045 } else if (tg3_flag(tp, POLL_SERDES)) { in tg3_timer()
11049 if (tp->link_up && in tg3_timer()
11053 if (!tp->link_up && in tg3_timer()
11059 if (!tp->serdes_counter) { in tg3_timer()
11061 (tp->mac_mode & in tg3_timer()
11064 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11067 tg3_setup_phy(tp, false); in tg3_timer()
11069 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11070 tg3_flag(tp, 5780_CLASS)) { in tg3_timer()
11071 tg3_serdes_parallel_detect(tp); in tg3_timer()
11072 } else if (tg3_flag(tp, POLL_CPMU_LINK)) { in tg3_timer()
11077 if (link_up != tp->link_up) in tg3_timer()
11078 tg3_setup_phy(tp, false); in tg3_timer()
11081 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11101 if (!--tp->asf_counter) { in tg3_timer()
11102 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_timer()
11103 tg3_wait_for_event_ack(tp); in tg3_timer()
11105 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, in tg3_timer()
11107 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); in tg3_timer()
11108 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, in tg3_timer()
11111 tg3_generate_fw_event(tp); in tg3_timer()
11113 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11117 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL); in tg3_timer()
11119 spin_unlock(&tp->lock); in tg3_timer()
11122 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11123 add_timer(&tp->timer); in tg3_timer()
11126 static void tg3_timer_init(struct tg3 *tp) in tg3_timer_init() argument
11128 if (tg3_flag(tp, TAGGED_STATUS) && in tg3_timer_init()
11129 tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_timer_init()
11130 !tg3_flag(tp, 57765_CLASS)) in tg3_timer_init()
11131 tp->timer_offset = HZ; in tg3_timer_init()
11133 tp->timer_offset = HZ / 10; in tg3_timer_init()
11135 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11137 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11138 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11141 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11144 static void tg3_timer_start(struct tg3 *tp) in tg3_timer_start() argument
11146 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11147 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11149 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11150 add_timer(&tp->timer); in tg3_timer_start()
11153 static void tg3_timer_stop(struct tg3 *tp) in tg3_timer_stop() argument
11155 del_timer_sync(&tp->timer); in tg3_timer_stop()
11161 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy) in tg3_restart_hw() argument
11162 __releases(tp->lock) in tg3_restart_hw()
11163 __acquires(tp->lock) in tg3_restart_hw()
11167 err = tg3_init_hw(tp, reset_phy); in tg3_restart_hw()
11169 netdev_err(tp->dev, in tg3_restart_hw()
11171 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_restart_hw()
11172 tg3_full_unlock(tp); in tg3_restart_hw()
11173 tg3_timer_stop(tp); in tg3_restart_hw()
11174 tp->irq_sync = 0; in tg3_restart_hw()
11175 tg3_napi_enable(tp); in tg3_restart_hw()
11176 dev_close(tp->dev); in tg3_restart_hw()
11177 tg3_full_lock(tp, 0); in tg3_restart_hw()
11184 struct tg3 *tp = container_of(work, struct tg3, reset_task); in tg3_reset_task() local
11188 tg3_full_lock(tp, 0); in tg3_reset_task()
11190 if (tp->pcierr_recovery || !netif_running(tp->dev) || in tg3_reset_task()
11191 tp->pdev->error_state != pci_channel_io_normal) { in tg3_reset_task()
11192 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11193 tg3_full_unlock(tp); in tg3_reset_task()
11198 tg3_full_unlock(tp); in tg3_reset_task()
11200 tg3_phy_stop(tp); in tg3_reset_task()
11202 tg3_netif_stop(tp); in tg3_reset_task()
11204 tg3_full_lock(tp, 1); in tg3_reset_task()
11206 if (tg3_flag(tp, TX_RECOVERY_PENDING)) { in tg3_reset_task()
11207 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11208 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11209 tg3_flag_set(tp, MBOX_WRITE_REORDER); in tg3_reset_task()
11210 tg3_flag_clear(tp, TX_RECOVERY_PENDING); in tg3_reset_task()
11213 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_reset_task()
11214 err = tg3_init_hw(tp, true); in tg3_reset_task()
11216 tg3_full_unlock(tp); in tg3_reset_task()
11217 tp->irq_sync = 0; in tg3_reset_task()
11218 tg3_napi_enable(tp); in tg3_reset_task()
11222 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11223 dev_close(tp->dev); in tg3_reset_task()
11227 tg3_netif_start(tp); in tg3_reset_task()
11228 tg3_full_unlock(tp); in tg3_reset_task()
11229 tg3_phy_start(tp); in tg3_reset_task()
11230 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11235 static int tg3_request_irq(struct tg3 *tp, int irq_num) in tg3_request_irq() argument
11240 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11242 if (tp->irq_cnt == 1) in tg3_request_irq()
11243 name = tp->dev->name; in tg3_request_irq()
11248 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11251 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11254 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11257 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11261 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_request_irq()
11263 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_request_irq()
11268 if (tg3_flag(tp, TAGGED_STATUS)) in tg3_request_irq()
11276 static int tg3_test_interrupt(struct tg3 *tp) in tg3_test_interrupt() argument
11278 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11279 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11286 tg3_disable_ints(tp); in tg3_test_interrupt()
11294 if (tg3_flag(tp, 57765_PLUS)) { in tg3_test_interrupt()
11305 tg3_enable_ints(tp); in tg3_test_interrupt()
11307 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11322 if (tg3_flag(tp, 57765_PLUS) && in tg3_test_interrupt()
11329 tg3_disable_ints(tp); in tg3_test_interrupt()
11333 err = tg3_request_irq(tp, 0); in tg3_test_interrupt()
11340 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { in tg3_test_interrupt()
11353 static int tg3_test_msi(struct tg3 *tp) in tg3_test_msi() argument
11358 if (!tg3_flag(tp, USING_MSI)) in tg3_test_msi()
11364 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11365 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11368 err = tg3_test_interrupt(tp); in tg3_test_msi()
11370 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11380 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11384 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11386 pci_disable_msi(tp->pdev); in tg3_test_msi()
11388 tg3_flag_clear(tp, USING_MSI); in tg3_test_msi()
11389 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11391 err = tg3_request_irq(tp, 0); in tg3_test_msi()
11398 tg3_full_lock(tp, 1); in tg3_test_msi()
11400 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_test_msi()
11401 err = tg3_init_hw(tp, true); in tg3_test_msi()
11403 tg3_full_unlock(tp); in tg3_test_msi()
11406 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11411 static int tg3_request_firmware(struct tg3 *tp) in tg3_request_firmware() argument
11415 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11416 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11417 tp->fw_needed); in tg3_request_firmware()
11421 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11428 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11429 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11430 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11431 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11432 release_firmware(tp->fw); in tg3_request_firmware()
11433 tp->fw = NULL; in tg3_request_firmware()
11438 tp->fw_needed = NULL; in tg3_request_firmware()
11442 static u32 tg3_irq_count(struct tg3 *tp) in tg3_irq_count() argument
11444 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11452 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11458 static bool tg3_enable_msix(struct tg3 *tp) in tg3_enable_msix() argument
11463 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11464 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11465 if (!tp->rxq_cnt) in tg3_enable_msix()
11466 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11467 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11468 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11474 if (!tp->txq_req) in tg3_enable_msix()
11475 tp->txq_cnt = 1; in tg3_enable_msix()
11477 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11479 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11484 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11487 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11488 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11489 tp->irq_cnt, rc); in tg3_enable_msix()
11490 tp->irq_cnt = rc; in tg3_enable_msix()
11491 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11492 if (tp->txq_cnt) in tg3_enable_msix()
11493 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11496 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11497 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11499 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11500 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11504 if (tp->irq_cnt == 1) in tg3_enable_msix()
11507 tg3_flag_set(tp, ENABLE_RSS); in tg3_enable_msix()
11509 if (tp->txq_cnt > 1) in tg3_enable_msix()
11510 tg3_flag_set(tp, ENABLE_TSS); in tg3_enable_msix()
11512 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11517 static void tg3_ints_init(struct tg3 *tp) in tg3_ints_init() argument
11519 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && in tg3_ints_init()
11520 !tg3_flag(tp, TAGGED_STATUS)) { in tg3_ints_init()
11524 netdev_warn(tp->dev, in tg3_ints_init()
11529 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) in tg3_ints_init()
11530 tg3_flag_set(tp, USING_MSIX); in tg3_ints_init()
11531 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11532 tg3_flag_set(tp, USING_MSI); in tg3_ints_init()
11534 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
11536 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11538 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_ints_init()
11543 if (!tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
11544 tp->irq_cnt = 1; in tg3_ints_init()
11545 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11548 if (tp->irq_cnt == 1) { in tg3_ints_init()
11549 tp->txq_cnt = 1; in tg3_ints_init()
11550 tp->rxq_cnt = 1; in tg3_ints_init()
11551 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11552 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11556 static void tg3_ints_fini(struct tg3 *tp) in tg3_ints_fini() argument
11558 if (tg3_flag(tp, USING_MSIX)) in tg3_ints_fini()
11559 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11560 else if (tg3_flag(tp, USING_MSI)) in tg3_ints_fini()
11561 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11562 tg3_flag_clear(tp, USING_MSI); in tg3_ints_fini()
11563 tg3_flag_clear(tp, USING_MSIX); in tg3_ints_fini()
11564 tg3_flag_clear(tp, ENABLE_RSS); in tg3_ints_fini()
11565 tg3_flag_clear(tp, ENABLE_TSS); in tg3_ints_fini()
11568 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq, in tg3_start() argument
11571 struct net_device *dev = tp->dev; in tg3_start()
11578 tg3_ints_init(tp); in tg3_start()
11580 tg3_rss_check_indir_tbl(tp); in tg3_start()
11585 err = tg3_alloc_consistent(tp); in tg3_start()
11589 tg3_napi_init(tp); in tg3_start()
11591 tg3_napi_enable(tp); in tg3_start()
11593 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11594 err = tg3_request_irq(tp, i); in tg3_start()
11597 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11605 tg3_full_lock(tp, 0); in tg3_start()
11608 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_start()
11610 err = tg3_init_hw(tp, reset_phy); in tg3_start()
11612 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_start()
11613 tg3_free_rings(tp); in tg3_start()
11616 tg3_full_unlock(tp); in tg3_start()
11621 if (test_irq && tg3_flag(tp, USING_MSI)) { in tg3_start()
11622 err = tg3_test_msi(tp); in tg3_start()
11625 tg3_full_lock(tp, 0); in tg3_start()
11626 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_start()
11627 tg3_free_rings(tp); in tg3_start()
11628 tg3_full_unlock(tp); in tg3_start()
11633 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { in tg3_start()
11641 tg3_phy_start(tp); in tg3_start()
11643 tg3_hwmon_open(tp); in tg3_start()
11645 tg3_full_lock(tp, 0); in tg3_start()
11647 tg3_timer_start(tp); in tg3_start()
11648 tg3_flag_set(tp, INIT_COMPLETE); in tg3_start()
11649 tg3_enable_ints(tp); in tg3_start()
11651 tg3_ptp_resume(tp); in tg3_start()
11653 tg3_full_unlock(tp); in tg3_start()
11667 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11668 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11673 tg3_napi_disable(tp); in tg3_start()
11674 tg3_napi_fini(tp); in tg3_start()
11675 tg3_free_consistent(tp); in tg3_start()
11678 tg3_ints_fini(tp); in tg3_start()
11683 static void tg3_stop(struct tg3 *tp) in tg3_stop() argument
11687 tg3_reset_task_cancel(tp); in tg3_stop()
11688 tg3_netif_stop(tp); in tg3_stop()
11690 tg3_timer_stop(tp); in tg3_stop()
11692 tg3_hwmon_close(tp); in tg3_stop()
11694 tg3_phy_stop(tp); in tg3_stop()
11696 tg3_full_lock(tp, 1); in tg3_stop()
11698 tg3_disable_ints(tp); in tg3_stop()
11700 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_stop()
11701 tg3_free_rings(tp); in tg3_stop()
11702 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_stop()
11704 tg3_full_unlock(tp); in tg3_stop()
11706 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11707 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11711 tg3_ints_fini(tp); in tg3_stop()
11713 tg3_napi_fini(tp); in tg3_stop()
11715 tg3_free_consistent(tp); in tg3_stop()
11720 struct tg3 *tp = netdev_priv(dev); in tg3_open() local
11723 if (tp->pcierr_recovery) { in tg3_open()
11729 if (tp->fw_needed) { in tg3_open()
11730 err = tg3_request_firmware(tp); in tg3_open()
11731 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_open()
11733 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11734 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11735 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11736 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11737 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11739 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { in tg3_open()
11743 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11744 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_open()
11745 } else if (!tg3_flag(tp, TSO_CAPABLE)) { in tg3_open()
11746 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11747 tg3_flag_set(tp, TSO_CAPABLE); in tg3_open()
11751 tg3_carrier_off(tp); in tg3_open()
11753 err = tg3_power_up(tp); in tg3_open()
11757 tg3_full_lock(tp, 0); in tg3_open()
11759 tg3_disable_ints(tp); in tg3_open()
11760 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_open()
11762 tg3_full_unlock(tp); in tg3_open()
11764 err = tg3_start(tp, in tg3_open()
11765 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11768 tg3_frob_aux_power(tp, false); in tg3_open()
11769 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11777 struct tg3 *tp = netdev_priv(dev); in tg3_close() local
11779 if (tp->pcierr_recovery) { in tg3_close()
11785 tg3_stop(tp); in tg3_close()
11787 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11788 tg3_power_down_prepare(tp); in tg3_close()
11790 tg3_carrier_off(tp); in tg3_close()
11800 static u64 tg3_calc_crc_errors(struct tg3 *tp) in tg3_calc_crc_errors() argument
11802 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11804 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11805 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_calc_crc_errors()
11806 tg3_asic_rev(tp) == ASIC_REV_5701)) { in tg3_calc_crc_errors()
11809 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { in tg3_calc_crc_errors()
11810 tg3_writephy(tp, MII_TG3_TEST1, in tg3_calc_crc_errors()
11812 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); in tg3_calc_crc_errors()
11816 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11818 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11828 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats) in tg3_get_estats() argument
11830 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11831 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
11912 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats) in tg3_get_nstats() argument
11914 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
11915 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
11960 tg3_calc_crc_errors(tp); in tg3_get_nstats()
11976 for (i = 0; i < tp->irq_cnt; i++) { in tg3_get_nstats()
11977 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_get_nstats()
11995 struct tg3 *tp = netdev_priv(dev); in tg3_get_regs() local
12001 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
12004 tg3_full_lock(tp, 0); in tg3_get_regs()
12006 tg3_dump_legacy_regs(tp, (u32 *)_p); in tg3_get_regs()
12008 tg3_full_unlock(tp); in tg3_get_regs()
12013 struct tg3 *tp = netdev_priv(dev); in tg3_get_eeprom_len() local
12015 return tp->nvram_size; in tg3_get_eeprom_len()
12020 struct tg3 *tp = netdev_priv(dev); in tg3_get_eeprom() local
12026 if (tg3_flag(tp, NO_NVRAM)) in tg3_get_eeprom()
12036 if (tg3_flag(tp, CPMU_PRESENT)) { in tg3_get_eeprom()
12046 tg3_override_clk(tp); in tg3_get_eeprom()
12056 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
12068 ret = tg3_nvram_read_be32(tp, offset + i, &val); in tg3_get_eeprom()
12092 ret = tg3_nvram_read_be32(tp, b_offset, &val); in tg3_get_eeprom()
12102 tg3_restore_clk(tp); in tg3_get_eeprom()
12111 struct tg3 *tp = netdev_priv(dev); in tg3_set_eeprom() local
12117 if (tg3_flag(tp, NO_NVRAM) || in tg3_set_eeprom()
12126 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12140 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12157 ret = tg3_nvram_write_block(tp, offset, len, buf); in tg3_set_eeprom()
12168 struct tg3 *tp = netdev_priv(dev); in tg3_get_link_ksettings() local
12171 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_get_link_ksettings()
12173 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_link_ksettings()
12175 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_get_link_ksettings()
12183 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_link_ksettings()
12187 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12201 advertising = tp->link_config.advertising; in tg3_get_link_ksettings()
12202 if (tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_get_link_ksettings()
12203 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_link_ksettings()
12204 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12210 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12217 if (netif_running(dev) && tp->link_up) { in tg3_get_link_ksettings()
12218 cmd->base.speed = tp->link_config.active_speed; in tg3_get_link_ksettings()
12219 cmd->base.duplex = tp->link_config.active_duplex; in tg3_get_link_ksettings()
12222 tp->link_config.rmt_adv); in tg3_get_link_ksettings()
12224 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12225 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_link_ksettings()
12235 cmd->base.phy_address = tp->phy_addr; in tg3_get_link_ksettings()
12236 cmd->base.autoneg = tp->link_config.autoneg; in tg3_get_link_ksettings()
12243 struct tg3 *tp = netdev_priv(dev); in tg3_set_link_ksettings() local
12247 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_link_ksettings()
12249 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_link_ksettings()
12251 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_link_ksettings()
12272 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_link_ksettings()
12276 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_link_ksettings()
12297 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_link_ksettings()
12310 tg3_full_lock(tp, 0); in tg3_set_link_ksettings()
12312 tp->link_config.autoneg = cmd->base.autoneg; in tg3_set_link_ksettings()
12314 tp->link_config.advertising = (advertising | in tg3_set_link_ksettings()
12316 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_link_ksettings()
12317 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_link_ksettings()
12319 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12320 tp->link_config.speed = speed; in tg3_set_link_ksettings()
12321 tp->link_config.duplex = cmd->base.duplex; in tg3_set_link_ksettings()
12324 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_link_ksettings()
12326 tg3_warn_mgmt_link_flap(tp); in tg3_set_link_ksettings()
12329 tg3_setup_phy(tp, true); in tg3_set_link_ksettings()
12331 tg3_full_unlock(tp); in tg3_set_link_ksettings()
12338 struct tg3 *tp = netdev_priv(dev); in tg3_get_drvinfo() local
12341 strscpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12342 strscpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12347 struct tg3 *tp = netdev_priv(dev); in tg3_get_wol() local
12349 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12354 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12361 struct tg3 *tp = netdev_priv(dev); in tg3_set_wol() local
12362 struct device *dp = &tp->pdev->dev; in tg3_set_wol()
12367 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) in tg3_set_wol()
12373 tg3_flag_set(tp, WOL_ENABLE); in tg3_set_wol()
12375 tg3_flag_clear(tp, WOL_ENABLE); in tg3_set_wol()
12382 struct tg3 *tp = netdev_priv(dev); in tg3_get_msglevel() local
12383 return tp->msg_enable; in tg3_get_msglevel()
12388 struct tg3 *tp = netdev_priv(dev); in tg3_set_msglevel() local
12389 tp->msg_enable = value; in tg3_set_msglevel()
12394 struct tg3 *tp = netdev_priv(dev); in tg3_nway_reset() local
12400 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12403 tg3_warn_mgmt_link_flap(tp); in tg3_nway_reset()
12405 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_nway_reset()
12406 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12408 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_nway_reset()
12412 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12414 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_nway_reset()
12415 if (!tg3_readphy(tp, MII_BMCR, &bmcr) && in tg3_nway_reset()
12417 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12418 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | in tg3_nway_reset()
12422 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12433 struct tg3 *tp = netdev_priv(dev); in tg3_get_ringparam() local
12435 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12436 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
12437 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12443 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12444 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
12445 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12449 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12457 struct tg3 *tp = netdev_priv(dev); in tg3_set_ringparam() local
12461 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12462 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12465 (tg3_flag(tp, TSO_BUG) && in tg3_set_ringparam()
12470 tg3_phy_stop(tp); in tg3_set_ringparam()
12471 tg3_netif_stop(tp); in tg3_set_ringparam()
12475 tg3_full_lock(tp, irq_sync); in tg3_set_ringparam()
12477 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12479 if (tg3_flag(tp, MAX_RXPEND_64) && in tg3_set_ringparam()
12480 tp->rx_pending > 63) in tg3_set_ringparam()
12481 tp->rx_pending = 63; in tg3_set_ringparam()
12483 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_set_ringparam()
12484 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12486 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12487 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12490 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_set_ringparam()
12492 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_ringparam()
12493 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_set_ringparam()
12494 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_set_ringparam()
12497 err = tg3_restart_hw(tp, reset_phy); in tg3_set_ringparam()
12499 tg3_netif_start(tp); in tg3_set_ringparam()
12502 tg3_full_unlock(tp); in tg3_set_ringparam()
12505 tg3_phy_start(tp); in tg3_set_ringparam()
12512 struct tg3 *tp = netdev_priv(dev); in tg3_get_pauseparam() local
12514 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12516 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12521 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12529 struct tg3 *tp = netdev_priv(dev); in tg3_set_pauseparam() local
12533 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12534 tg3_warn_mgmt_link_flap(tp); in tg3_set_pauseparam()
12536 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_pauseparam()
12539 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_pauseparam()
12544 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12547 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12550 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12553 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12557 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12559 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12561 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12574 tg3_setup_flow_control(tp, 0, 0); in tg3_set_pauseparam()
12580 tg3_netif_stop(tp); in tg3_set_pauseparam()
12584 tg3_full_lock(tp, irq_sync); in tg3_set_pauseparam()
12587 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12589 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12591 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12593 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12595 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12597 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12600 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_set_pauseparam()
12602 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_pauseparam()
12603 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_set_pauseparam()
12604 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_set_pauseparam()
12607 err = tg3_restart_hw(tp, reset_phy); in tg3_set_pauseparam()
12609 tg3_netif_start(tp); in tg3_set_pauseparam()
12612 tg3_full_unlock(tp); in tg3_set_pauseparam()
12615 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12635 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxnfc() local
12637 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxnfc()
12642 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12643 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12660 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxfh_indir_size() local
12662 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxfh_indir_size()
12670 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxfh() local
12679 indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12687 struct tg3 *tp = netdev_priv(dev); in tg3_set_rxfh() local
12701 tp->rss_ind_tbl[i] = indir[i]; in tg3_set_rxfh()
12703 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS)) in tg3_set_rxfh()
12709 tg3_full_lock(tp, 0); in tg3_set_rxfh()
12710 tg3_rss_write_indir_tbl(tp); in tg3_set_rxfh()
12711 tg3_full_unlock(tp); in tg3_set_rxfh()
12719 struct tg3 *tp = netdev_priv(dev); in tg3_get_channels() local
12722 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12723 channel->max_tx = tp->txq_max; in tg3_get_channels()
12726 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12727 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12729 if (tp->rxq_req) in tg3_get_channels()
12730 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12732 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12734 if (tp->txq_req) in tg3_get_channels()
12735 channel->tx_count = tp->txq_req; in tg3_get_channels()
12737 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12744 struct tg3 *tp = netdev_priv(dev); in tg3_set_channels() local
12746 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_set_channels()
12749 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12750 channel->tx_count > tp->txq_max) in tg3_set_channels()
12753 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12754 tp->txq_req = channel->tx_count; in tg3_set_channels()
12759 tg3_stop(tp); in tg3_set_channels()
12761 tg3_carrier_off(tp); in tg3_set_channels()
12763 tg3_start(tp, true, false, false); in tg3_set_channels()
12786 struct tg3 *tp = netdev_priv(dev); in tg3_set_phys_id() local
12808 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12818 struct tg3 *tp = netdev_priv(dev); in tg3_get_ethtool_stats() local
12820 if (tp->hw_stats) in tg3_get_ethtool_stats()
12821 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats); in tg3_get_ethtool_stats()
12826 static __be32 *tg3_vpd_readblock(struct tg3 *tp, unsigned int *vpdlen) in tg3_vpd_readblock() argument
12833 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) in tg3_vpd_readblock()
12840 if (tg3_nvram_read(tp, offset, &val)) in tg3_vpd_readblock()
12850 if (tg3_nvram_read(tp, offset + 4, &offset)) in tg3_vpd_readblock()
12853 offset = tg3_nvram_logical_addr(tp, offset); in tg3_vpd_readblock()
12870 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) in tg3_vpd_readblock()
12875 buf = pci_vpd_alloc(tp->pdev, vpdlen); in tg3_vpd_readblock()
12897 static int tg3_test_nvram(struct tg3 *tp) in tg3_test_nvram() argument
12904 if (tg3_flag(tp, NO_NVRAM)) in tg3_test_nvram()
12907 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_test_nvram()
12950 err = tg3_nvram_read_be32(tp, i, &buf[j]); in tg3_test_nvram()
13041 buf = tg3_vpd_readblock(tp, &len); in tg3_test_nvram()
13057 static int tg3_test_link(struct tg3 *tp) in tg3_test_link() argument
13061 if (!netif_running(tp->dev)) in tg3_test_link()
13064 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13070 if (tp->link_up) in tg3_test_link()
13081 static int tg3_test_registers(struct tg3 *tp) in tg3_test_registers() argument
13231 if (tg3_flag(tp, 5705_PLUS)) { in tg3_test_registers()
13233 if (tg3_flag(tp, 5750_PLUS)) in tg3_test_registers()
13244 if (tg3_flag(tp, IS_5788) && in tg3_test_registers()
13294 if (netif_msg_hw(tp)) in tg3_test_registers()
13295 netdev_err(tp->dev, in tg3_test_registers()
13301 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) in tg3_do_mem_test() argument
13311 tg3_write_mem(tp, offset + j, test_pattern[i]); in tg3_do_mem_test()
13312 tg3_read_mem(tp, offset + j, &val); in tg3_do_mem_test()
13320 static int tg3_test_memory(struct tg3 *tp) in tg3_test_memory() argument
13367 if (tg3_flag(tp, 5717_PLUS)) in tg3_test_memory()
13369 else if (tg3_flag(tp, 57765_CLASS) || in tg3_test_memory()
13370 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_test_memory()
13372 else if (tg3_flag(tp, 5755_PLUS)) in tg3_test_memory()
13374 else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_test_memory()
13376 else if (tg3_flag(tp, 5705_PLUS)) in tg3_test_memory()
13382 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); in tg3_test_memory()
13413 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) in tg3_run_loopback() argument
13424 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13426 tnapi = &tp->napi[0]; in tg3_run_loopback()
13427 rnapi = &tp->napi[0]; in tg3_run_loopback()
13428 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13429 if (tg3_flag(tp, ENABLE_RSS)) in tg3_run_loopback()
13430 rnapi = &tp->napi[1]; in tg3_run_loopback()
13431 if (tg3_flag(tp, ENABLE_TSS)) in tg3_run_loopback()
13432 tnapi = &tp->napi[1]; in tg3_run_loopback()
13439 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13444 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13468 if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
13469 tg3_flag(tp, HW_TSO_2) || in tg3_run_loopback()
13470 tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
13478 if (tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
13483 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_run_loopback()
13485 else if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
13486 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_run_loopback()
13497 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in tg3_run_loopback()
13505 map = dma_map_single(&tp->pdev->dev, skb->data, tx_len, DMA_TO_DEVICE); in tg3_run_loopback()
13506 if (dma_mapping_error(&tp->pdev->dev, map)) { in tg3_run_loopback()
13515 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13542 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13604 dma_sync_single_for_cpu(&tp->pdev->dev, map, rx_len, in tg3_run_loopback()
13607 rx_data += TG3_RX_OFFSET(tp); in tg3_run_loopback()
13629 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) in tg3_test_loopback() argument
13635 if (tp->dma_limit) in tg3_test_loopback()
13636 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13638 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13639 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13641 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13649 err = tg3_reset_hw(tp, true); in tg3_test_loopback()
13658 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_test_loopback()
13672 if (tg3_asic_rev(tp) != ASIC_REV_5780 && in tg3_test_loopback()
13673 !tg3_flag(tp, CPMU_PRESENT)) { in tg3_test_loopback()
13674 tg3_mac_loopback(tp, true); in tg3_test_loopback()
13676 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13679 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13680 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13683 tg3_mac_loopback(tp, false); in tg3_test_loopback()
13686 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13687 !tg3_flag(tp, USE_PHYLIB)) { in tg3_test_loopback()
13690 tg3_phy_lpbk_set(tp, 0, false); in tg3_test_loopback()
13699 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13701 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
13702 tg3_run_loopback(tp, ETH_FRAME_LEN, true)) in tg3_test_loopback()
13704 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13705 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13709 tg3_phy_lpbk_set(tp, 0, true); in tg3_test_loopback()
13717 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13720 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
13721 tg3_run_loopback(tp, ETH_FRAME_LEN, true)) in tg3_test_loopback()
13724 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13725 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13731 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13732 tg3_phy_toggle_apd(tp, true); in tg3_test_loopback()
13739 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13747 struct tg3 *tp = netdev_priv(dev); in tg3_self_test() local
13750 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13751 if (tg3_power_up(tp)) { in tg3_self_test()
13756 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_self_test()
13761 if (tg3_test_nvram(tp) != 0) { in tg3_self_test()
13765 if (!doextlpbk && tg3_test_link(tp)) { in tg3_self_test()
13773 tg3_phy_stop(tp); in tg3_self_test()
13774 tg3_netif_stop(tp); in tg3_self_test()
13778 tg3_full_lock(tp, irq_sync); in tg3_self_test()
13779 tg3_halt(tp, RESET_KIND_SUSPEND, 1); in tg3_self_test()
13780 err = tg3_nvram_lock(tp); in tg3_self_test()
13781 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_self_test()
13782 if (!tg3_flag(tp, 5705_PLUS)) in tg3_self_test()
13783 tg3_halt_cpu(tp, TX_CPU_BASE); in tg3_self_test()
13785 tg3_nvram_unlock(tp); in tg3_self_test()
13787 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13788 tg3_phy_reset(tp); in tg3_self_test()
13790 if (tg3_test_registers(tp) != 0) { in tg3_self_test()
13795 if (tg3_test_memory(tp) != 0) { in tg3_self_test()
13803 if (tg3_test_loopback(tp, data, doextlpbk)) in tg3_self_test()
13806 tg3_full_unlock(tp); in tg3_self_test()
13808 if (tg3_test_interrupt(tp) != 0) { in tg3_self_test()
13813 tg3_full_lock(tp, 0); in tg3_self_test()
13815 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_self_test()
13817 tg3_flag_set(tp, INIT_COMPLETE); in tg3_self_test()
13818 err2 = tg3_restart_hw(tp, true); in tg3_self_test()
13820 tg3_netif_start(tp); in tg3_self_test()
13823 tg3_full_unlock(tp); in tg3_self_test()
13826 tg3_phy_start(tp); in tg3_self_test()
13828 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13829 tg3_power_down_prepare(tp); in tg3_self_test()
13835 struct tg3 *tp = netdev_priv(dev); in tg3_hwtstamp_set() local
13838 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_hwtstamp_set()
13850 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13853 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13857 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13861 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13865 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13869 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13873 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13877 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13881 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13885 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13889 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13893 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13897 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13904 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
13906 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
13909 tg3_flag_set(tp, TX_TSTAMP_EN); in tg3_hwtstamp_set()
13911 tg3_flag_clear(tp, TX_TSTAMP_EN); in tg3_hwtstamp_set()
13919 struct tg3 *tp = netdev_priv(dev); in tg3_hwtstamp_get() local
13922 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_hwtstamp_get()
13926 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ? in tg3_hwtstamp_get()
13929 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
13981 struct tg3 *tp = netdev_priv(dev); in tg3_ioctl() local
13984 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_ioctl()
13986 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
13988 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_ioctl()
13994 data->phy_id = tp->phy_addr; in tg3_ioctl()
14000 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14006 spin_lock_bh(&tp->lock); in tg3_ioctl()
14007 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14009 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14017 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14023 spin_lock_bh(&tp->lock); in tg3_ioctl()
14024 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14026 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14048 struct tg3 *tp = netdev_priv(dev); in tg3_get_coalesce() local
14050 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14059 struct tg3 *tp = netdev_priv(dev); in tg3_set_coalesce() local
14063 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_set_coalesce()
14085 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14086 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14087 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14088 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14089 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14090 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14091 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14092 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14093 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14096 tg3_full_lock(tp, 0); in tg3_set_coalesce()
14097 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14098 tg3_full_unlock(tp); in tg3_set_coalesce()
14105 struct tg3 *tp = netdev_priv(dev); in tg3_set_eee() local
14107 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14108 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14112 if (edata->advertised != tp->eee.advertised) { in tg3_set_eee()
14113 netdev_warn(tp->dev, in tg3_set_eee()
14119 netdev_warn(tp->dev, in tg3_set_eee()
14125 tp->eee = *edata; in tg3_set_eee()
14127 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14128 tg3_warn_mgmt_link_flap(tp); in tg3_set_eee()
14130 if (netif_running(tp->dev)) { in tg3_set_eee()
14131 tg3_full_lock(tp, 0); in tg3_set_eee()
14132 tg3_setup_eee(tp); in tg3_set_eee()
14133 tg3_phy_reset(tp); in tg3_set_eee()
14134 tg3_full_unlock(tp); in tg3_set_eee()
14142 struct tg3 *tp = netdev_priv(dev); in tg3_get_eee() local
14144 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14145 netdev_warn(tp->dev, in tg3_get_eee()
14150 *edata = tp->eee; in tg3_get_eee()
14199 struct tg3 *tp = netdev_priv(dev); in tg3_get_stats64() local
14201 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14202 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) { in tg3_get_stats64()
14203 *stats = tp->net_stats_prev; in tg3_get_stats64()
14204 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14208 tg3_get_nstats(tp, stats); in tg3_get_stats64()
14209 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14214 struct tg3 *tp = netdev_priv(dev); in tg3_set_rx_mode() local
14219 tg3_full_lock(tp, 0); in tg3_set_rx_mode()
14221 tg3_full_unlock(tp); in tg3_set_rx_mode()
14224 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, in tg3_set_mtu() argument
14230 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
14232 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_set_mtu()
14234 tg3_flag_set(tp, JUMBO_RING_ENABLE); in tg3_set_mtu()
14237 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
14238 tg3_flag_set(tp, TSO_CAPABLE); in tg3_set_mtu()
14241 tg3_flag_clear(tp, JUMBO_RING_ENABLE); in tg3_set_mtu()
14247 struct tg3 *tp = netdev_priv(dev); in tg3_change_mtu() local
14255 tg3_set_mtu(dev, tp, new_mtu); in tg3_change_mtu()
14259 tg3_phy_stop(tp); in tg3_change_mtu()
14261 tg3_netif_stop(tp); in tg3_change_mtu()
14263 tg3_set_mtu(dev, tp, new_mtu); in tg3_change_mtu()
14265 tg3_full_lock(tp, 1); in tg3_change_mtu()
14267 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_change_mtu()
14272 if (tg3_asic_rev(tp) == ASIC_REV_57766 || in tg3_change_mtu()
14273 tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_change_mtu()
14274 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_change_mtu()
14275 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_change_mtu()
14278 err = tg3_restart_hw(tp, reset_phy); in tg3_change_mtu()
14281 tg3_netif_start(tp); in tg3_change_mtu()
14283 tg3_full_unlock(tp); in tg3_change_mtu()
14286 tg3_phy_start(tp); in tg3_change_mtu()
14309 static void tg3_get_eeprom_size(struct tg3 *tp) in tg3_get_eeprom_size() argument
14313 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14315 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_get_eeprom_size()
14330 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14331 if (tg3_nvram_read(tp, cursize, &val) != 0) in tg3_get_eeprom_size()
14340 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14343 static void tg3_get_nvram_size(struct tg3 *tp) in tg3_get_nvram_size() argument
14347 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) in tg3_get_nvram_size()
14352 tg3_get_eeprom_size(tp); in tg3_get_nvram_size()
14356 if (tg3_nvram_read(tp, 0xf0, &val) == 0) { in tg3_get_nvram_size()
14369 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14373 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14376 static void tg3_get_nvram_info(struct tg3 *tp) in tg3_get_nvram_info() argument
14382 tg3_flag_set(tp, FLASH); in tg3_get_nvram_info()
14388 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_get_nvram_info()
14389 tg3_flag(tp, 5780_CLASS)) { in tg3_get_nvram_info()
14392 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14393 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14394 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14397 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14398 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14401 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14402 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14403 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14406 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14407 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14408 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14411 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14412 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14416 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14417 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14421 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14422 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14423 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14427 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) in tg3_nvram_get_pagesize() argument
14431 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14434 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14437 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14440 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14443 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14446 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14449 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14454 static void tg3_get_5752_nvram_info(struct tg3 *tp) in tg3_get_5752_nvram_info() argument
14462 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5752_nvram_info()
14467 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14468 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14471 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14472 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14473 tg3_flag_set(tp, FLASH); in tg3_get_5752_nvram_info()
14478 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14479 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14480 tg3_flag_set(tp, FLASH); in tg3_get_5752_nvram_info()
14484 if (tg3_flag(tp, FLASH)) { in tg3_get_5752_nvram_info()
14485 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5752_nvram_info()
14488 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14495 static void tg3_get_5755_nvram_info(struct tg3 *tp) in tg3_get_5755_nvram_info() argument
14503 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5755_nvram_info()
14513 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14514 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5755_nvram_info()
14515 tg3_flag_set(tp, FLASH); in tg3_get_5755_nvram_info()
14516 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14519 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14522 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14525 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14531 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14532 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5755_nvram_info()
14533 tg3_flag_set(tp, FLASH); in tg3_get_5755_nvram_info()
14534 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14536 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14540 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14544 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14551 static void tg3_get_5787_nvram_info(struct tg3 *tp) in tg3_get_5787_nvram_info() argument
14562 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14563 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14564 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14573 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14574 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14575 tg3_flag_set(tp, FLASH); in tg3_get_5787_nvram_info()
14576 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14581 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14582 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14583 tg3_flag_set(tp, FLASH); in tg3_get_5787_nvram_info()
14584 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14589 static void tg3_get_5761_nvram_info(struct tg3 *tp) in tg3_get_5761_nvram_info() argument
14597 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5761_nvram_info()
14611 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14612 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5761_nvram_info()
14613 tg3_flag_set(tp, FLASH); in tg3_get_5761_nvram_info()
14614 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5761_nvram_info()
14615 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14625 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14626 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5761_nvram_info()
14627 tg3_flag_set(tp, FLASH); in tg3_get_5761_nvram_info()
14628 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14633 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14640 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14646 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14652 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14658 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14664 static void tg3_get_5906_nvram_info(struct tg3 *tp) in tg3_get_5906_nvram_info() argument
14666 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14667 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5906_nvram_info()
14668 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14671 static void tg3_get_57780_nvram_info(struct tg3 *tp) in tg3_get_57780_nvram_info() argument
14680 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14681 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14682 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14694 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14695 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14696 tg3_flag_set(tp, FLASH); in tg3_get_57780_nvram_info()
14702 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14706 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14710 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14717 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14718 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14719 tg3_flag_set(tp, FLASH); in tg3_get_57780_nvram_info()
14723 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14726 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14729 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14734 tg3_flag_set(tp, NO_NVRAM); in tg3_get_57780_nvram_info()
14738 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_57780_nvram_info()
14739 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14740 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_57780_nvram_info()
14744 static void tg3_get_5717_nvram_info(struct tg3 *tp) in tg3_get_5717_nvram_info() argument
14753 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14754 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14755 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14767 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14768 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14769 tg3_flag_set(tp, FLASH); in tg3_get_5717_nvram_info()
14777 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14780 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14794 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14795 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14796 tg3_flag_set(tp, FLASH); in tg3_get_5717_nvram_info()
14805 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14808 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14813 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5717_nvram_info()
14817 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5717_nvram_info()
14818 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14819 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5717_nvram_info()
14822 static void tg3_get_5720_nvram_info(struct tg3 *tp) in tg3_get_5720_nvram_info() argument
14829 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_get_5720_nvram_info()
14831 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14841 tp->nvram_pagesize = 4096; in tg3_get_5720_nvram_info()
14842 tp->nvram_jedecnum = JEDEC_MACRONIX; in tg3_get_5720_nvram_info()
14843 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14844 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5720_nvram_info()
14845 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14847 tp->nvram_size = in tg3_get_5720_nvram_info()
14871 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14872 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14877 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14879 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14893 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14894 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14895 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14901 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14906 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14910 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14913 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_get_5720_nvram_info()
14914 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14936 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
14937 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14938 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14945 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14951 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14957 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14960 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_get_5720_nvram_info()
14961 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14966 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14970 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5720_nvram_info()
14971 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
14972 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5720_nvram_info()
14974 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_get_5720_nvram_info()
14977 if (tg3_nvram_read(tp, 0, &val)) in tg3_get_5720_nvram_info()
14982 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14987 static void tg3_nvram_init(struct tg3 *tp) in tg3_nvram_init() argument
14989 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_nvram_init()
14991 tg3_flag_clear(tp, NVRAM); in tg3_nvram_init()
14992 tg3_flag_clear(tp, NVRAM_BUFFERED); in tg3_nvram_init()
14993 tg3_flag_set(tp, NO_NVRAM); in tg3_nvram_init()
15009 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_nvram_init()
15010 tg3_asic_rev(tp) != ASIC_REV_5701) { in tg3_nvram_init()
15011 tg3_flag_set(tp, NVRAM); in tg3_nvram_init()
15013 if (tg3_nvram_lock(tp)) { in tg3_nvram_init()
15014 netdev_warn(tp->dev, in tg3_nvram_init()
15019 tg3_enable_nvram_access(tp); in tg3_nvram_init()
15021 tp->nvram_size = 0; in tg3_nvram_init()
15023 if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_nvram_init()
15024 tg3_get_5752_nvram_info(tp); in tg3_nvram_init()
15025 else if (tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_nvram_init()
15026 tg3_get_5755_nvram_info(tp); in tg3_nvram_init()
15027 else if (tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_nvram_init()
15028 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_nvram_init()
15029 tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_nvram_init()
15030 tg3_get_5787_nvram_info(tp); in tg3_nvram_init()
15031 else if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_nvram_init()
15032 tg3_get_5761_nvram_info(tp); in tg3_nvram_init()
15033 else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_nvram_init()
15034 tg3_get_5906_nvram_info(tp); in tg3_nvram_init()
15035 else if (tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_nvram_init()
15036 tg3_flag(tp, 57765_CLASS)) in tg3_nvram_init()
15037 tg3_get_57780_nvram_info(tp); in tg3_nvram_init()
15038 else if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_nvram_init()
15039 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_nvram_init()
15040 tg3_get_5717_nvram_info(tp); in tg3_nvram_init()
15041 else if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_nvram_init()
15042 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_nvram_init()
15043 tg3_get_5720_nvram_info(tp); in tg3_nvram_init()
15045 tg3_get_nvram_info(tp); in tg3_nvram_init()
15047 if (tp->nvram_size == 0) in tg3_nvram_init()
15048 tg3_get_nvram_size(tp); in tg3_nvram_init()
15050 tg3_disable_nvram_access(tp); in tg3_nvram_init()
15051 tg3_nvram_unlock(tp); in tg3_nvram_init()
15054 tg3_flag_clear(tp, NVRAM); in tg3_nvram_init()
15055 tg3_flag_clear(tp, NVRAM_BUFFERED); in tg3_nvram_init()
15057 tg3_get_eeprom_size(tp); in tg3_nvram_init()
15130 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp) in tg3_lookup_by_subsys() argument
15136 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15138 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15144 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) in tg3_get_eeprom_hw_cfg() argument
15148 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15149 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15152 tg3_flag_set(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15153 tg3_flag_set(tp, WOL_CAP); in tg3_get_eeprom_hw_cfg()
15155 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_eeprom_hw_cfg()
15157 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15158 tg3_flag_set(tp, IS_NIC); in tg3_get_eeprom_hw_cfg()
15162 tg3_flag_set(tp, ASPM_WORKAROUND); in tg3_get_eeprom_hw_cfg()
15165 tg3_flag_set(tp, WOL_ENABLE); in tg3_get_eeprom_hw_cfg()
15166 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15171 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); in tg3_get_eeprom_hw_cfg()
15178 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); in tg3_get_eeprom_hw_cfg()
15179 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15181 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); in tg3_get_eeprom_hw_cfg()
15183 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_get_eeprom_hw_cfg()
15184 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_get_eeprom_hw_cfg()
15185 tg3_asic_rev(tp) != ASIC_REV_5703 && in tg3_get_eeprom_hw_cfg()
15187 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); in tg3_get_eeprom_hw_cfg()
15189 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_get_eeprom_hw_cfg()
15190 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); in tg3_get_eeprom_hw_cfg()
15192 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_eeprom_hw_cfg()
15193 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_eeprom_hw_cfg()
15194 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_get_eeprom_hw_cfg()
15195 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5); in tg3_get_eeprom_hw_cfg()
15201 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); in tg3_get_eeprom_hw_cfg()
15212 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15214 if (!tg3_flag(tp, 5705_PLUS)) in tg3_get_eeprom_hw_cfg()
15215 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15217 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15220 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15229 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15233 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15237 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15242 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
15243 tg3_asic_rev(tp) == ASIC_REV_5701) in tg3_get_eeprom_hw_cfg()
15244 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15249 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15250 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && in tg3_get_eeprom_hw_cfg()
15251 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1) in tg3_get_eeprom_hw_cfg()
15252 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15255 if (tg3_flag(tp, 5717_PLUS) || in tg3_get_eeprom_hw_cfg()
15256 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_eeprom_hw_cfg()
15257 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15263 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15267 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15268 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) in tg3_get_eeprom_hw_cfg()
15269 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15275 if ((tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
15276 tg3_asic_rev(tp) == ASIC_REV_5701) && in tg3_get_eeprom_hw_cfg()
15277 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15278 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15280 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) in tg3_get_eeprom_hw_cfg()
15281 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15284 tg3_flag_set(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15285 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15287 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15288 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15289 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15291 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15292 tg3_flag_set(tp, IS_NIC); in tg3_get_eeprom_hw_cfg()
15296 tg3_flag_set(tp, ENABLE_ASF); in tg3_get_eeprom_hw_cfg()
15297 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15298 tg3_flag_set(tp, ASF_NEW_HANDSHAKE); in tg3_get_eeprom_hw_cfg()
15302 tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15303 tg3_flag_set(tp, ENABLE_APE); in tg3_get_eeprom_hw_cfg()
15305 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15307 tg3_flag_clear(tp, WOL_CAP); in tg3_get_eeprom_hw_cfg()
15309 if (tg3_flag(tp, WOL_CAP) && in tg3_get_eeprom_hw_cfg()
15311 tg3_flag_set(tp, WOL_ENABLE); in tg3_get_eeprom_hw_cfg()
15312 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15316 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15321 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15323 if ((tg3_flag(tp, 57765_PLUS) || in tg3_get_eeprom_hw_cfg()
15324 (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_get_eeprom_hw_cfg()
15325 tg3_chip_rev(tp) != CHIPREV_5784_AX)) && in tg3_get_eeprom_hw_cfg()
15327 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15329 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_get_eeprom_hw_cfg()
15332 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); in tg3_get_eeprom_hw_cfg()
15333 if (tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_get_eeprom_hw_cfg()
15334 !tg3_flag(tp, 57765_PLUS) && in tg3_get_eeprom_hw_cfg()
15336 tg3_flag_set(tp, ASPM_WORKAROUND); in tg3_get_eeprom_hw_cfg()
15338 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15340 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15344 tg3_flag_set(tp, RGMII_INBAND_DISABLE); in tg3_get_eeprom_hw_cfg()
15346 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); in tg3_get_eeprom_hw_cfg()
15348 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); in tg3_get_eeprom_hw_cfg()
15351 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15354 if (tg3_flag(tp, WOL_CAP)) in tg3_get_eeprom_hw_cfg()
15355 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15356 tg3_flag(tp, WOL_ENABLE)); in tg3_get_eeprom_hw_cfg()
15358 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15361 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val) in tg3_ape_otp_read() argument
15366 err = tg3_nvram_lock(tp); in tg3_ape_otp_read()
15370 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE); in tg3_ape_otp_read()
15371 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN | in tg3_ape_otp_read()
15373 tg3_ape_read32(tp, TG3_APE_OTP_CTRL); in tg3_ape_otp_read()
15377 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS); in tg3_ape_otp_read()
15379 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA); in tg3_ape_otp_read()
15385 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0); in tg3_ape_otp_read()
15387 tg3_nvram_unlock(tp); in tg3_ape_otp_read()
15394 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd) in tg3_issue_otp_command() argument
15417 static u32 tg3_read_otp_phycfg(struct tg3 *tp) in tg3_read_otp_phycfg() argument
15423 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) in tg3_read_otp_phycfg()
15428 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
15435 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
15443 static void tg3_phy_init_link_config(struct tg3 *tp) in tg3_phy_init_link_config() argument
15447 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15448 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15453 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15462 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15463 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15464 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15465 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15466 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15467 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15469 tp->old_link = -1; in tg3_phy_init_link_config()
15472 static int tg3_phy_probe(struct tg3 *tp) in tg3_phy_probe() argument
15479 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_phy_probe()
15480 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15482 if (tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
15483 switch (tp->pci_fn) { in tg3_phy_probe()
15485 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15488 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15491 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15494 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15499 if (!tg3_flag(tp, ENABLE_ASF) && in tg3_phy_probe()
15500 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15501 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15502 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15505 if (tg3_flag(tp, USE_PHYLIB)) in tg3_phy_probe()
15506 return tg3_phy_init(tp); in tg3_phy_probe()
15512 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
15520 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); in tg3_phy_probe()
15521 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); in tg3_phy_probe()
15531 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15533 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15535 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15537 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15547 p = tg3_lookup_by_subsys(tp); in tg3_phy_probe()
15549 tp->phy_id = p->phy_id; in tg3_phy_probe()
15550 } else if (!tg3_flag(tp, IS_SSB_CORE)) { in tg3_phy_probe()
15561 if (!tp->phy_id || in tg3_phy_probe()
15562 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15563 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15567 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15568 (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_phy_probe()
15569 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_phy_probe()
15570 tg3_asic_rev(tp) == ASIC_REV_57766 || in tg3_phy_probe()
15571 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_phy_probe()
15572 (tg3_asic_rev(tp) == ASIC_REV_5717 && in tg3_phy_probe()
15573 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) || in tg3_phy_probe()
15574 (tg3_asic_rev(tp) == ASIC_REV_57765 && in tg3_phy_probe()
15575 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) { in tg3_phy_probe()
15576 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15578 tp->eee.supported = SUPPORTED_100baseT_Full | in tg3_phy_probe()
15580 tp->eee.advertised = ADVERTISED_100baseT_Full | in tg3_phy_probe()
15582 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15583 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15584 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15587 tg3_phy_init_link_config(tp); in tg3_phy_probe()
15589 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15590 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15591 !tg3_flag(tp, ENABLE_APE) && in tg3_phy_probe()
15592 !tg3_flag(tp, ENABLE_ASF)) { in tg3_phy_probe()
15595 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_phy_probe()
15596 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_phy_probe()
15600 err = tg3_phy_reset(tp); in tg3_phy_probe()
15604 tg3_phy_set_wirespeed(tp); in tg3_phy_probe()
15606 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) { in tg3_phy_probe()
15607 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15608 tp->link_config.flowctrl); in tg3_phy_probe()
15610 tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()
15616 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15617 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
15621 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
15627 static void tg3_read_vpd(struct tg3 *tp) in tg3_read_vpd() argument
15633 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); in tg3_read_vpd()
15650 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15651 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, vpd_data + i); in tg3_read_vpd()
15662 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15666 if (tp->board_part_number[0]) in tg3_read_vpd()
15670 if (tg3_asic_rev(tp) == ASIC_REV_5717) { in tg3_read_vpd()
15671 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15672 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15673 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15674 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15675 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15678 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_read_vpd()
15679 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15680 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15681 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15682 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15683 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15684 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15685 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15686 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15689 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) { in tg3_read_vpd()
15690 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15691 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15692 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15693 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15694 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15695 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15696 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15697 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15698 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15699 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15700 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15701 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15704 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_read_vpd()
15705 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15706 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15707 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15708 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15709 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15710 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15711 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15712 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15715 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_read_vpd()
15716 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15719 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15723 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) in tg3_fw_img_is_valid() argument
15727 if (tg3_nvram_read(tp, offset, &val) || in tg3_fw_img_is_valid()
15729 tg3_nvram_read(tp, offset + 4, &val) || in tg3_fw_img_is_valid()
15736 static void tg3_read_bc_ver(struct tg3 *tp) in tg3_read_bc_ver() argument
15742 if (tg3_nvram_read(tp, 0xc, &offset) || in tg3_read_bc_ver()
15743 tg3_nvram_read(tp, 0x4, &start)) in tg3_read_bc_ver()
15746 offset = tg3_nvram_logical_addr(tp, offset); in tg3_read_bc_ver()
15748 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_bc_ver()
15752 if (tg3_nvram_read(tp, offset + 4, &val)) in tg3_read_bc_ver()
15759 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15763 tg3_nvram_read(tp, offset + 8, &ver_offset)) in tg3_read_bc_ver()
15769 if (tg3_nvram_read_be32(tp, offset + i, &v)) in tg3_read_bc_ver()
15772 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15777 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) in tg3_read_bc_ver()
15783 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15788 static void tg3_read_hwsb_ver(struct tg3 *tp) in tg3_read_hwsb_ver() argument
15793 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) in tg3_read_hwsb_ver()
15801 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15804 static void tg3_read_sb_ver(struct tg3 *tp, u32 val) in tg3_read_sb_ver() argument
15808 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15836 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_sb_ver()
15848 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15849 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15853 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15855 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15859 static void tg3_read_mgmtfw_ver(struct tg3 *tp) in tg3_read_mgmtfw_ver() argument
15867 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_mgmtfw_ver()
15877 if (!tg3_flag(tp, 5705_PLUS)) in tg3_read_mgmtfw_ver()
15879 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15882 if (tg3_nvram_read(tp, offset + 4, &offset) || in tg3_read_mgmtfw_ver()
15883 !tg3_fw_img_is_valid(tp, offset) || in tg3_read_mgmtfw_ver()
15884 tg3_nvram_read(tp, offset + 8, &val)) in tg3_read_mgmtfw_ver()
15889 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15891 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15892 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
15896 if (tg3_nvram_read_be32(tp, offset, &v)) in tg3_read_mgmtfw_ver()
15902 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
15906 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
15911 static void tg3_probe_ncsi(struct tg3 *tp) in tg3_probe_ncsi() argument
15915 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_probe_ncsi()
15919 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_probe_ncsi()
15923 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) in tg3_probe_ncsi()
15924 tg3_flag_set(tp, APE_HAS_NCSI); in tg3_probe_ncsi()
15927 static void tg3_read_dash_ver(struct tg3 *tp) in tg3_read_dash_ver() argument
15933 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); in tg3_read_dash_ver()
15935 if (tg3_flag(tp, APE_HAS_NCSI)) in tg3_read_dash_ver()
15937 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
15942 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
15944 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
15952 static void tg3_read_otp_ver(struct tg3 *tp) in tg3_read_otp_ver() argument
15956 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_read_otp_ver()
15959 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) && in tg3_read_otp_ver()
15960 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) && in tg3_read_otp_ver()
15972 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
15973 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
15977 static void tg3_read_fw_ver(struct tg3 *tp) in tg3_read_fw_ver() argument
15982 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
15985 if (tg3_flag(tp, NO_NVRAM)) { in tg3_read_fw_ver()
15986 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
15987 tg3_read_otp_ver(tp); in tg3_read_fw_ver()
15991 if (tg3_nvram_read(tp, 0, &val)) in tg3_read_fw_ver()
15995 tg3_read_bc_ver(tp); in tg3_read_fw_ver()
15997 tg3_read_sb_ver(tp, val); in tg3_read_fw_ver()
15999 tg3_read_hwsb_ver(tp); in tg3_read_fw_ver()
16001 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_read_fw_ver()
16002 if (tg3_flag(tp, ENABLE_APE)) { in tg3_read_fw_ver()
16003 tg3_probe_ncsi(tp); in tg3_read_fw_ver()
16005 tg3_read_dash_ver(tp); in tg3_read_fw_ver()
16007 tg3_read_mgmtfw_ver(tp); in tg3_read_fw_ver()
16011 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
16014 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) in tg3_rx_ret_ring_size() argument
16016 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_rx_ret_ring_size()
16018 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) in tg3_rx_ret_ring_size()
16031 static struct pci_dev *tg3_find_peer(struct tg3 *tp) in tg3_find_peer() argument
16034 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16037 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16038 if (peer && peer != tp->pdev) in tg3_find_peer()
16046 peer = tp->pdev; in tg3_find_peer()
16059 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) in tg3_detect_asic_rev() argument
16061 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16062 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) { in tg3_detect_asic_rev()
16068 tg3_flag_set(tp, CPMU_PRESENT); in tg3_detect_asic_rev()
16070 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16071 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16072 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16073 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16074 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16075 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16076 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16077 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16078 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16079 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16080 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16082 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16083 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16084 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16085 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16086 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16087 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16088 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16089 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16090 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16091 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16096 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16102 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW) in tg3_detect_asic_rev()
16103 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16105 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0) in tg3_detect_asic_rev()
16106 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16108 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_detect_asic_rev()
16109 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_detect_asic_rev()
16110 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_detect_asic_rev()
16111 tg3_flag_set(tp, 5717_PLUS); in tg3_detect_asic_rev()
16113 if (tg3_asic_rev(tp) == ASIC_REV_57765 || in tg3_detect_asic_rev()
16114 tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_detect_asic_rev()
16115 tg3_flag_set(tp, 57765_CLASS); in tg3_detect_asic_rev()
16117 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) || in tg3_detect_asic_rev()
16118 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_detect_asic_rev()
16119 tg3_flag_set(tp, 57765_PLUS); in tg3_detect_asic_rev()
16122 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_detect_asic_rev()
16123 tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_detect_asic_rev()
16124 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_detect_asic_rev()
16125 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_detect_asic_rev()
16126 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_detect_asic_rev()
16127 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_detect_asic_rev()
16128 tg3_flag(tp, 57765_PLUS)) in tg3_detect_asic_rev()
16129 tg3_flag_set(tp, 5755_PLUS); in tg3_detect_asic_rev()
16131 if (tg3_asic_rev(tp) == ASIC_REV_5780 || in tg3_detect_asic_rev()
16132 tg3_asic_rev(tp) == ASIC_REV_5714) in tg3_detect_asic_rev()
16133 tg3_flag_set(tp, 5780_CLASS); in tg3_detect_asic_rev()
16135 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_detect_asic_rev()
16136 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_detect_asic_rev()
16137 tg3_asic_rev(tp) == ASIC_REV_5906 || in tg3_detect_asic_rev()
16138 tg3_flag(tp, 5755_PLUS) || in tg3_detect_asic_rev()
16139 tg3_flag(tp, 5780_CLASS)) in tg3_detect_asic_rev()
16140 tg3_flag_set(tp, 5750_PLUS); in tg3_detect_asic_rev()
16142 if (tg3_asic_rev(tp) == ASIC_REV_5705 || in tg3_detect_asic_rev()
16143 tg3_flag(tp, 5750_PLUS)) in tg3_detect_asic_rev()
16144 tg3_flag_set(tp, 5705_PLUS); in tg3_detect_asic_rev()
16147 static bool tg3_10_100_only_device(struct tg3 *tp, in tg3_10_100_only_device() argument
16152 if ((tg3_asic_rev(tp) == ASIC_REV_5703 && in tg3_10_100_only_device()
16154 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16158 if (tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_10_100_only_device()
16169 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) in tg3_get_invariants() argument
16184 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16186 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16193 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16195 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16197 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16198 tp->misc_host_ctrl); in tg3_get_invariants()
16200 tg3_detect_asic_rev(tp, misc_ctrl_reg); in tg3_get_invariants()
16219 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) || in tg3_get_invariants()
16220 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) { in tg3_get_invariants()
16252 tp->pdev->bus->number)) { in tg3_get_invariants()
16253 tg3_flag_set(tp, ICH_WORKAROUND); in tg3_get_invariants()
16260 if (tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_get_invariants()
16282 tp->pdev->bus->number) && in tg3_get_invariants()
16284 tp->pdev->bus->number)) { in tg3_get_invariants()
16285 tg3_flag_set(tp, 5701_DMA_BUG); in tg3_get_invariants()
16298 if (tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16299 tg3_flag_set(tp, 40BIT_DMA_BUG); in tg3_get_invariants()
16300 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16310 tp->pdev->bus->number) && in tg3_get_invariants()
16312 tp->pdev->bus->number)) { in tg3_get_invariants()
16313 tg3_flag_set(tp, 40BIT_DMA_BUG); in tg3_get_invariants()
16320 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_invariants()
16321 tg3_asic_rev(tp) == ASIC_REV_5714) in tg3_get_invariants()
16322 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16325 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0) in tg3_get_invariants()
16327 else if (tg3_flag(tp, 57765_PLUS)) in tg3_get_invariants()
16328 tg3_flag_set(tp, HW_TSO_3); in tg3_get_invariants()
16329 else if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16330 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16331 tg3_flag_set(tp, HW_TSO_2); in tg3_get_invariants()
16332 else if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
16333 tg3_flag_set(tp, HW_TSO_1); in tg3_get_invariants()
16334 tg3_flag_set(tp, TSO_BUG); in tg3_get_invariants()
16335 if (tg3_asic_rev(tp) == ASIC_REV_5750 && in tg3_get_invariants()
16336 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2) in tg3_get_invariants()
16337 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16338 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_get_invariants()
16339 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_get_invariants()
16340 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_get_invariants()
16341 tg3_flag_set(tp, FW_TSO); in tg3_get_invariants()
16342 tg3_flag_set(tp, TSO_BUG); in tg3_get_invariants()
16343 if (tg3_asic_rev(tp) == ASIC_REV_5705) in tg3_get_invariants()
16344 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16346 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16350 if (tg3_flag(tp, HW_TSO_1) || in tg3_get_invariants()
16351 tg3_flag(tp, HW_TSO_2) || in tg3_get_invariants()
16352 tg3_flag(tp, HW_TSO_3) || in tg3_get_invariants()
16353 tg3_flag(tp, FW_TSO)) { in tg3_get_invariants()
16358 tg3_flag_set(tp, TSO_CAPABLE); in tg3_get_invariants()
16360 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16361 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16362 tp->fw_needed = NULL; in tg3_get_invariants()
16365 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) in tg3_get_invariants()
16366 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16368 if (tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_get_invariants()
16369 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16371 tp->irq_max = 1; in tg3_get_invariants()
16373 if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
16374 tg3_flag_set(tp, SUPPORT_MSI); in tg3_get_invariants()
16375 if (tg3_chip_rev(tp) == CHIPREV_5750_AX || in tg3_get_invariants()
16376 tg3_chip_rev(tp) == CHIPREV_5750_BX || in tg3_get_invariants()
16377 (tg3_asic_rev(tp) == ASIC_REV_5714 && in tg3_get_invariants()
16378 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 && in tg3_get_invariants()
16379 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16380 tg3_flag_clear(tp, SUPPORT_MSI); in tg3_get_invariants()
16382 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16383 tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16384 tg3_flag_set(tp, 1SHOT_MSI); in tg3_get_invariants()
16387 if (tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
16388 tg3_flag_set(tp, SUPPORT_MSIX); in tg3_get_invariants()
16389 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16393 tp->txq_max = 1; in tg3_get_invariants()
16394 tp->rxq_max = 1; in tg3_get_invariants()
16395 if (tp->irq_max > 1) { in tg3_get_invariants()
16396 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16397 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS); in tg3_get_invariants()
16399 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16400 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_get_invariants()
16401 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16404 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16405 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16406 tg3_flag_set(tp, SHORT_DMA_BUG); in tg3_get_invariants()
16408 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_get_invariants()
16409 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16411 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16412 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16413 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_get_invariants()
16414 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16415 tg3_flag_set(tp, LRG_PROD_RING_CAP); in tg3_get_invariants()
16417 if (tg3_flag(tp, 57765_PLUS) && in tg3_get_invariants()
16418 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0) in tg3_get_invariants()
16419 tg3_flag_set(tp, USE_JUMBO_BDFLAG); in tg3_get_invariants()
16421 if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
16422 tg3_flag(tp, 5780_CLASS) || in tg3_get_invariants()
16423 tg3_flag(tp, USE_JUMBO_BDFLAG)) in tg3_get_invariants()
16424 tg3_flag_set(tp, JUMBO_CAPABLE); in tg3_get_invariants()
16426 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16429 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16432 tg3_flag_set(tp, PCI_EXPRESS); in tg3_get_invariants()
16434 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16436 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16437 tg3_flag_clear(tp, HW_TSO_2); in tg3_get_invariants()
16438 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16440 if (tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_get_invariants()
16441 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_get_invariants()
16442 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 || in tg3_get_invariants()
16443 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1) in tg3_get_invariants()
16444 tg3_flag_set(tp, CLKREQ_BUG); in tg3_get_invariants()
16445 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) { in tg3_get_invariants()
16446 tg3_flag_set(tp, L1PLLPD_EN); in tg3_get_invariants()
16448 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_get_invariants()
16453 tg3_flag_set(tp, PCI_EXPRESS); in tg3_get_invariants()
16454 } else if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
16455 tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16456 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16457 if (!tp->pcix_cap) { in tg3_get_invariants()
16458 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16464 tg3_flag_set(tp, PCIX_MODE); in tg3_get_invariants()
16474 !tg3_flag(tp, PCI_EXPRESS)) in tg3_get_invariants()
16475 tg3_flag_set(tp, MBOX_WRITE_REORDER); in tg3_get_invariants()
16477 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16478 &tp->pci_cacheline_sz); in tg3_get_invariants()
16479 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16480 &tp->pci_lat_timer); in tg3_get_invariants()
16481 if (tg3_asic_rev(tp) == ASIC_REV_5703 && in tg3_get_invariants()
16482 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16483 tp->pci_lat_timer = 64; in tg3_get_invariants()
16484 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16485 tp->pci_lat_timer); in tg3_get_invariants()
16491 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) { in tg3_get_invariants()
16495 tg3_flag_set(tp, TXD_MBOX_HWBUG); in tg3_get_invariants()
16502 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16505 tg3_flag_set(tp, PCIX_TARGET_HWBUG); in tg3_get_invariants()
16511 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16512 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16516 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16517 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16521 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16523 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16528 tg3_flag_set(tp, PCI_HIGH_SPEED); in tg3_get_invariants()
16530 tg3_flag_set(tp, PCI_32BIT); in tg3_get_invariants()
16533 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) && in tg3_get_invariants()
16536 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16540 tp->read32 = tg3_read32; in tg3_get_invariants()
16541 tp->write32 = tg3_write32; in tg3_get_invariants()
16542 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16543 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16544 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16545 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16548 if (tg3_flag(tp, PCIX_TARGET_HWBUG)) in tg3_get_invariants()
16549 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16550 else if (tg3_asic_rev(tp) == ASIC_REV_5701 || in tg3_get_invariants()
16551 (tg3_flag(tp, PCI_EXPRESS) && in tg3_get_invariants()
16552 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) { in tg3_get_invariants()
16560 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16563 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { in tg3_get_invariants()
16564 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16565 if (tg3_flag(tp, MBOX_WRITE_REORDER)) in tg3_get_invariants()
16566 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16569 if (tg3_flag(tp, ICH_WORKAROUND)) { in tg3_get_invariants()
16570 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16571 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16572 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16573 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16574 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16575 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16577 iounmap(tp->regs); in tg3_get_invariants()
16578 tp->regs = NULL; in tg3_get_invariants()
16580 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16582 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16584 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16585 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16586 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16587 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16588 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16591 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16592 (tg3_flag(tp, PCIX_MODE) && in tg3_get_invariants()
16593 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16594 tg3_asic_rev(tp) == ASIC_REV_5701))) in tg3_get_invariants()
16595 tg3_flag_set(tp, SRAM_USE_CONFIG); in tg3_get_invariants()
16605 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16606 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_invariants()
16607 tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16608 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16609 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16610 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16612 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16614 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16615 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16616 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_get_invariants()
16617 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); in tg3_get_invariants()
16621 if (tg3_asic_rev(tp) == ASIC_REV_5717) in tg3_get_invariants()
16622 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16624 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16628 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { in tg3_get_invariants()
16629 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16630 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16641 tg3_get_eeprom_hw_cfg(tp); in tg3_get_invariants()
16643 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) { in tg3_get_invariants()
16644 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16645 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16646 tp->fw_needed = NULL; in tg3_get_invariants()
16649 if (tg3_flag(tp, ENABLE_APE)) { in tg3_get_invariants()
16656 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16659 tg3_ape_lock_init(tp); in tg3_get_invariants()
16660 tp->ape_hb_interval = in tg3_get_invariants()
16669 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16670 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16671 tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_get_invariants()
16672 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16677 else if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_get_invariants()
16678 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16680 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_get_invariants()
16681 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_get_invariants()
16682 tg3_flag(tp, 57765_CLASS)) in tg3_get_invariants()
16683 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16685 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16686 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16688 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16689 if (tg3_flag(tp, IS_NIC)) in tg3_get_invariants()
16691 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16695 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16696 tp->grc_local_ctrl |= in tg3_get_invariants()
16700 tg3_pwrsrc_switch_to_vmain(tp); in tg3_get_invariants()
16705 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16706 tg3_flag_set(tp, JUMBO_RING_ENABLE); in tg3_get_invariants()
16709 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16710 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
16711 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || in tg3_get_invariants()
16712 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) { in tg3_get_invariants()
16713 tg3_flag_clear(tp, WOL_SPEED_100MB); in tg3_get_invariants()
16715 tg3_flag_set(tp, WOL_SPEED_100MB); in tg3_get_invariants()
16718 if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16719 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16722 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16723 (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_get_invariants()
16724 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) && in tg3_get_invariants()
16725 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) || in tg3_get_invariants()
16726 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16727 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16728 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16730 if (tg3_chip_rev(tp) == CHIPREV_5703_AX || in tg3_get_invariants()
16731 tg3_chip_rev(tp) == CHIPREV_5704_AX) in tg3_get_invariants()
16732 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16733 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) in tg3_get_invariants()
16734 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16736 if (tg3_flag(tp, 5705_PLUS) && in tg3_get_invariants()
16737 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16738 tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_get_invariants()
16739 tg3_asic_rev(tp) != ASIC_REV_57780 && in tg3_get_invariants()
16740 !tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
16741 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_get_invariants()
16742 tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_get_invariants()
16743 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_get_invariants()
16744 tg3_asic_rev(tp) == ASIC_REV_5761) { in tg3_get_invariants()
16745 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16746 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16747 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16748 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16749 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16751 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16754 if (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_get_invariants()
16755 tg3_chip_rev(tp) != CHIPREV_5784_AX) { in tg3_get_invariants()
16756 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16757 if (tp->phy_otp == 0) in tg3_get_invariants()
16758 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16761 if (tg3_flag(tp, CPMU_PRESENT)) in tg3_get_invariants()
16762 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16764 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16766 tp->coalesce_mode = 0; in tg3_get_invariants()
16767 if (tg3_chip_rev(tp) != CHIPREV_5700_AX && in tg3_get_invariants()
16768 tg3_chip_rev(tp) != CHIPREV_5700_BX) in tg3_get_invariants()
16769 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16772 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16773 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_get_invariants()
16774 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_get_invariants()
16775 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) { in tg3_get_invariants()
16776 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16777 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16780 if (tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_get_invariants()
16781 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_get_invariants()
16782 tg3_flag_set(tp, USE_PHYLIB); in tg3_get_invariants()
16784 err = tg3_mdio_init(tp); in tg3_get_invariants()
16790 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_get_invariants()
16791 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16800 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16802 tg3_switch_clocks(tp); in tg3_get_invariants()
16810 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16813 !tg3_flag(tp, PCIX_TARGET_HWBUG)) { in tg3_get_invariants()
16814 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
16815 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || in tg3_get_invariants()
16816 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 || in tg3_get_invariants()
16817 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) { in tg3_get_invariants()
16824 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16830 tg3_flag_set(tp, PCIX_TARGET_HWBUG); in tg3_get_invariants()
16835 tg3_nvram_init(tp); in tg3_get_invariants()
16838 if (tg3_asic_rev(tp) == ASIC_REV_57766 && in tg3_get_invariants()
16839 !tg3_flag(tp, NO_NVRAM)) in tg3_get_invariants()
16840 tp->fw_needed = NULL; in tg3_get_invariants()
16845 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_get_invariants()
16848 tg3_flag_set(tp, IS_5788); in tg3_get_invariants()
16850 if (!tg3_flag(tp, IS_5788) && in tg3_get_invariants()
16851 tg3_asic_rev(tp) != ASIC_REV_5700) in tg3_get_invariants()
16852 tg3_flag_set(tp, TAGGED_STATUS); in tg3_get_invariants()
16853 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_get_invariants()
16854 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16857 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16858 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16859 tp->misc_host_ctrl); in tg3_get_invariants()
16863 if (tg3_flag(tp, ENABLE_APE)) in tg3_get_invariants()
16864 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16866 tp->mac_mode = 0; in tg3_get_invariants()
16868 if (tg3_10_100_only_device(tp, ent)) in tg3_get_invariants()
16869 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16871 err = tg3_phy_probe(tp); in tg3_get_invariants()
16873 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16875 tg3_mdio_fini(tp); in tg3_get_invariants()
16878 tg3_read_vpd(tp); in tg3_get_invariants()
16879 tg3_read_fw_ver(tp); in tg3_get_invariants()
16881 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16882 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16884 if (tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_get_invariants()
16885 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16887 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16894 if (tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_get_invariants()
16895 tg3_flag_set(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16897 tg3_flag_clear(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16903 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
16904 tg3_asic_rev(tp) == ASIC_REV_5701 && in tg3_get_invariants()
16905 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
16906 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16907 tg3_flag_set(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16911 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
16912 tg3_flag_set(tp, POLL_SERDES); in tg3_get_invariants()
16914 tg3_flag_clear(tp, POLL_SERDES); in tg3_get_invariants()
16916 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF)) in tg3_get_invariants()
16917 tg3_flag_set(tp, POLL_CPMU_LINK); in tg3_get_invariants()
16919 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
16920 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
16921 if (tg3_asic_rev(tp) == ASIC_REV_5701 && in tg3_get_invariants()
16922 tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16923 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
16925 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
16929 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
16930 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
16931 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
16933 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
16938 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_get_invariants()
16939 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_get_invariants()
16940 tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_get_invariants()
16941 tp->rx_std_max_post = 8; in tg3_get_invariants()
16943 if (tg3_flag(tp, ASPM_WORKAROUND)) in tg3_get_invariants()
16944 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
16950 static int tg3_get_device_address(struct tg3 *tp, u8 *addr) in tg3_get_device_address() argument
16956 if (!eth_platform_get_mac_address(&tp->pdev->dev, addr)) in tg3_get_device_address()
16959 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_get_device_address()
16960 err = ssb_gige_get_macaddr(tp->pdev, addr); in tg3_get_device_address()
16966 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_device_address()
16967 tg3_flag(tp, 5780_CLASS)) { in tg3_get_device_address()
16970 if (tg3_nvram_lock(tp)) in tg3_get_device_address()
16973 tg3_nvram_unlock(tp); in tg3_get_device_address()
16974 } else if (tg3_flag(tp, 5717_PLUS)) { in tg3_get_device_address()
16975 if (tp->pci_fn & 1) in tg3_get_device_address()
16977 if (tp->pci_fn > 1) in tg3_get_device_address()
16979 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_device_address()
16983 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); in tg3_get_device_address()
16988 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); in tg3_get_device_address()
16999 if (!tg3_flag(tp, NO_NVRAM) && in tg3_get_device_address()
17000 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && in tg3_get_device_address()
17001 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { in tg3_get_device_address()
17027 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val) in tg3_calc_dma_bndry() argument
17033 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17042 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_calc_dma_bndry()
17043 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_calc_dma_bndry()
17044 !tg3_flag(tp, PCI_EXPRESS)) in tg3_calc_dma_bndry()
17057 if (tg3_flag(tp, 57765_PLUS)) { in tg3_calc_dma_bndry()
17076 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
17101 } else if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
17168 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, in tg3_do_test_dma() argument
17219 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17221 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17223 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17256 static int tg3_test_dma(struct tg3 *tp) in tg3_test_dma() argument
17262 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17269 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17272 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17274 if (tg3_flag(tp, 57765_PLUS)) in tg3_test_dma()
17277 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_test_dma()
17279 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17280 } else if (!tg3_flag(tp, PCIX_MODE)) { in tg3_test_dma()
17281 if (tg3_asic_rev(tp) == ASIC_REV_5705 || in tg3_test_dma()
17282 tg3_asic_rev(tp) == ASIC_REV_5750) in tg3_test_dma()
17283 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17285 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17287 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_test_dma()
17288 tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_test_dma()
17296 if (tg3_flag(tp, 40BIT_DMA_BUG) && in tg3_test_dma()
17297 tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_test_dma()
17298 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17300 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17302 if (tg3_asic_rev(tp) == ASIC_REV_5703) in tg3_test_dma()
17305 tp->dma_rwctrl |= in tg3_test_dma()
17309 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) { in tg3_test_dma()
17311 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17312 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_test_dma()
17314 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17316 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17319 if (tg3_flag(tp, ONE_DMA_AT_ONCE)) in tg3_test_dma()
17320 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17322 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_test_dma()
17323 tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_test_dma()
17324 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17326 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_test_dma()
17327 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_test_dma()
17329 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17341 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17344 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17347 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_test_dma()
17348 tg3_asic_rev(tp) != ASIC_REV_5701) in tg3_test_dma()
17354 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17355 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17356 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17365 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true); in tg3_test_dma()
17367 dev_err(&tp->pdev->dev, in tg3_test_dma()
17374 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false); in tg3_test_dma()
17376 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17386 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17388 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17389 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17390 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17393 dev_err(&tp->pdev->dev, in tg3_test_dma()
17407 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17414 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17415 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17418 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17421 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17425 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17430 static void tg3_init_bufmgr_config(struct tg3 *tp) in tg3_init_bufmgr_config() argument
17432 if (tg3_flag(tp, 57765_PLUS)) { in tg3_init_bufmgr_config()
17433 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17435 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17437 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17440 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17442 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17444 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17446 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_bufmgr_config()
17447 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17449 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17451 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17453 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_init_bufmgr_config()
17454 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17456 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17460 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17462 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17464 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17467 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17469 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17471 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17474 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17476 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17478 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17482 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17483 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17486 static char *tg3_phy_string(struct tg3 *tp) in tg3_phy_string() argument
17488 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17518 static char *tg3_bus_string(struct tg3 *tp, char *str) in tg3_bus_string() argument
17520 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_bus_string()
17523 } else if (tg3_flag(tp, PCIX_MODE)) { in tg3_bus_string()
17542 if (tg3_flag(tp, PCI_HIGH_SPEED)) in tg3_bus_string()
17547 if (tg3_flag(tp, PCI_32BIT)) in tg3_bus_string()
17554 static void tg3_init_coal(struct tg3 *tp) in tg3_init_coal() argument
17556 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17570 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17578 if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_coal()
17589 struct tg3 *tp; in tg3_init_one() local
17611 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); in tg3_init_one()
17619 tp = netdev_priv(dev); in tg3_init_one()
17620 tp->pdev = pdev; in tg3_init_one()
17621 tp->dev = dev; in tg3_init_one()
17622 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17623 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17624 tp->irq_sync = 1; in tg3_init_one()
17625 tp->pcierr_recovery = false; in tg3_init_one()
17628 tp->msg_enable = tg3_debug; in tg3_init_one()
17630 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17633 tg3_flag_set(tp, IS_SSB_CORE); in tg3_init_one()
17635 tg3_flag_set(tp, FLUSH_POSTED_WRITES); in tg3_init_one()
17637 tg3_flag_set(tp, ONE_DMA_AT_ONCE); in tg3_init_one()
17639 tg3_flag_set(tp, USE_PHYLIB); in tg3_init_one()
17640 tg3_flag_set(tp, ROBOSWITCH); in tg3_init_one()
17643 tg3_flag_set(tp, RGMII_MODE); in tg3_init_one()
17650 tp->misc_host_ctrl = in tg3_init_one()
17662 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17665 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17667 spin_lock_init(&tp->lock); in tg3_init_one()
17668 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17669 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17671 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17672 if (!tp->regs) { in tg3_init_one()
17678 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17679 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17680 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17681 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17682 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17683 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17684 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17685 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17686 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17687 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17688 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17689 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17690 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17691 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17692 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17693 tg3_flag_set(tp, ENABLE_APE); in tg3_init_one()
17694 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17695 if (!tp->aperegs) { in tg3_init_one()
17703 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17704 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17711 err = tg3_get_invariants(tp, ent); in tg3_init_one()
17724 if (tg3_flag(tp, IS_5788)) in tg3_init_one()
17726 else if (tg3_flag(tp, 40BIT_DMA_BUG)) { in tg3_init_one()
17757 tg3_init_bufmgr_config(tp); in tg3_init_one()
17762 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) { in tg3_init_one()
17765 if (tg3_flag(tp, 5755_PLUS)) in tg3_init_one()
17773 if ((tg3_flag(tp, HW_TSO_1) || in tg3_init_one()
17774 tg3_flag(tp, HW_TSO_2) || in tg3_init_one()
17775 tg3_flag(tp, HW_TSO_3)) && in tg3_init_one()
17778 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { in tg3_init_one()
17781 if (tg3_flag(tp, HW_TSO_3) || in tg3_init_one()
17782 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_init_one()
17783 (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_init_one()
17784 tg3_chip_rev(tp) != CHIPREV_5784_AX) || in tg3_init_one()
17785 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_init_one()
17786 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_init_one()
17799 if (tg3_asic_rev(tp) != ASIC_REV_5780 && in tg3_init_one()
17800 !tg3_flag(tp, CPMU_PRESENT)) in tg3_init_one()
17809 dev->max_mtu = TG3_MAX_MTU(tp); in tg3_init_one()
17811 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 && in tg3_init_one()
17812 !tg3_flag(tp, TSO_CAPABLE) && in tg3_init_one()
17814 tg3_flag_set(tp, MAX_RXPEND_64); in tg3_init_one()
17815 tp->rx_pending = 63; in tg3_init_one()
17818 err = tg3_get_device_address(tp, addr); in tg3_init_one()
17829 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17830 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17832 tnapi->tp = tp; in tg3_init_one()
17846 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_init_one()
17874 tg3_full_lock(tp, 0); in tg3_init_one()
17876 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_init_one()
17877 tg3_full_unlock(tp); in tg3_init_one()
17880 err = tg3_test_dma(tp); in tg3_init_one()
17886 tg3_init_coal(tp); in tg3_init_one()
17890 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_init_one()
17891 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_init_one()
17892 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_init_one()
17893 tg3_flag_set(tp, PTP_CAPABLE); in tg3_init_one()
17895 tg3_timer_init(tp); in tg3_init_one()
17897 tg3_carrier_off(tp); in tg3_init_one()
17905 if (tg3_flag(tp, PTP_CAPABLE)) { in tg3_init_one()
17906 tg3_ptp_init(tp); in tg3_init_one()
17907 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
17908 &tp->pdev->dev); in tg3_init_one()
17909 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
17910 tp->ptp_clock = NULL; in tg3_init_one()
17914 tp->board_part_number, in tg3_init_one()
17915 tg3_chip_rev_id(tp), in tg3_init_one()
17916 tg3_bus_string(tp, str), in tg3_init_one()
17919 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { in tg3_init_one()
17922 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
17924 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
17931 tg3_phy_string(tp), ethtype, in tg3_init_one()
17932 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
17933 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
17938 tg3_flag(tp, USE_LINKCHG_REG) != 0, in tg3_init_one()
17939 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
17940 tg3_flag(tp, ENABLE_ASF) != 0, in tg3_init_one()
17941 tg3_flag(tp, TSO_CAPABLE) != 0); in tg3_init_one()
17943 tp->dma_rwctrl, in tg3_init_one()
17952 if (tp->aperegs) { in tg3_init_one()
17953 iounmap(tp->aperegs); in tg3_init_one()
17954 tp->aperegs = NULL; in tg3_init_one()
17958 if (tp->regs) { in tg3_init_one()
17959 iounmap(tp->regs); in tg3_init_one()
17960 tp->regs = NULL; in tg3_init_one()
17980 struct tg3 *tp = netdev_priv(dev); in tg3_remove_one() local
17982 tg3_ptp_fini(tp); in tg3_remove_one()
17984 release_firmware(tp->fw); in tg3_remove_one()
17986 tg3_reset_task_cancel(tp); in tg3_remove_one()
17988 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_remove_one()
17989 tg3_phy_fini(tp); in tg3_remove_one()
17990 tg3_mdio_fini(tp); in tg3_remove_one()
17994 if (tp->aperegs) { in tg3_remove_one()
17995 iounmap(tp->aperegs); in tg3_remove_one()
17996 tp->aperegs = NULL; in tg3_remove_one()
17998 if (tp->regs) { in tg3_remove_one()
17999 iounmap(tp->regs); in tg3_remove_one()
18000 tp->regs = NULL; in tg3_remove_one()
18012 struct tg3 *tp = netdev_priv(dev); in tg3_suspend() local
18020 tg3_reset_task_cancel(tp); in tg3_suspend()
18021 tg3_phy_stop(tp); in tg3_suspend()
18022 tg3_netif_stop(tp); in tg3_suspend()
18024 tg3_timer_stop(tp); in tg3_suspend()
18026 tg3_full_lock(tp, 1); in tg3_suspend()
18027 tg3_disable_ints(tp); in tg3_suspend()
18028 tg3_full_unlock(tp); in tg3_suspend()
18032 tg3_full_lock(tp, 0); in tg3_suspend()
18033 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_suspend()
18034 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_suspend()
18035 tg3_full_unlock(tp); in tg3_suspend()
18037 err = tg3_power_down_prepare(tp); in tg3_suspend()
18041 tg3_full_lock(tp, 0); in tg3_suspend()
18043 tg3_flag_set(tp, INIT_COMPLETE); in tg3_suspend()
18044 err2 = tg3_restart_hw(tp, true); in tg3_suspend()
18048 tg3_timer_start(tp); in tg3_suspend()
18051 tg3_netif_start(tp); in tg3_suspend()
18054 tg3_full_unlock(tp); in tg3_suspend()
18057 tg3_phy_start(tp); in tg3_suspend()
18068 struct tg3 *tp = netdev_priv(dev); in tg3_resume() local
18078 tg3_full_lock(tp, 0); in tg3_resume()
18080 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_resume()
18082 tg3_flag_set(tp, INIT_COMPLETE); in tg3_resume()
18083 err = tg3_restart_hw(tp, in tg3_resume()
18084 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18088 tg3_timer_start(tp); in tg3_resume()
18090 tg3_netif_start(tp); in tg3_resume()
18093 tg3_full_unlock(tp); in tg3_resume()
18096 tg3_phy_start(tp); in tg3_resume()
18109 struct tg3 *tp = netdev_priv(dev); in tg3_shutdown() local
18111 tg3_reset_task_cancel(tp); in tg3_shutdown()
18121 tg3_power_down(tp); in tg3_shutdown()
18140 struct tg3 *tp = netdev_priv(netdev); in tg3_io_error_detected() local
18146 tg3_reset_task_cancel(tp); in tg3_io_error_detected()
18151 if (!netdev || tp->pcierr_recovery || !netif_running(netdev)) in tg3_io_error_detected()
18156 tp->pcierr_recovery = true; in tg3_io_error_detected()
18158 tg3_phy_stop(tp); in tg3_io_error_detected()
18160 tg3_netif_stop(tp); in tg3_io_error_detected()
18162 tg3_timer_stop(tp); in tg3_io_error_detected()
18167 tg3_full_lock(tp, 0); in tg3_io_error_detected()
18168 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_io_error_detected()
18169 tg3_full_unlock(tp); in tg3_io_error_detected()
18174 tg3_napi_enable(tp); in tg3_io_error_detected()
18199 struct tg3 *tp = netdev_priv(netdev); in tg3_io_slot_reset() local
18220 err = tg3_power_up(tp); in tg3_io_slot_reset()
18228 tg3_napi_enable(tp); in tg3_io_slot_reset()
18246 struct tg3 *tp = netdev_priv(netdev); in tg3_io_resume() local
18254 tg3_full_lock(tp, 0); in tg3_io_resume()
18255 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_io_resume()
18256 tg3_flag_set(tp, INIT_COMPLETE); in tg3_io_resume()
18257 err = tg3_restart_hw(tp, true); in tg3_io_resume()
18259 tg3_full_unlock(tp); in tg3_io_resume()
18266 tg3_timer_start(tp); in tg3_io_resume()
18268 tg3_netif_start(tp); in tg3_io_resume()
18270 tg3_full_unlock(tp); in tg3_io_resume()
18272 tg3_phy_start(tp); in tg3_io_resume()
18275 tp->pcierr_recovery = false; in tg3_io_resume()