Lines Matching refs:tg3_writephy
1230 static int tg3_writephy(struct tg3 *tp, int reg, u32 val) in tg3_writephy() function
1239 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_write()
1243 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_write()
1247 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_write()
1252 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_write()
1262 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_read()
1266 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_read()
1270 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_read()
1285 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_read()
1296 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_write()
1298 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write()
1307 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, in tg3_phy_auxctl_read()
1321 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); in tg3_phy_auxctl_write()
1347 return tg3_writephy(tp, MII_TG3_MISC_SHDW, in tg3_phy_shdw_write()
1360 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
2205 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_fet_toggle_apd()
2212 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); in tg3_phy_fet_toggle_apd()
2214 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_phy_fet_toggle_apd()
2263 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_toggle_automdix()
2270 tg3_writephy(tp, reg, phy); in tg3_phy_toggle_automdix()
2272 tg3_writephy(tp, MII_TG3_FET_TEST, ephy); in tg3_phy_toggle_automdix()
2471 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2473 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2476 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
2479 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2485 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2487 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2493 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2512 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); in tg3_phy_write_and_check_testpat()
2513 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
2514 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
2531 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_reset_chanpat()
2533 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2535 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
2536 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2564 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2567 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
2574 tg3_writephy(tp, MII_CTRL1000, in tg3_phy_reset_5703_4_5()
2595 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); in tg3_phy_reset_5703_4_5()
2596 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
2600 tg3_writephy(tp, MII_CTRL1000, phy9_orig); in tg3_phy_reset_5703_4_5()
2607 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2708 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2709 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2721 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); in tg3_phy_reset()
2723 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset()
2724 tg3_writephy(tp, MII_TG3_TEST1, in tg3_phy_reset()
2727 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); in tg3_phy_reset()
2752 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_reset()
2758 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); in tg3_phy_reset()
3086 tg3_writephy(tp, MII_ADVERTISE, 0); in tg3_power_down_phy()
3087 tg3_writephy(tp, MII_BMCR, in tg3_power_down_phy()
3090 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_power_down_phy()
3094 tg3_writephy(tp, in tg3_power_down_phy()
3098 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_power_down_phy()
3103 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_power_down_phy()
3126 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); in tg3_power_down_phy()
4331 err = tg3_writephy(tp, MII_ADVERTISE, new_adv); in tg3_phy_autoneg_cfg()
4342 err = tg3_writephy(tp, MII_CTRL1000, new_adv); in tg3_phy_autoneg_cfg()
4447 tg3_writephy(tp, MII_BMCR, in tg3_phy_copper_begin()
4461 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL); in tg3_phy_copper_begin()
4484 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); in tg3_phy_copper_begin()
4497 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_copper_begin()
4843 tg3_writephy(tp, 0x15, 0x0a75); in tg3_setup_copper_phy()
4844 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4845 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_setup_copper_phy()
4846 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4854 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); in tg3_setup_copper_phy()
4856 tg3_writephy(tp, MII_TG3_IMASK, ~0); in tg3_setup_copper_phy()
4861 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_setup_copper_phy()
4864 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); in tg3_setup_copper_phy()
5459 tg3_writephy(tp, 0x16, 0x8007); in tg3_init_bcm8002()
5462 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_init_bcm8002()
5470 tg3_writephy(tp, 0x10, 0x8411); in tg3_init_bcm8002()
5473 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5475 tg3_writephy(tp, 0x18, 0x00a0); in tg3_init_bcm8002()
5476 tg3_writephy(tp, 0x16, 0x41ff); in tg3_init_bcm8002()
5479 tg3_writephy(tp, 0x13, 0x0400); in tg3_init_bcm8002()
5481 tg3_writephy(tp, 0x13, 0x0000); in tg3_init_bcm8002()
5483 tg3_writephy(tp, 0x11, 0x0a50); in tg3_init_bcm8002()
5485 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5495 tg3_writephy(tp, 0x10, 0x8011); in tg3_init_bcm8002()
5895 tg3_writephy(tp, MII_ADVERTISE, newadv); in tg3_setup_fiber_mii_phy()
5897 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_setup_fiber_mii_phy()
5928 tg3_writephy(tp, MII_ADVERTISE, adv); in tg3_setup_fiber_mii_phy()
5929 tg3_writephy(tp, MII_BMCR, bmcr | in tg3_setup_fiber_mii_phy()
5935 tg3_writephy(tp, MII_BMCR, new_bmcr); in tg3_setup_fiber_mii_phy()
6020 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); in tg3_serdes_parallel_detect()
6024 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6037 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_serdes_parallel_detect()
6047 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6055 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); in tg3_serdes_parallel_detect()
8224 tg3_writephy(tp, MII_CTRL1000, val); in tg3_phy_lpbk_set()
8228 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); in tg3_phy_lpbk_set()
8233 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_lpbk_set()
8243 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | in tg3_phy_lpbk_set()
8274 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_lpbk_set()
10701 tg3_writephy(tp, MII_TG3_TEST1, in tg3_reset_hw()
11810 tg3_writephy(tp, MII_TG3_TEST1, in tg3_calc_crc_errors()
12418 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | in tg3_nway_reset()
15610 tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()