1293 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)  in tg3_phydsp_write()  function
2319 	tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);  in tg3_phy_apply_otp()
2323 	tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);  in tg3_phy_apply_otp()
2327 	tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);  in tg3_phy_apply_otp()
2330 	tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);  in tg3_phy_apply_otp()
2333 	tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);  in tg3_phy_apply_otp()
2337 	tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);  in tg3_phy_apply_otp()
2413 			tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000);  in tg3_phy_eee_adjust()
2433 		tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);  in tg3_phy_eee_enable()
2583 		tg3_phydsp_write(tp, 0x8005, 0x0800);  in tg3_phy_reset_5703_4_5()
2594 	tg3_phydsp_write(tp, 0x8005, 0x0000);  in tg3_phy_reset_5703_4_5()
2673 		tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);  in tg3_phy_reset()
2703 		tg3_phydsp_write(tp, 0x201f, 0x2aaa);  in tg3_phy_reset()
2704 		tg3_phydsp_write(tp, 0x000a, 0x0323);  in tg3_phy_reset()
2715 			tg3_phydsp_write(tp, 0x000a, 0x310b);  in tg3_phy_reset()
2716 			tg3_phydsp_write(tp, 0x201f, 0x9506);  in tg3_phy_reset()
2717 			tg3_phydsp_write(tp, 0x401f, 0x14e2);  in tg3_phy_reset()
2763 		tg3_phydsp_write(tp, 0xffb, 0x4000);  in tg3_phy_reset()
4389 			tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val);  in tg3_phy_autoneg_cfg()
4394 				tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val |  in tg3_phy_autoneg_cfg()
4609 	err |= tg3_phydsp_write(tp, 0x0012, 0x1804);  in tg3_init_5401phy_dsp()
4610 	err |= tg3_phydsp_write(tp, 0x0013, 0x1204);  in tg3_init_5401phy_dsp()
4611 	err |= tg3_phydsp_write(tp, 0x8006, 0x0132);  in tg3_init_5401phy_dsp()
4612 	err |= tg3_phydsp_write(tp, 0x8006, 0x0232);  in tg3_init_5401phy_dsp()
4613 	err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);  in tg3_init_5401phy_dsp()