14378 	u32 nvcfg1;  in tg3_get_nvram_info()  local
14380 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_nvram_info()
14381 	if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {  in tg3_get_nvram_info()
14384 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_nvram_info()
14385 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_nvram_info()
14390 		switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {  in tg3_get_nvram_info()
14456 	u32 nvcfg1;  in tg3_get_5752_nvram_info()  local
14458 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5752_nvram_info()
14461 	if (nvcfg1 & (1 << 27))  in tg3_get_5752_nvram_info()
14464 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5752_nvram_info()
14485 		tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5752_nvram_info()
14490 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_5752_nvram_info()
14491 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_5752_nvram_info()
14497 	u32 nvcfg1, protect = 0;  in tg3_get_5755_nvram_info()  local
14499 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5755_nvram_info()
14502 	if (nvcfg1 & (1 << 27)) {  in tg3_get_5755_nvram_info()
14507 	nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;  in tg3_get_5755_nvram_info()
14508 	switch (nvcfg1) {  in tg3_get_5755_nvram_info()
14517 		if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||  in tg3_get_5755_nvram_info()
14518 		    nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)  in tg3_get_5755_nvram_info()
14521 		else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)  in tg3_get_5755_nvram_info()
14535 		if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)  in tg3_get_5755_nvram_info()
14539 		else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)  in tg3_get_5755_nvram_info()
14553 	u32 nvcfg1;  in tg3_get_5787_nvram_info()  local
14555 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5787_nvram_info()
14557 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5787_nvram_info()
14566 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_5787_nvram_info()
14567 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_5787_nvram_info()
14591 	u32 nvcfg1, protect = 0;  in tg3_get_5761_nvram_info()  local
14593 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5761_nvram_info()
14596 	if (nvcfg1 & (1 << 27)) {  in tg3_get_5761_nvram_info()
14601 	nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;  in tg3_get_5761_nvram_info()
14602 	switch (nvcfg1) {  in tg3_get_5761_nvram_info()
14635 		switch (nvcfg1) {  in tg3_get_5761_nvram_info()
14673 	u32 nvcfg1;  in tg3_get_57780_nvram_info()  local
14675 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_57780_nvram_info()
14677 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_57780_nvram_info()
14684 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_57780_nvram_info()
14685 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_57780_nvram_info()
14698 		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_57780_nvram_info()
14721 		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_57780_nvram_info()
14738 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_57780_nvram_info()
14746 	u32 nvcfg1;  in tg3_get_5717_nvram_info()  local
14748 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5717_nvram_info()
14750 	switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5717_nvram_info()
14757 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_5717_nvram_info()
14758 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_5717_nvram_info()
14771 		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5717_nvram_info()
14798 		switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {  in tg3_get_5717_nvram_info()
14817 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5717_nvram_info()
14824 	u32 nvcfg1, nvmpinstrp, nv_status;  in tg3_get_5720_nvram_info()  local
14826 	nvcfg1 = tr32(NVRAM_CFG1);  in tg3_get_5720_nvram_info()
14827 	nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;  in tg3_get_5720_nvram_info()
14830 		if (!(nvcfg1 & NVRAM_CFG1_5762VENDOR_MASK)) {  in tg3_get_5720_nvram_info()
14874 		nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;  in tg3_get_5720_nvram_info()
14875 		tw32(NVRAM_CFG1, nvcfg1);  in tg3_get_5720_nvram_info()
14970 	tg3_nvram_get_pagesize(tp, nvcfg1);  in tg3_get_5720_nvram_info()