13089 #define TG3_FL_NOT_5705	0x2  in tg3_test_registers()  macro
13096 		{ MAC_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13100 		{ MAC_STATUS, TG3_FL_NOT_5705,  in tg3_test_registers()
13114 		{ MAC_RX_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13128 		{ RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,  in tg3_test_registers()
13130 		{ RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13132 		{ RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,  in tg3_test_registers()
13134 		{ RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,  in tg3_test_registers()
13146 		{ RCVBDI_STD_THRESH, TG3_FL_NOT_5705,  in tg3_test_registers()
13150 		{ RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,  in tg3_test_registers()
13154 		{ HOSTCC_MODE, TG3_FL_NOT_5705,  in tg3_test_registers()
13158 		{ HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13162 		{ HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13166 		{ HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,  in tg3_test_registers()
13170 		{ HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,  in tg3_test_registers()
13174 		{ HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13176 		{ HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13178 		{ HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13182 		{ HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,  in tg3_test_registers()
13186 		{ HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,  in tg3_test_registers()
13188 		{ HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,  in tg3_test_registers()
13190 		{ HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13212 		{ BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,  in tg3_test_registers()
13214 		{ BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,  in tg3_test_registers()
13220 		{ GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,  in tg3_test_registers()
13238 		if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))  in tg3_test_registers()