Lines Matching +full:pull +full:- +full:up +full:- +full:adv
7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
93 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
95 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
97 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
123 * and dev->tx_timeout() should be called to fix the problem
146 /* Do not place this n-ring entries value into the tp struct itself,
150 * replace things like '% foo' with '& (foo - 1)'.
154 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
161 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
164 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
197 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
201 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
206 /* minimum number of free TX descriptors required to wake up TX process */
207 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
232 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
354 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
472 writel(val, tp->regs + off); in tg3_write32()
477 return readl(tp->regs + off); in tg3_read32()
482 writel(val, tp->aperegs + off); in tg3_ape_write32()
487 return readl(tp->aperegs + off); in tg3_ape_read32()
494 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
495 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
497 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
502 writel(val, tp->regs + off); in tg3_write_flush_reg32()
503 readl(tp->regs + off); in tg3_write_flush_reg32()
511 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
512 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
513 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
514 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
523 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
528 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
533 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
534 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
536 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
543 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
544 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
553 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
554 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
555 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
556 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
568 /* Non-posted methods */ in _tw32_flush()
569 tp->write32(tp, off, val); in _tw32_flush()
575 tp->read32(tp, off); in _tw32_flush()
586 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
590 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
595 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
606 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
611 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
614 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
616 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
617 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
618 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
620 #define tw32(reg, val) tp->write32(tp, reg, val)
623 #define tr32(reg) tp->read32(tp, reg)
633 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
635 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
639 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
647 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
660 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
662 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
663 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
666 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
674 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
697 if (!tp->pci_fn) in tg3_ape_lock_init()
700 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
723 if (!tp->pci_fn) in tg3_ape_lock()
726 bit = 1 << tp->pci_fn; in tg3_ape_lock()
735 return -EINVAL; in tg3_ape_lock()
750 /* Wait for up to 1 millisecond to acquire lock. */ in tg3_ape_lock()
755 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
764 ret = -EBUSY; in tg3_ape_lock()
784 if (!tp->pci_fn) in tg3_ape_unlock()
787 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
813 return -EBUSY; in tg3_ape_event_lock()
822 timeout_us -= (timeout_us > 10) ? 10 : timeout_us; in tg3_ape_event_lock()
825 return timeout_us ? 0 : -EBUSY; in tg3_ape_event_lock()
856 return -ENODEV; in tg3_ape_scratchpad_read()
860 return -EAGAIN; in tg3_ape_scratchpad_read()
872 len -= length; in tg3_ape_scratchpad_read()
876 return -EAGAIN; in tg3_ape_scratchpad_read()
878 /* Wait for up to 1 msec for APE to service previous event. */ in tg3_ape_scratchpad_read()
897 return -EAGAIN; in tg3_ape_scratchpad_read()
899 for (i = 0; length; i += 4, length -= 4) { in tg3_ape_scratchpad_read()
917 return -EAGAIN; in tg3_ape_send_event()
921 return -EAGAIN; in tg3_ape_send_event()
923 /* Wait for up to 20 millisecond for APE to service previous event. */ in tg3_ape_send_event()
947 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_ape_driver_state_change()
964 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
990 time_before(jiffies, tp->ape_hb_jiffies + interval)) in tg3_send_ape_heartbeat()
993 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_send_ape_heartbeat()
994 tp->ape_hb_jiffies = jiffies; in tg3_send_ape_heartbeat()
1002 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
1003 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1004 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1011 tp->irq_sync = 0; in tg3_enable_ints()
1015 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1017 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1018 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1019 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1021 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1023 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1025 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1030 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1031 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1033 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1035 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1040 struct tg3 *tp = tnapi->tp; in tg3_has_work()
1041 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_has_work()
1046 if (sblk->status & SD_STATUS_LINK_CHG) in tg3_has_work()
1051 if (sblk->idx[0].tx_consumer != tnapi->tx_cons) in tg3_has_work()
1055 if (tnapi->rx_rcb_prod_idx && in tg3_has_work()
1056 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_has_work()
1069 struct tg3 *tp = tnapi->tp; in tg3_int_reenable()
1071 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_int_reenable()
1078 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1079 HOSTCC_MODE_ENABLE | tnapi->coal_now); in tg3_int_reenable()
1096 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1124 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1126 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1130 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1152 loops -= 1; in __tg3_readphy()
1155 ret = -EBUSY; in __tg3_readphy()
1161 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1162 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1166 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1173 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1183 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1187 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1189 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1193 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1213 loops -= 1; in __tg3_writephy()
1216 ret = -EBUSY; in __tg3_writephy()
1220 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1221 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1225 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1232 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1362 return -EBUSY; in tg3_bmcr_reset()
1365 while (limit--) { in tg3_bmcr_reset()
1368 return -EBUSY; in tg3_bmcr_reset()
1377 return -EBUSY; in tg3_bmcr_reset()
1384 struct tg3 *tp = bp->priv; in tg3_mdio_read()
1387 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1390 val = -EIO; in tg3_mdio_read()
1392 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1399 struct tg3 *tp = bp->priv; in tg3_mdio_write()
1402 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1405 ret = -EIO; in tg3_mdio_write()
1407 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1417 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_config_5785()
1418 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_config_5785()
1436 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { in tg3_mdio_config_5785()
1495 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1496 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1513 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1521 tp->phy_addr += 7; in tg3_mdio_init()
1525 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1528 tp->phy_addr = addr; in tg3_mdio_init()
1530 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1537 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1538 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1539 return -ENOMEM; in tg3_mdio_init()
1541 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1542 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(tp->pdev)); in tg3_mdio_init()
1543 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1544 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1545 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1546 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1547 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1550 * Unfortunately, it does not ensure the PHY is powered up before in tg3_mdio_init()
1557 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1559 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1560 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1564 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_init()
1566 if (!phydev || !phydev->drv) { in tg3_mdio_init()
1567 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1568 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1569 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1570 return -ENODEV; in tg3_mdio_init()
1573 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_init()
1575 phydev->interface = PHY_INTERFACE_MODE_GMII; in tg3_mdio_init()
1576 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1580 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | in tg3_mdio_init()
1586 phydev->interface = PHY_INTERFACE_MODE_RGMII; in tg3_mdio_init()
1590 phydev->interface = PHY_INTERFACE_MODE_MII; in tg3_mdio_init()
1591 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1592 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1608 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1609 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1613 /* tp->lock is held. */
1622 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1627 /* tp->lock is held. */
1635 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1636 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - in tg3_wait_for_event_ack()
1650 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1657 /* tp->lock is held. */
1677 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1692 /* tp->lock is held. */
1714 /* tp->lock is held. */
1730 /* tp->lock is held. */
1759 /* tp->lock is held. */
1780 /* tp->lock is held. */
1820 /* Wait up to 20ms for init done. */ in tg3_poll_fw()
1824 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1825 return -ENODEV; in tg3_poll_fw()
1829 return -ENODEV; in tg3_poll_fw()
1837 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1840 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1857 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1872 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1873 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1876 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1877 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1879 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1881 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1884 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1885 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1887 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1890 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1891 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1892 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1897 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1900 static u32 tg3_decode_flowctrl_1000T(u32 adv) in tg3_decode_flowctrl_1000T() argument
1904 if (adv & ADVERTISE_PAUSE_CAP) { in tg3_decode_flowctrl_1000T()
1906 if (!(adv & ADVERTISE_PAUSE_ASYM)) in tg3_decode_flowctrl_1000T()
1908 } else if (adv & ADVERTISE_PAUSE_ASYM) in tg3_decode_flowctrl_1000T()
1930 static u32 tg3_decode_flowctrl_1000X(u32 adv) in tg3_decode_flowctrl_1000X() argument
1934 if (adv & ADVERTISE_1000XPAUSE) { in tg3_decode_flowctrl_1000X()
1936 if (!(adv & ADVERTISE_1000XPSE_ASYM)) in tg3_decode_flowctrl_1000X()
1938 } else if (adv & ADVERTISE_1000XPSE_ASYM) in tg3_decode_flowctrl_1000X()
1964 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1965 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1968 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; in tg3_setup_flow_control()
1970 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1973 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1978 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1980 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
1983 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1985 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1987 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1988 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
1991 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1993 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1995 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
1996 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2004 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_adjust_link()
2006 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2008 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2011 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2013 if (phydev->link) { in tg3_adjust_link()
2017 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) in tg3_adjust_link()
2019 else if (phydev->speed == SPEED_1000 || in tg3_adjust_link()
2025 if (phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2029 tp->link_config.flowctrl); in tg3_adjust_link()
2031 if (phydev->pause) in tg3_adjust_link()
2033 if (phydev->asym_pause) in tg3_adjust_link()
2041 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2042 tp->mac_mode = mac_mode; in tg3_adjust_link()
2043 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2048 if (phydev->speed == SPEED_10) in tg3_adjust_link()
2056 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2067 if (phydev->link != tp->old_link || in tg3_adjust_link()
2068 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2069 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2070 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2073 tp->old_link = phydev->link; in tg3_adjust_link()
2074 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2075 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2077 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2087 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2093 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_init()
2096 phydev = phy_connect(tp->dev, phydev_name(phydev), in tg3_phy_init()
2097 tg3_adjust_link, phydev->interface); in tg3_phy_init()
2099 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2104 switch (phydev->interface) { in tg3_phy_init()
2107 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2118 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_init()
2119 return -EINVAL; in tg3_phy_init()
2122 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2133 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2136 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_start()
2138 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2139 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2140 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2141 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2142 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2144 phydev->advertising, tp->link_config.advertising); in tg3_phy_start()
2154 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2157 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_stop()
2162 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2163 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_fini()
2164 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2173 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2176 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2177 /* Cannot do read-modify-write on 5401 */ in tg3_phy_set_extloopbk()
2224 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2227 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2254 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2257 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2295 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2308 if (!tp->phy_otp) in tg3_phy_apply_otp()
2311 otp = tp->phy_otp; in tg3_phy_apply_otp()
2344 struct ethtool_eee *dest = &tp->eee; in tg3_eee_pull_config()
2346 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2355 /* Pull eee_active */ in tg3_eee_pull_config()
2358 dest->eee_active = 1; in tg3_eee_pull_config()
2360 dest->eee_active = 0; in tg3_eee_pull_config()
2362 /* Pull lp advertised settings */ in tg3_eee_pull_config()
2365 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val); in tg3_eee_pull_config()
2367 /* Pull advertised and eee_enabled settings */ in tg3_eee_pull_config()
2370 dest->eee_enabled = !!val; in tg3_eee_pull_config()
2371 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val); in tg3_eee_pull_config()
2373 /* Pull tx_lpi_enabled */ in tg3_eee_pull_config()
2375 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX); in tg3_eee_pull_config()
2377 /* Pull lpi timer value */ in tg3_eee_pull_config()
2378 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2385 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2388 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2390 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2392 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2393 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2394 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2397 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2405 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2406 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2409 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2425 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2444 while (limit--) { in tg3_wait_macro_done()
2453 return -EBUSY; in tg3_wait_macro_done()
2482 return -EBUSY; in tg3_phy_write_and_check_testpat()
2490 return -EBUSY; in tg3_phy_write_and_check_testpat()
2496 return -EBUSY; in tg3_phy_write_and_check_testpat()
2506 return -EBUSY; in tg3_phy_write_and_check_testpat()
2516 return -EBUSY; in tg3_phy_write_and_check_testpat()
2538 return -EBUSY; in tg3_phy_reset_chanpat()
2566 /* Set full-duplex, 1000 mbps. */ in tg3_phy_reset_5703_4_5()
2587 } while (--retries); in tg3_phy_reset_5703_4_5()
2614 netif_carrier_off(tp->dev); in tg3_carrier_off()
2615 tp->link_up = false; in tg3_carrier_off()
2621 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2622 "Management side-band traffic will be interrupted during phy settings change\n"); in tg3_warn_mgmt_link_flap()
2626 * link unless the FORCE argument is non-zero.
2641 return -EBUSY; in tg3_phy_reset()
2643 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2644 netif_carrier_off(tp->dev); in tg3_phy_reset()
2689 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2694 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2700 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2707 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2712 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2719 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2722 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2735 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2736 /* Cannot do read-modify-write on 5401 */ in tg3_phy_reset()
2739 /* Set bit 14 with read-modify-write to preserve other bits */ in tg3_phy_reset()
2795 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2817 return -EIO; in tg3_pwrsrc_switch_to_vmain()
2821 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2826 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2842 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2864 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2871 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2872 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2873 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ in tg3_pwrsrc_switch_to_vaux()
2879 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2897 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2903 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2916 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2922 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2928 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2975 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2978 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
3005 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3007 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3023 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3027 if (!tp->pci_fn) in tg3_phy_power_bug()
3032 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3033 !tp->pci_fn) in tg3_phy_power_bug()
3046 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3047 !tp->pci_fn) in tg3_phy_led_bug()
3059 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3062 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3081 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3129 /* tp->lock is held. */
3135 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3144 return -ENODEV; in tg3_nvram_lock()
3147 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3152 /* tp->lock is held. */
3156 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3157 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3158 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3163 /* tp->lock is held. */
3173 /* tp->lock is held. */
3190 return -EINVAL; in tg3_nvram_read_using_eeprom()
3210 return -EBUSY; in tg3_nvram_read_using_eeprom()
3239 return -EBUSY; in tg3_nvram_exec_cmd()
3250 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3252 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3254 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3265 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3268 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3269 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); in tg3_nvram_logical_addr()
3278 * machine, the 32-bit value will be byteswapped.
3290 return -EINVAL; in tg3_nvram_read()
3363 rc = -EBUSY; in tg3_nvram_write_block_using_eeprom()
3376 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3377 u32 pagemask = pagesize - 1; in tg3_nvram_write_block_unbuffered()
3383 return -ENOMEM; in tg3_nvram_write_block_unbuffered()
3405 len -= size; in tg3_nvram_write_block_unbuffered()
3409 offset = offset + (pagesize - page_off); in tg3_nvram_write_block_unbuffered()
3451 else if (j == (pagesize - 4)) in tg3_nvram_write_block_unbuffered()
3483 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3491 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3494 if (i == (len - 4)) in tg3_nvram_write_block_buffered()
3504 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3531 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3568 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3580 /* tp->lock is held. */
3591 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3592 return -EBUSY; in tg3_pause_cpu()
3595 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu()
3598 /* tp->lock is held. */
3610 /* tp->lock is held. */
3616 /* tp->lock is held. */
3623 /* tp->lock is held. */
3629 /* tp->lock is held. */
3656 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3658 return -ENODEV; in tg3_halt_cpu()
3676 * tp->fw->size minus headers. in tg3_fw_data_len()
3686 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3687 fw_len = be32_to_cpu(fw_hdr->len); in tg3_fw_data_len()
3689 fw_len = tp->fw->size; in tg3_fw_data_len()
3691 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32); in tg3_fw_data_len()
3694 /* tp->lock is held. */
3701 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3704 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3707 return -EINVAL; in tg3_load_firmware_cpu()
3735 total_len -= TG3_FW_HDR_LEN; in tg3_load_firmware_cpu()
3743 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) + in tg3_load_firmware_cpu()
3747 total_len -= be32_to_cpu(fw_hdr->len); in tg3_load_firmware_cpu()
3751 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len)); in tg3_load_firmware_cpu()
3760 /* tp->lock is held. */
3778 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu_and_set_pc()
3781 /* tp->lock is held. */
3787 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3791 length = end_address_of_bss - start_address_of_text. in tg3_load_5701_a0_firmware_fix()
3809 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3811 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3814 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3815 return -ENODEV; in tg3_load_5701_a0_firmware_fix()
3840 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3841 return -EBUSY; in tg3_validate_rxcpu_state()
3846 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3848 return -EEXIST; in tg3_validate_rxcpu_state()
3854 /* tp->lock is held. */
3865 if (!tp->fw) in tg3_load_57766_firmware()
3870 * data to be written to non-contiguous locations. in tg3_load_57766_firmware()
3882 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3883 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR) in tg3_load_57766_firmware()
3895 /* tp->lock is held. */
3905 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3909 length = end_address_of_bss - start_address_of_text. in tg3_load_tso_firmware()
3913 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3932 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3934 netdev_err(tp->dev, in tg3_load_tso_firmware()
3937 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3938 return -ENODEV; in tg3_load_tso_firmware()
3945 /* tp->lock is held. */
3959 index -= 4; in __tg3_set_one_mac_addr()
3965 /* tp->lock is held. */
3974 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3980 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3983 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
3984 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
3985 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
3986 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
3987 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
3988 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
3999 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
4000 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4009 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4014 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4031 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4038 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4043 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4044 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4049 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_power_down_prepare()
4051 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4053 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4054 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4055 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4057 &tp->link_config.advertising, in tg3_power_down_prepare()
4058 phydev->advertising); in tg3_power_down_prepare()
4082 linkmode_copy(phydev->advertising, advertising); in tg3_power_down_prepare()
4085 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; in tg3_power_down_prepare()
4097 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4098 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4100 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4129 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4131 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4140 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4142 else if (tp->phy_flags & in tg3_power_down_prepare()
4144 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4151 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4165 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4189 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4216 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4219 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4235 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4271 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4272 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4309 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4335 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4358 /* Advertise 100-BaseTX EEE ability */ in tg3_phy_autoneg_cfg()
4361 /* Advertise 1000-BaseT EEE ability */ in tg3_phy_autoneg_cfg()
4365 if (!tp->eee.eee_enabled) { in tg3_phy_autoneg_cfg()
4367 tp->eee.advertised = 0; in tg3_phy_autoneg_cfg()
4369 tp->eee.advertised = advertise & in tg3_phy_autoneg_cfg()
4408 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4409 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4410 u32 adv, fc; in tg3_phy_copper_begin() local
4412 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4413 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4414 adv = ADVERTISED_10baseT_Half | in tg3_phy_copper_begin()
4417 adv |= ADVERTISED_100baseT_Half | in tg3_phy_copper_begin()
4419 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4420 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4422 adv |= ADVERTISED_1000baseT_Half; in tg3_phy_copper_begin()
4423 adv |= ADVERTISED_1000baseT_Full; in tg3_phy_copper_begin()
4428 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4429 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4430 adv &= ~(ADVERTISED_1000baseT_Half | in tg3_phy_copper_begin()
4433 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4436 tg3_phy_autoneg_cfg(tp, adv, fc); in tg3_phy_copper_begin()
4438 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4439 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4453 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4454 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4457 /* With autoneg disabled, 5715 only links up when the in tg3_phy_copper_begin()
4465 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4479 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4513 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4514 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4517 err = -EIO; in tg3_phy_pull_config()
4521 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4524 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4527 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4530 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4533 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4534 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4543 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4545 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4547 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4553 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4554 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4557 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4558 u32 adv; in tg3_phy_pull_config() local
4564 adv = mii_adv_to_ethtool_adv_t(val & ADVERTISE_ALL); in tg3_phy_pull_config()
4565 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4567 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4569 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4572 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4573 u32 adv; in tg3_phy_pull_config() local
4575 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4580 adv = mii_ctrl1000_to_ethtool_adv_t(val); in tg3_phy_pull_config()
4586 adv = tg3_decode_flowctrl_1000X(val); in tg3_phy_pull_config()
4587 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4590 adv = mii_adv_to_ethtool_adv_x(val); in tg3_phy_pull_config()
4593 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4623 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4628 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4629 if (tp->eee.advertised != eee.advertised || in tg3_phy_eee_config_ok()
4630 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4631 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4646 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4650 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4651 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4661 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4690 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4703 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4710 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4712 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4714 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4715 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4716 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4753 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4763 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4767 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4785 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4787 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4793 /* Some third-party PHYs need to be reset on link going in tg3_setup_copper_phy()
4799 tp->link_up) { in tg3_setup_copper_phy()
4808 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4829 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4832 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4853 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4855 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4860 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4870 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4871 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4873 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4922 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4923 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4925 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4939 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4946 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4947 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4953 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4956 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4965 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4972 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4980 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4981 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4986 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
4990 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
4992 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4993 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
4994 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4996 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4997 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
4998 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
5000 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5003 * in RGMII mode, the Led Control Register must be set up. in tg3_setup_copper_phy()
5009 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5011 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5014 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5022 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5023 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5024 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5028 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5029 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5031 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5037 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5039 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5040 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5044 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5059 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5073 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5074 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5075 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5078 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5147 #define ANEG_FAILED -1
5159 if (ap->state == ANEG_STATE_UNKNOWN) { in tg3_fiber_aneg_smachine()
5160 ap->rxconfig = 0; in tg3_fiber_aneg_smachine()
5161 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5162 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5163 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5164 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5165 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5166 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5167 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5169 ap->cur_time++; in tg3_fiber_aneg_smachine()
5174 if (rx_cfg_reg != ap->ability_match_cfg) { in tg3_fiber_aneg_smachine()
5175 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5176 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5177 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5179 if (++ap->ability_match_count > 1) { in tg3_fiber_aneg_smachine()
5180 ap->ability_match = 1; in tg3_fiber_aneg_smachine()
5181 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5185 ap->ack_match = 1; in tg3_fiber_aneg_smachine()
5187 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5189 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5191 ap->idle_match = 1; in tg3_fiber_aneg_smachine()
5192 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5193 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5194 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5195 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5200 ap->rxconfig = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5203 switch (ap->state) { in tg3_fiber_aneg_smachine()
5205 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) in tg3_fiber_aneg_smachine()
5206 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5210 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); in tg3_fiber_aneg_smachine()
5211 if (ap->flags & MR_AN_ENABLE) { in tg3_fiber_aneg_smachine()
5212 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5213 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5214 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5215 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5216 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5217 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5218 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5220 ap->state = ANEG_STATE_RESTART_INIT; in tg3_fiber_aneg_smachine()
5222 ap->state = ANEG_STATE_DISABLE_LINK_OK; in tg3_fiber_aneg_smachine()
5227 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5228 ap->flags &= ~(MR_NP_LOADED); in tg3_fiber_aneg_smachine()
5229 ap->txconfig = 0; in tg3_fiber_aneg_smachine()
5231 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5232 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5236 ap->state = ANEG_STATE_RESTART; in tg3_fiber_aneg_smachine()
5240 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5242 ap->state = ANEG_STATE_ABILITY_DETECT_INIT; in tg3_fiber_aneg_smachine()
5252 ap->flags &= ~(MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5253 ap->txconfig = ANEG_CFG_FD; in tg3_fiber_aneg_smachine()
5254 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5256 ap->txconfig |= ANEG_CFG_PS1; in tg3_fiber_aneg_smachine()
5258 ap->txconfig |= ANEG_CFG_PS2; in tg3_fiber_aneg_smachine()
5259 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5260 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5261 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5264 ap->state = ANEG_STATE_ABILITY_DETECT; in tg3_fiber_aneg_smachine()
5268 if (ap->ability_match != 0 && ap->rxconfig != 0) in tg3_fiber_aneg_smachine()
5269 ap->state = ANEG_STATE_ACK_DETECT_INIT; in tg3_fiber_aneg_smachine()
5273 ap->txconfig |= ANEG_CFG_ACK; in tg3_fiber_aneg_smachine()
5274 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5275 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5276 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5279 ap->state = ANEG_STATE_ACK_DETECT; in tg3_fiber_aneg_smachine()
5283 if (ap->ack_match != 0) { in tg3_fiber_aneg_smachine()
5284 if ((ap->rxconfig & ~ANEG_CFG_ACK) == in tg3_fiber_aneg_smachine()
5285 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { in tg3_fiber_aneg_smachine()
5286 ap->state = ANEG_STATE_COMPLETE_ACK_INIT; in tg3_fiber_aneg_smachine()
5288 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5290 } else if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5291 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5292 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5297 if (ap->rxconfig & ANEG_CFG_INVAL) { in tg3_fiber_aneg_smachine()
5301 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | in tg3_fiber_aneg_smachine()
5310 if (ap->rxconfig & ANEG_CFG_FD) in tg3_fiber_aneg_smachine()
5311 ap->flags |= MR_LP_ADV_FULL_DUPLEX; in tg3_fiber_aneg_smachine()
5312 if (ap->rxconfig & ANEG_CFG_HD) in tg3_fiber_aneg_smachine()
5313 ap->flags |= MR_LP_ADV_HALF_DUPLEX; in tg3_fiber_aneg_smachine()
5314 if (ap->rxconfig & ANEG_CFG_PS1) in tg3_fiber_aneg_smachine()
5315 ap->flags |= MR_LP_ADV_SYM_PAUSE; in tg3_fiber_aneg_smachine()
5316 if (ap->rxconfig & ANEG_CFG_PS2) in tg3_fiber_aneg_smachine()
5317 ap->flags |= MR_LP_ADV_ASYM_PAUSE; in tg3_fiber_aneg_smachine()
5318 if (ap->rxconfig & ANEG_CFG_RF1) in tg3_fiber_aneg_smachine()
5319 ap->flags |= MR_LP_ADV_REMOTE_FAULT1; in tg3_fiber_aneg_smachine()
5320 if (ap->rxconfig & ANEG_CFG_RF2) in tg3_fiber_aneg_smachine()
5321 ap->flags |= MR_LP_ADV_REMOTE_FAULT2; in tg3_fiber_aneg_smachine()
5322 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5323 ap->flags |= MR_LP_ADV_NEXT_PAGE; in tg3_fiber_aneg_smachine()
5325 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5327 ap->flags ^= (MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5328 if (ap->rxconfig & 0x0008) in tg3_fiber_aneg_smachine()
5329 ap->flags |= MR_TOGGLE_RX; in tg3_fiber_aneg_smachine()
5330 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5331 ap->flags |= MR_NP_RX; in tg3_fiber_aneg_smachine()
5332 ap->flags |= MR_PAGE_RX; in tg3_fiber_aneg_smachine()
5334 ap->state = ANEG_STATE_COMPLETE_ACK; in tg3_fiber_aneg_smachine()
5339 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5340 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5341 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5344 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5346 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { in tg3_fiber_aneg_smachine()
5347 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5349 if ((ap->txconfig & ANEG_CFG_NP) == 0 && in tg3_fiber_aneg_smachine()
5350 !(ap->flags & MR_NP_RX)) { in tg3_fiber_aneg_smachine()
5351 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5360 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5361 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5362 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5365 ap->state = ANEG_STATE_IDLE_DETECT; in tg3_fiber_aneg_smachine()
5370 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5371 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5372 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5375 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5378 ap->state = ANEG_STATE_LINK_OK; in tg3_fiber_aneg_smachine()
5383 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); in tg3_fiber_aneg_smachine()
5413 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5417 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5433 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5434 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5472 /* Enable auto-lock and comdet, select txclk for tx. */ in tg3_init_bcm8002()
5517 /* preserve bits 0-11,13,14 for signal pre-emphasis */ in tg3_setup_fiber_hw_autoneg()
5518 /* preserve bits 20-23 for voltage regulator */ in tg3_setup_fiber_hw_autoneg()
5524 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5545 /* Want auto-negotiation. */ in tg3_setup_fiber_hw_autoneg()
5548 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5555 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5556 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5560 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5571 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5572 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5592 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5597 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5598 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5600 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5601 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5617 /* Link parallel detection - link is up */ in tg3_setup_fiber_hw_autoneg()
5625 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5627 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5634 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5635 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5649 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5666 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5693 /* Forcing 1000FD link up. */ in tg3_setup_fiber_by_hand()
5696 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5699 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5716 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5717 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5718 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5721 tp->link_up && in tg3_setup_fiber_phy()
5738 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5739 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5740 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5743 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5750 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5758 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5760 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5775 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5776 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5777 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5780 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5785 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5786 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5787 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5791 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5792 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5793 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5799 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5801 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5802 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5826 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5829 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5834 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5837 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5840 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5849 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5857 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5858 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5866 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5879 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5880 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5881 /* do nothing, just check for link up at the end */ in tg3_setup_fiber_mii_phy()
5882 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5883 u32 adv, newadv; in tg3_setup_fiber_mii_phy() local
5885 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5886 newadv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF | in tg3_setup_fiber_mii_phy()
5891 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5892 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5894 if ((newadv != adv) || !(bmcr & BMCR_ANENABLE)) { in tg3_setup_fiber_mii_phy()
5900 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5901 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5911 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5921 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5922 u32 adv; in tg3_setup_fiber_mii_phy() local
5924 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5925 adv &= ~(ADVERTISE_1000XFULL | in tg3_setup_fiber_mii_phy()
5928 tg3_writephy(tp, MII_ADVERTISE, adv); in tg3_setup_fiber_mii_phy()
5945 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5973 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5976 /* Link is up via parallel detect */ in tg3_setup_fiber_mii_phy()
5987 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5988 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
5989 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5991 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5996 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
5997 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
6005 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
6007 tp->serdes_counter--; in tg3_serdes_parallel_detect()
6011 if (!tp->link_up && in tg3_serdes_parallel_detect()
6012 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6031 * config code words, link is up by parallel in tg3_serdes_parallel_detect()
6038 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6041 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6042 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6043 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6057 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6068 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6070 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6099 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6100 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6108 if (tp->link_up) { in tg3_setup_phy()
6110 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6118 if (!tp->link_up) in tg3_setup_phy()
6120 tp->pwrmgmt_thresh; in tg3_setup_phy()
6129 /* tp->lock must be held */
6142 /* tp->lock must be held */
6159 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | in tg3_get_ts_info()
6164 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | in tg3_get_ts_info()
6169 if (tp->ptp_clock) in tg3_get_ts_info()
6170 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6172 info->phc_index = -1; in tg3_get_ts_info()
6174 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); in tg3_get_ts_info()
6176 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | in tg3_get_ts_info()
6216 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6230 ns += tp->ptp_adjust; in tg3_ptp_gettimex()
6248 tp->ptp_adjust = 0; in tg3_ptp_settime()
6261 switch (rq->type) { in tg3_ptp_enable()
6264 if (rq->perout.flags) in tg3_ptp_enable()
6265 return -EOPNOTSUPP; in tg3_ptp_enable()
6267 if (rq->perout.index != 0) in tg3_ptp_enable()
6268 return -EINVAL; in tg3_ptp_enable()
6277 nsec = rq->perout.start.sec * 1000000000ULL + in tg3_ptp_enable()
6278 rq->perout.start.nsec; in tg3_ptp_enable()
6280 if (rq->perout.period.sec || rq->perout.period.nsec) { in tg3_ptp_enable()
6281 netdev_warn(tp->dev, in tg3_ptp_enable()
6282 "Device supports only a one-shot timesync output, period must be 0\n"); in tg3_ptp_enable()
6283 rval = -EINVAL; in tg3_ptp_enable()
6288 netdev_warn(tp->dev, in tg3_ptp_enable()
6290 rval = -EINVAL; in tg3_ptp_enable()
6314 return -EOPNOTSUPP; in tg3_ptp_enable()
6337 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) + in tg3_hwclock_to_timestamp()
6338 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6341 /* tp->lock must be held */
6349 tp->ptp_adjust = 0; in tg3_ptp_init()
6350 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6353 /* tp->lock must be held */
6359 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6360 tp->ptp_adjust = 0; in tg3_ptp_resume()
6365 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6368 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6369 tp->ptp_clock = NULL; in tg3_ptp_fini()
6370 tp->ptp_adjust = 0; in tg3_ptp_fini()
6375 return tp->irq_sync; in tg3_irq_sync()
6445 if (tp->pdev->error_state != pci_channel_io_normal) { in tg3_dump_state()
6446 netdev_err(tp->dev, "PCI channel ERROR!\n"); in tg3_dump_state()
6455 /* Read up to but not including private PCI registers */ in tg3_dump_state()
6466 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6473 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6474 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6477 netdev_err(tp->dev, in tg3_dump_state()
6480 tnapi->hw_status->status, in tg3_dump_state()
6481 tnapi->hw_status->status_tag, in tg3_dump_state()
6482 tnapi->hw_status->rx_jumbo_consumer, in tg3_dump_state()
6483 tnapi->hw_status->rx_consumer, in tg3_dump_state()
6484 tnapi->hw_status->rx_mini_consumer, in tg3_dump_state()
6485 tnapi->hw_status->idx[0].rx_producer, in tg3_dump_state()
6486 tnapi->hw_status->idx[0].tx_consumer); in tg3_dump_state()
6488 netdev_err(tp->dev, in tg3_dump_state()
6491 tnapi->last_tag, tnapi->last_irq_tag, in tg3_dump_state()
6492 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, in tg3_dump_state()
6493 tnapi->rx_rcb_ptr, in tg3_dump_state()
6494 tnapi->prodring.rx_std_prod_idx, in tg3_dump_state()
6495 tnapi->prodring.rx_std_cons_idx, in tg3_dump_state()
6496 tnapi->prodring.rx_jmb_prod_idx, in tg3_dump_state()
6497 tnapi->prodring.rx_jmb_cons_idx); in tg3_dump_state()
6501 /* This is called whenever we suspect that the system chipset is re-
6510 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6512 netdev_warn(tp->dev, in tg3_tx_recover()
6513 "The system may be re-ordering memory-mapped I/O " in tg3_tx_recover()
6525 return tnapi->tx_pending - in tg3_tx_avail()
6526 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); in tg3_tx_avail()
6535 struct tg3 *tp = tnapi->tp; in tg3_tx()
6536 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_tx()
6537 u32 sw_idx = tnapi->tx_cons; in tg3_tx()
6539 int index = tnapi - tp->napi; in tg3_tx()
6543 index--; in tg3_tx()
6545 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6548 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6549 struct sk_buff *skb = ri->skb; in tg3_tx()
6557 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) { in tg3_tx()
6567 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), in tg3_tx()
6570 ri->skb = NULL; in tg3_tx()
6572 while (ri->fragmented) { in tg3_tx()
6573 ri->fragmented = false; in tg3_tx()
6575 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6580 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in tg3_tx()
6581 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6582 if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) in tg3_tx()
6585 dma_unmap_page(&tp->pdev->dev, in tg3_tx()
6587 skb_frag_size(&skb_shinfo(skb)->frags[i]), in tg3_tx()
6590 while (ri->fragmented) { in tg3_tx()
6591 ri->fragmented = false; in tg3_tx()
6593 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6600 bytes_compl += skb->len; in tg3_tx()
6612 tnapi->tx_cons = sw_idx; in tg3_tx()
6644 if (!ri->data) in tg3_rx_data_free()
6647 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), map_sz, in tg3_rx_data_free()
6649 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data); in tg3_rx_data_free()
6650 ri->data = NULL; in tg3_rx_data_free()
6677 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6678 desc = &tpr->rx_std[dest_idx]; in tg3_alloc_rx_data()
6679 map = &tpr->rx_std_buffers[dest_idx]; in tg3_alloc_rx_data()
6680 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6684 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6685 desc = &tpr->rx_jmb[dest_idx].std; in tg3_alloc_rx_data()
6686 map = &tpr->rx_jmb_buffers[dest_idx]; in tg3_alloc_rx_data()
6691 return -EINVAL; in tg3_alloc_rx_data()
6710 return -ENOMEM; in tg3_alloc_rx_data()
6712 mapping = dma_map_single(&tp->pdev->dev, data + TG3_RX_OFFSET(tp), in tg3_alloc_rx_data()
6714 if (unlikely(dma_mapping_error(&tp->pdev->dev, mapping))) { in tg3_alloc_rx_data()
6716 return -EIO; in tg3_alloc_rx_data()
6719 map->data = data; in tg3_alloc_rx_data()
6722 desc->addr_hi = ((u64)mapping >> 32); in tg3_alloc_rx_data()
6723 desc->addr_lo = ((u64)mapping & 0xffffffff); in tg3_alloc_rx_data()
6737 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx()
6740 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6745 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6746 dest_desc = &dpr->rx_std[dest_idx]; in tg3_recycle_rx()
6747 dest_map = &dpr->rx_std_buffers[dest_idx]; in tg3_recycle_rx()
6748 src_desc = &spr->rx_std[src_idx]; in tg3_recycle_rx()
6749 src_map = &spr->rx_std_buffers[src_idx]; in tg3_recycle_rx()
6753 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6754 dest_desc = &dpr->rx_jmb[dest_idx].std; in tg3_recycle_rx()
6755 dest_map = &dpr->rx_jmb_buffers[dest_idx]; in tg3_recycle_rx()
6756 src_desc = &spr->rx_jmb[src_idx].std; in tg3_recycle_rx()
6757 src_map = &spr->rx_jmb_buffers[src_idx]; in tg3_recycle_rx()
6764 dest_map->data = src_map->data; in tg3_recycle_rx()
6767 dest_desc->addr_hi = src_desc->addr_hi; in tg3_recycle_rx()
6768 dest_desc->addr_lo = src_desc->addr_lo; in tg3_recycle_rx()
6775 src_map->data = NULL; in tg3_recycle_rx()
6790 * it is first placed into the on-chip ram. When the packet's length
6798 * rings, then cache lines never move beyond shared-modified state.
6804 struct tg3 *tp = tnapi->tp; in tg3_rx()
6807 u32 sw_idx = tnapi->rx_rcb_ptr; in tg3_rx()
6810 struct tg3_rx_prodring_set *tpr = &tnapi->prodring; in tg3_rx()
6812 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6820 std_prod_idx = tpr->rx_std_prod_idx; in tg3_rx()
6821 jmb_prod_idx = tpr->rx_jmb_prod_idx; in tg3_rx()
6824 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; in tg3_rx()
6832 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_rx()
6833 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_rx()
6835 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6837 data = ri->data; in tg3_rx()
6841 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6843 data = ri->data; in tg3_rx()
6850 if (desc->err_vlan & RXD_ERR_MASK) { in tg3_rx()
6856 tnapi->rx_dropped++; in tg3_rx()
6861 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - in tg3_rx()
6864 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6866 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6881 dma_unmap_single(&tp->pdev->dev, dma_addr, skb_size, in tg3_rx()
6889 ri->data = NULL; in tg3_rx()
6904 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6910 dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr, len, in tg3_rx()
6912 memcpy(skb->data, in tg3_rx()
6915 dma_sync_single_for_device(&tp->pdev->dev, dma_addr, in tg3_rx()
6924 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6925 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_rx()
6926 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_rx()
6928 skb->ip_summed = CHECKSUM_UNNECESSARY; in tg3_rx()
6932 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6934 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6935 skb->protocol != htons(ETH_P_8021Q) && in tg3_rx()
6936 skb->protocol != htons(ETH_P_8021AD)) { in tg3_rx()
6941 if (desc->type_flags & RXD_FLAG_VLAN && in tg3_rx()
6942 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6944 desc->err_vlan & RXD_VLAN_MASK); in tg3_rx()
6946 napi_gro_receive(&tnapi->napi, skb); in tg3_rx()
6949 budget--; in tg3_rx()
6954 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6955 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
6956 tp->rx_std_ring_mask; in tg3_rx()
6958 tpr->rx_std_prod_idx); in tg3_rx()
6964 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
6968 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6974 tnapi->rx_rcb_ptr = sw_idx; in tg3_rx()
6975 tw32_rx_mbox(tnapi->consmbox, sw_idx); in tg3_rx()
6983 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
6984 tp->rx_std_ring_mask; in tg3_rx()
6986 tpr->rx_std_prod_idx); in tg3_rx()
6989 tpr->rx_jmb_prod_idx = jmb_prod_idx & in tg3_rx()
6990 tp->rx_jmb_ring_mask; in tg3_rx()
6992 tpr->rx_jmb_prod_idx); in tg3_rx()
7000 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
7001 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
7003 if (tnapi != &tp->napi[1]) { in tg3_rx()
7004 tp->rx_refill = true; in tg3_rx()
7005 napi_schedule(&tp->napi[1].napi); in tg3_rx()
7016 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7018 if (sblk->status & SD_STATUS_LINK_CHG) { in tg3_poll_link()
7019 sblk->status = SD_STATUS_UPDATED | in tg3_poll_link()
7020 (sblk->status & ~SD_STATUS_LINK_CHG); in tg3_poll_link()
7021 spin_lock(&tp->lock); in tg3_poll_link()
7031 spin_unlock(&tp->lock); in tg3_poll_link()
7044 src_prod_idx = spr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7051 if (spr->rx_std_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7054 if (spr->rx_std_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7055 cpycnt = src_prod_idx - spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7057 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7058 spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7061 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7063 si = spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7064 di = dpr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7067 if (dpr->rx_std_buffers[i].data) { in tg3_rx_prodring_xfer()
7068 cpycnt = i - di; in tg3_rx_prodring_xfer()
7069 err = -ENOSPC; in tg3_rx_prodring_xfer()
7083 memcpy(&dpr->rx_std_buffers[di], in tg3_rx_prodring_xfer()
7084 &spr->rx_std_buffers[si], in tg3_rx_prodring_xfer()
7089 sbd = &spr->rx_std[si]; in tg3_rx_prodring_xfer()
7090 dbd = &dpr->rx_std[di]; in tg3_rx_prodring_xfer()
7091 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7092 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7095 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7096 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7097 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7098 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7102 src_prod_idx = spr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7109 if (spr->rx_jmb_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7112 if (spr->rx_jmb_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7113 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7115 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7116 spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7119 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7121 si = spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7122 di = dpr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7125 if (dpr->rx_jmb_buffers[i].data) { in tg3_rx_prodring_xfer()
7126 cpycnt = i - di; in tg3_rx_prodring_xfer()
7127 err = -ENOSPC; in tg3_rx_prodring_xfer()
7141 memcpy(&dpr->rx_jmb_buffers[di], in tg3_rx_prodring_xfer()
7142 &spr->rx_jmb_buffers[si], in tg3_rx_prodring_xfer()
7147 sbd = &spr->rx_jmb[si].std; in tg3_rx_prodring_xfer()
7148 dbd = &dpr->rx_jmb[di].std; in tg3_rx_prodring_xfer()
7149 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7150 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7153 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7154 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7155 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7156 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7164 struct tg3 *tp = tnapi->tp; in tg3_poll_work()
7167 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { in tg3_poll_work()
7173 if (!tnapi->rx_rcb_prod_idx) in tg3_poll_work()
7178 * code synchronizes with tg3->napi.poll() in tg3_poll_work()
7180 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_poll_work()
7181 work_done += tg3_rx(tnapi, budget - work_done); in tg3_poll_work()
7183 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7184 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7186 u32 std_prod_idx = dpr->rx_std_prod_idx; in tg3_poll_work()
7187 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; in tg3_poll_work()
7189 tp->rx_refill = false; in tg3_poll_work()
7190 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7192 &tp->napi[i].prodring); in tg3_poll_work()
7196 if (std_prod_idx != dpr->rx_std_prod_idx) in tg3_poll_work()
7198 dpr->rx_std_prod_idx); in tg3_poll_work()
7200 if (jmb_prod_idx != dpr->rx_jmb_prod_idx) in tg3_poll_work()
7202 dpr->rx_jmb_prod_idx); in tg3_poll_work()
7205 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7213 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7214 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7219 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_cancel()
7220 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7227 struct tg3 *tp = tnapi->tp; in tg3_poll_msix()
7229 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll_msix()
7240 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll_msix()
7244 tnapi->last_tag = sblk->status_tag; in tg3_poll_msix()
7245 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll_msix()
7249 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && in tg3_poll_msix()
7250 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { in tg3_poll_msix()
7255 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7260 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_poll_msix()
7265 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7266 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7268 tnapi->coal_now); in tg3_poll_msix()
7295 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7300 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7305 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7321 struct tg3 *tp = tnapi->tp; in tg3_poll()
7323 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll()
7326 if (sblk->status & SD_STATUS_ERROR) in tg3_poll()
7340 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll()
7344 tnapi->last_tag = sblk->status_tag; in tg3_poll()
7345 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll()
7348 sblk->status &= ~SD_STATUS_UPDATED; in tg3_poll()
7371 for (i = tp->irq_cnt - 1; i >= 0; i--) in tg3_napi_disable()
7372 napi_disable(&tp->napi[i].napi); in tg3_napi_disable()
7379 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_enable()
7380 napi_enable(&tp->napi[i].napi); in tg3_napi_enable()
7387 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll); in tg3_napi_init()
7388 for (i = 1; i < tp->irq_cnt; i++) in tg3_napi_init()
7389 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix); in tg3_napi_init()
7396 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7397 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7402 netif_trans_update(tp->dev); /* prevent tx timeout */ in tg3_netif_stop()
7404 netif_carrier_off(tp->dev); in tg3_netif_stop()
7405 netif_tx_disable(tp->dev); in tg3_netif_stop()
7408 /* tp->lock must be held */
7417 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7419 if (tp->link_up) in tg3_netif_start()
7420 netif_carrier_on(tp->dev); in tg3_netif_start()
7423 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7428 __releases(tp->lock) in tg3_irq_quiesce()
7429 __acquires(tp->lock) in tg3_irq_quiesce()
7433 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7435 tp->irq_sync = 1; in tg3_irq_quiesce()
7438 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7440 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7441 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7443 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7447 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7453 spin_lock_bh(&tp->lock); in tg3_full_lock()
7460 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7463 /* One-shot MSI handler - Chip automatically disables interrupt
7469 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot()
7471 prefetch(tnapi->hw_status); in tg3_msi_1shot()
7472 if (tnapi->rx_rcb) in tg3_msi_1shot()
7473 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi_1shot()
7476 napi_schedule(&tnapi->napi); in tg3_msi_1shot()
7481 /* MSI ISR - No need to check for interrupt sharing and no need to
7488 struct tg3 *tp = tnapi->tp; in tg3_msi()
7490 prefetch(tnapi->hw_status); in tg3_msi()
7491 if (tnapi->rx_rcb) in tg3_msi()
7492 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi()
7494 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_msi()
7495 * chip-internal interrupt pending events. in tg3_msi()
7496 * Writing non-zero to intr-mbox-0 additional tells the in tg3_msi()
7497 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_msi()
7500 tw32_mailbox(tnapi->int_mbox, 0x00000001); in tg3_msi()
7502 napi_schedule(&tnapi->napi); in tg3_msi()
7510 struct tg3 *tp = tnapi->tp; in tg3_interrupt()
7511 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt()
7519 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { in tg3_interrupt()
7528 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt()
7529 * chip-internal interrupt pending events. in tg3_interrupt()
7530 * Writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt()
7531 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt()
7534 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt()
7541 sblk->status &= ~SD_STATUS_UPDATED; in tg3_interrupt()
7543 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt()
7544 napi_schedule(&tnapi->napi); in tg3_interrupt()
7546 /* No work, shared interrupt perhaps? re-enable in tg3_interrupt()
7559 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged()
7560 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt_tagged()
7568 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { in tg3_interrupt_tagged()
7577 * writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt_tagged()
7578 * chip-internal interrupt pending events. in tg3_interrupt_tagged()
7579 * writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt_tagged()
7580 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt_tagged()
7583 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt_tagged()
7595 tnapi->last_irq_tag = sblk->status_tag; in tg3_interrupt_tagged()
7600 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt_tagged()
7602 napi_schedule(&tnapi->napi); in tg3_interrupt_tagged()
7612 struct tg3 *tp = tnapi->tp; in tg3_test_isr()
7613 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_test_isr()
7615 if ((sblk->status & SD_STATUS_UPDATED) || in tg3_test_isr()
7632 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7633 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7671 /* Test for DMA addresses > 40-bit */
7688 txbd->addr_hi = ((u64) mapping >> 32); in tg3_tx_set_bd()
7689 txbd->addr_lo = ((u64) mapping & 0xffffffff); in tg3_tx_set_bd()
7690 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); in tg3_tx_set_bd()
7691 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); in tg3_tx_set_bd()
7698 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set()
7713 if (tp->dma_limit) { in tg3_tx_frag_set()
7716 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7717 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7718 len -= tp->dma_limit; in tg3_tx_frag_set()
7722 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7723 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7726 tnapi->tx_buffers[*entry].fragmented = true; in tg3_tx_frag_set()
7728 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7730 *budget -= 1; in tg3_tx_frag_set()
7739 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7741 *budget -= 1; in tg3_tx_frag_set()
7745 tnapi->tx_buffers[prvidx].fragmented = false; in tg3_tx_frag_set()
7749 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7761 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7763 skb = txb->skb; in tg3_tx_skb_unmap()
7764 txb->skb = NULL; in tg3_tx_skb_unmap()
7766 dma_unmap_single(&tnapi->tp->pdev->dev, dma_unmap_addr(txb, mapping), in tg3_tx_skb_unmap()
7769 while (txb->fragmented) { in tg3_tx_skb_unmap()
7770 txb->fragmented = false; in tg3_tx_skb_unmap()
7772 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7776 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_tx_skb_unmap()
7779 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7781 dma_unmap_page(&tnapi->tp->pdev->dev, in tg3_tx_skb_unmap()
7785 while (txb->fragmented) { in tg3_tx_skb_unmap()
7786 txb->fragmented = false; in tg3_tx_skb_unmap()
7788 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7793 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7799 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround()
7807 int more_headroom = 4 - ((unsigned long)skb->data & 3); in tigon3_dma_hwbug_workaround()
7815 ret = -1; in tigon3_dma_hwbug_workaround()
7818 new_addr = dma_map_single(&tp->pdev->dev, new_skb->data, in tigon3_dma_hwbug_workaround()
7819 new_skb->len, DMA_TO_DEVICE); in tigon3_dma_hwbug_workaround()
7821 if (dma_mapping_error(&tp->pdev->dev, new_addr)) { in tigon3_dma_hwbug_workaround()
7823 ret = -1; in tigon3_dma_hwbug_workaround()
7829 tnapi->tx_buffers[*entry].skb = new_skb; in tigon3_dma_hwbug_workaround()
7830 dma_unmap_addr_set(&tnapi->tx_buffers[*entry], in tigon3_dma_hwbug_workaround()
7834 new_skb->len, base_flags, in tigon3_dma_hwbug_workaround()
7836 tg3_tx_skb_unmap(tnapi, save_entry, -1); in tigon3_dma_hwbug_workaround()
7838 ret = -1; in tigon3_dma_hwbug_workaround()
7853 return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3; in tg3_tso_bug_gso_check()
7864 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; in tg3_tso_bug()
7883 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7886 tnapi->tx_dropped++; in tg3_tso_bug()
7892 tg3_start_xmit(seg, tp->dev); in tg3_tso_bug()
7907 int i = -1, would_hit_hwbug; in tg3_start_xmit()
7918 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in tg3_start_xmit()
7925 * and TX reclaim runs via tp->napi.poll inside of a software in tg3_start_xmit()
7929 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { in tg3_start_xmit()
7940 entry = tnapi->tx_prod; in tg3_start_xmit()
7943 mss = skb_shinfo(skb)->gso_size; in tg3_start_xmit()
7953 hdr_len = skb_tcp_all_headers(skb) - ETH_HLEN; in tg3_start_xmit()
7958 if (skb->protocol == htons(ETH_P_8021Q) || in tg3_start_xmit()
7959 skb->protocol == htons(ETH_P_8021AD)) { in tg3_start_xmit()
7972 ip_csum = iph->check; in tg3_start_xmit()
7973 ip_tot_len = iph->tot_len; in tg3_start_xmit()
7974 iph->check = 0; in tg3_start_xmit()
7975 iph->tot_len = htons(mss + hdr_len); in tg3_start_xmit()
7982 tcp_csum = tcph->check; in tg3_start_xmit()
7987 tcph->check = 0; in tg3_start_xmit()
7990 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, in tg3_start_xmit()
8003 if (tcp_opt_len || iph->ihl > 5) { in tg3_start_xmit()
8006 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in tg3_start_xmit()
8010 if (tcp_opt_len || iph->ihl > 5) { in tg3_start_xmit()
8013 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in tg3_start_xmit()
8017 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { in tg3_start_xmit()
8021 if (skb->protocol == htons(ETH_P_8021Q) || in tg3_start_xmit()
8022 skb->protocol == htons(ETH_P_8021AD)) { in tg3_start_xmit()
8031 !mss && skb->len > VLAN_ETH_FRAME_LEN) in tg3_start_xmit()
8039 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) && in tg3_start_xmit()
8041 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in tg3_start_xmit()
8047 mapping = dma_map_single(&tp->pdev->dev, skb->data, len, in tg3_start_xmit()
8049 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8053 tnapi->tx_buffers[entry].skb = skb; in tg3_start_xmit()
8054 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); in tg3_start_xmit()
8062 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), in tg3_start_xmit()
8065 } else if (skb_shinfo(skb)->nr_frags > 0) { in tg3_start_xmit()
8076 last = skb_shinfo(skb)->nr_frags - 1; in tg3_start_xmit()
8078 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_start_xmit()
8081 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in tg3_start_xmit()
8084 tnapi->tx_buffers[entry].skb = NULL; in tg3_start_xmit()
8085 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, in tg3_start_xmit()
8087 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8102 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); in tg3_start_xmit()
8109 iph->check = ip_csum; in tg3_start_xmit()
8110 iph->tot_len = ip_tot_len; in tg3_start_xmit()
8112 tcph->check = tcp_csum; in tg3_start_xmit()
8119 entry = tnapi->tx_prod; in tg3_start_xmit()
8127 netdev_tx_sent_queue(txq, skb->len); in tg3_start_xmit()
8132 tnapi->tx_prod = entry; in tg3_start_xmit()
8148 tw32_tx_mbox(tnapi->prodmbox, entry); in tg3_start_xmit()
8154 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); in tg3_start_xmit()
8155 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; in tg3_start_xmit()
8159 tnapi->tx_dropped++; in tg3_start_xmit()
8166 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8169 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8172 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8174 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8175 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8177 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8179 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8182 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8184 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8187 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8199 return -EIO; in tg3_phy_lpbk_set()
8210 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8220 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8236 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8241 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8252 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8256 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8259 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8267 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8289 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8292 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8294 netif_carrier_on(tp->dev); in tg3_set_loopback()
8295 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8298 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8301 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8305 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8315 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8323 netdev_features_t changed = dev->features ^ features; in tg3_set_features()
8336 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8337 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; in tg3_rx_prodring_free()
8338 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8339 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8340 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8343 for (i = tpr->rx_jmb_cons_idx; in tg3_rx_prodring_free()
8344 i != tpr->rx_jmb_prod_idx; in tg3_rx_prodring_free()
8345 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8346 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8354 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8355 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8356 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8359 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8360 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8369 * end up in the driver. tp->{tx,}lock are held and thus
8377 tpr->rx_std_cons_idx = 0; in tg3_rx_prodring_alloc()
8378 tpr->rx_std_prod_idx = 0; in tg3_rx_prodring_alloc()
8379 tpr->rx_jmb_cons_idx = 0; in tg3_rx_prodring_alloc()
8380 tpr->rx_jmb_prod_idx = 0; in tg3_rx_prodring_alloc()
8382 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8383 memset(&tpr->rx_std_buffers[0], 0, in tg3_rx_prodring_alloc()
8385 if (tpr->rx_jmb_buffers) in tg3_rx_prodring_alloc()
8386 memset(&tpr->rx_jmb_buffers[0], 0, in tg3_rx_prodring_alloc()
8392 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8396 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8398 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8404 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8407 rxd = &tpr->rx_std[i]; in tg3_rx_prodring_alloc()
8408 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8409 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); in tg3_rx_prodring_alloc()
8410 rxd->opaque = (RXD_OPAQUE_RING_STD | in tg3_rx_prodring_alloc()
8415 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8420 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8423 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8426 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8434 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8439 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8442 rxd = &tpr->rx_jmb[i].std; in tg3_rx_prodring_alloc()
8443 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8444 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | in tg3_rx_prodring_alloc()
8446 rxd->opaque = (RXD_OPAQUE_RING_JUMBO | in tg3_rx_prodring_alloc()
8450 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8455 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8458 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8461 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8471 return -ENOMEM; in tg3_rx_prodring_alloc()
8477 kfree(tpr->rx_std_buffers); in tg3_rx_prodring_fini()
8478 tpr->rx_std_buffers = NULL; in tg3_rx_prodring_fini()
8479 kfree(tpr->rx_jmb_buffers); in tg3_rx_prodring_fini()
8480 tpr->rx_jmb_buffers = NULL; in tg3_rx_prodring_fini()
8481 if (tpr->rx_std) { in tg3_rx_prodring_fini()
8482 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8483 tpr->rx_std, tpr->rx_std_mapping); in tg3_rx_prodring_fini()
8484 tpr->rx_std = NULL; in tg3_rx_prodring_fini()
8486 if (tpr->rx_jmb) { in tg3_rx_prodring_fini()
8487 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8488 tpr->rx_jmb, tpr->rx_jmb_mapping); in tg3_rx_prodring_fini()
8489 tpr->rx_jmb = NULL; in tg3_rx_prodring_fini()
8496 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8498 if (!tpr->rx_std_buffers) in tg3_rx_prodring_init()
8499 return -ENOMEM; in tg3_rx_prodring_init()
8501 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8503 &tpr->rx_std_mapping, in tg3_rx_prodring_init()
8505 if (!tpr->rx_std) in tg3_rx_prodring_init()
8509 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8511 if (!tpr->rx_jmb_buffers) in tg3_rx_prodring_init()
8514 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8516 &tpr->rx_jmb_mapping, in tg3_rx_prodring_init()
8518 if (!tpr->rx_jmb) in tg3_rx_prodring_init()
8526 return -ENOMEM; in tg3_rx_prodring_init()
8529 /* Free up pending packets in all rx/tx rings.
8533 * end up in the driver. tp->{tx,}lock is not held and we are not
8540 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8541 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8543 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8545 if (!tnapi->tx_buffers) in tg3_free_rings()
8549 struct sk_buff *skb = tnapi->tx_buffers[i].skb; in tg3_free_rings()
8555 skb_shinfo(skb)->nr_frags - 1); in tg3_free_rings()
8559 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8567 * end up in the driver. tp->{tx,}lock are held and thus
8574 /* Free up all the SKBs. */ in tg3_init_rings()
8577 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8578 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8580 tnapi->last_tag = 0; in tg3_init_rings()
8581 tnapi->last_irq_tag = 0; in tg3_init_rings()
8582 tnapi->hw_status->status = 0; in tg3_init_rings()
8583 tnapi->hw_status->status_tag = 0; in tg3_init_rings()
8584 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_init_rings()
8586 tnapi->tx_prod = 0; in tg3_init_rings()
8587 tnapi->tx_cons = 0; in tg3_init_rings()
8588 if (tnapi->tx_ring) in tg3_init_rings()
8589 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); in tg3_init_rings()
8591 tnapi->rx_rcb_ptr = 0; in tg3_init_rings()
8592 if (tnapi->rx_rcb) in tg3_init_rings()
8593 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8595 if (tnapi->prodring.rx_std && in tg3_init_rings()
8596 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8598 return -ENOMEM; in tg3_init_rings()
8609 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8610 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8612 if (tnapi->tx_ring) { in tg3_mem_tx_release()
8613 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8614 tnapi->tx_ring, tnapi->tx_desc_mapping); in tg3_mem_tx_release()
8615 tnapi->tx_ring = NULL; in tg3_mem_tx_release()
8618 kfree(tnapi->tx_buffers); in tg3_mem_tx_release()
8619 tnapi->tx_buffers = NULL; in tg3_mem_tx_release()
8626 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8634 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8635 tnapi->tx_buffers = kcalloc(TG3_TX_RING_SIZE, in tg3_mem_tx_acquire()
8638 if (!tnapi->tx_buffers) in tg3_mem_tx_acquire()
8641 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8643 &tnapi->tx_desc_mapping, in tg3_mem_tx_acquire()
8645 if (!tnapi->tx_ring) in tg3_mem_tx_acquire()
8653 return -ENOMEM; in tg3_mem_tx_acquire()
8660 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8661 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8663 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8665 if (!tnapi->rx_rcb) in tg3_mem_rx_release()
8668 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8670 tnapi->rx_rcb, in tg3_mem_rx_release()
8671 tnapi->rx_rcb_mapping); in tg3_mem_rx_release()
8672 tnapi->rx_rcb = NULL; in tg3_mem_rx_release()
8680 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8689 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8691 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8701 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8703 &tnapi->rx_rcb_mapping, in tg3_mem_rx_acquire()
8705 if (!tnapi->rx_rcb) in tg3_mem_rx_acquire()
8713 return -ENOMEM; in tg3_mem_rx_acquire()
8724 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8725 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8727 if (tnapi->hw_status) { in tg3_free_consistent()
8728 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8729 tnapi->hw_status, in tg3_free_consistent()
8730 tnapi->status_mapping); in tg3_free_consistent()
8731 tnapi->hw_status = NULL; in tg3_free_consistent()
8738 /* tp->hw_stats can be referenced safely: in tg3_free_consistent()
8740 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set. in tg3_free_consistent()
8742 if (tp->hw_stats) { in tg3_free_consistent()
8743 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8744 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8745 tp->hw_stats = NULL; in tg3_free_consistent()
8757 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8759 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8760 if (!tp->hw_stats) in tg3_alloc_consistent()
8763 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8764 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8767 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8769 &tnapi->status_mapping, in tg3_alloc_consistent()
8771 if (!tnapi->hw_status) in tg3_alloc_consistent()
8774 sblk = tnapi->hw_status; in tg3_alloc_consistent()
8787 prodptr = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8790 prodptr = &sblk->rx_jumbo_consumer; in tg3_alloc_consistent()
8793 prodptr = &sblk->reserved; in tg3_alloc_consistent()
8796 prodptr = &sblk->rx_mini_consumer; in tg3_alloc_consistent()
8799 tnapi->rx_rcb_prod_idx = prodptr; in tg3_alloc_consistent()
8801 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8812 return -ENOMEM; in tg3_alloc_consistent()
8818 * clears. tp->lock is held.
8847 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8848 dev_err(&tp->pdev->dev, in tg3_stop_block()
8852 return -ENODEV; in tg3_stop_block()
8862 dev_err(&tp->pdev->dev, in tg3_stop_block()
8865 return -ENODEV; in tg3_stop_block()
8871 /* tp->lock is held. */
8878 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8879 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8880 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8881 err = -ENODEV; in tg3_abort_hw()
8885 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8886 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
8904 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8905 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
8908 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
8909 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
8917 dev_err(&tp->pdev->dev, in tg3_abort_hw()
8920 err |= -ENODEV; in tg3_abort_hw()
8934 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
8935 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
8936 if (tnapi->hw_status) in tg3_abort_hw()
8937 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_abort_hw()
8946 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
8954 /* Re-enable indirect register accesses. */ in tg3_restore_pci_state()
8955 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
8956 tp->misc_host_ctrl); in tg3_restore_pci_state()
8968 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
8970 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
8973 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
8974 tp->pci_cacheline_sz); in tg3_restore_pci_state()
8975 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
8976 tp->pci_lat_timer); in tg3_restore_pci_state()
8979 /* Make sure PCI-X relaxed ordering bit is clear. */ in tg3_restore_pci_state()
8983 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8986 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8998 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
8999 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9001 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
9002 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9053 /* tp->lock is held. */
9055 __releases(tp->lock) in tg3_chip_reset()
9056 __acquires(tp->lock) in tg3_chip_reset()
9062 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9063 return -ENODEV; in tg3_chip_reset()
9072 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9090 write_op = tp->write32; in tg3_chip_reset()
9092 tp->write32 = tg3_write32; in tg3_chip_reset()
9101 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9102 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9103 if (tnapi->hw_status) { in tg3_chip_reset()
9104 tnapi->hw_status->status = 0; in tg3_chip_reset()
9105 tnapi->hw_status->status_tag = 0; in tg3_chip_reset()
9107 tnapi->last_tag = 0; in tg3_chip_reset()
9108 tnapi->last_irq_tag = 0; in tg3_chip_reset()
9114 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9115 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9161 tp->write32 = write_op; in tg3_chip_reset()
9184 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9188 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9199 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9200 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9212 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9215 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9251 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9259 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9261 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9263 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9264 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9267 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9268 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9269 val = tp->mac_mode; in tg3_chip_reset()
9270 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9271 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9272 val = tp->mac_mode; in tg3_chip_reset()
9305 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9316 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9322 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9324 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9335 /* tp->lock is held. */
9352 if (tp->hw_stats) { in tg3_halt()
9354 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9355 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9358 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9361 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_halt()
9363 tnapi->rx_dropped = 0; in tg3_halt()
9364 tnapi->tx_dropped = 0; in tg3_halt()
9378 if (!is_valid_ether_addr(addr->sa_data)) in tg3_set_mac_addr()
9379 return -EADDRNOTAVAIL; in tg3_set_mac_addr()
9381 eth_hw_addr_set(dev, addr->sa_data); in tg3_set_mac_addr()
9399 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9402 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9407 /* tp->lock is held. */
9434 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9435 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9436 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9442 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9446 tw32(reg, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9448 tw32(reg, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9450 tw32(reg, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9454 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9464 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9467 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9468 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9469 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9470 limit--; in tg3_coal_rx_init()
9481 tw32(reg, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9483 tw32(reg, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9485 tw32(reg, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9488 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9501 u32 val = ec->stats_block_coalesce_usecs; in __tg3_set_coalesce()
9503 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); in __tg3_set_coalesce()
9504 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); in __tg3_set_coalesce()
9506 if (!tp->link_up) in __tg3_set_coalesce()
9513 /* tp->lock is held. */
9535 /* tp->lock is held. */
9544 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9545 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9547 if (!tnapi->tx_ring) in tg3_tx_rcbs_init()
9550 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9556 /* tp->lock is held. */
9579 /* tp->lock is held. */
9588 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9589 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9591 if (!tnapi->rx_rcb) in tg3_rx_ret_rcbs_init()
9594 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9595 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9600 /* tp->lock is held. */
9605 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9612 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9613 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9614 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9615 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9619 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9620 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9621 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9623 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9624 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9625 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9626 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9627 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9628 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9631 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9633 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9634 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9635 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9636 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9639 /* Make sure the NIC-based send BD rings are disabled. */ in tg3_rings_reset()
9647 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9651 ((u64) tnapi->status_mapping >> 32)); in tg3_rings_reset()
9653 ((u64) tnapi->status_mapping & 0xffffffff)); in tg3_rings_reset()
9657 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9658 u64 mapping = (u64)tnapi->status_mapping; in tg3_rings_reset()
9664 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9687 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9688 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9701 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9748 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9759 if (dev->flags & IFF_PROMISC) { in __tg3_set_rx_mode()
9762 } else if (dev->flags & IFF_ALLMULTI) { in __tg3_set_rx_mode()
9777 crc = calc_crc(ha->addr, ETH_ALEN); in __tg3_set_rx_mode()
9792 } else if (!(dev->flags & IFF_PROMISC)) { in __tg3_set_rx_mode()
9798 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9804 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9805 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9816 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9826 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9827 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9833 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9838 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9847 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9851 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9866 /* tp->lock is held. */
9871 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9882 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9883 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9886 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9890 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
10004 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
10005 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
10051 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10057 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10060 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10064 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10066 /* Pseudo-header checksum is done by hardware logic and not in tg3_reset_hw()
10067 * the offload processers, so make the chip do the pseudo- in tg3_reset_hw()
10069 * convenient to do the pseudo-header checksum in software in tg3_reset_hw()
10072 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10075 if (tp->rxptpctl) in tg3_reset_hw()
10077 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10082 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10088 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_reset_hw()
10089 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) { in tg3_reset_hw()
10114 fw_len = tp->fw_len; in tg3_reset_hw()
10115 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); in tg3_reset_hw()
10119 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); in tg3_reset_hw()
10122 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10124 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10126 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10128 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10131 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10133 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10135 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10138 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10140 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10157 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10158 return -ENODEV; in tg3_reset_hw()
10184 ((u64) tpr->rx_std_mapping >> 32)); in tg3_reset_hw()
10186 ((u64) tpr->rx_std_mapping & 0xffffffff)); in tg3_reset_hw()
10204 ((u64) tpr->rx_jmb_mapping >> 32)); in tg3_reset_hw()
10206 ((u64) tpr->rx_jmb_mapping & 0xffffffff)); in tg3_reset_hw()
10232 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10233 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); in tg3_reset_hw()
10235 tpr->rx_jmb_prod_idx = in tg3_reset_hw()
10236 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10237 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); in tg3_reset_hw()
10246 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10300 tp->dma_limit = 0; in tg3_reset_hw()
10301 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10303 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10389 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10397 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10399 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10413 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10420 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10421 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10427 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10431 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10433 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10435 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10436 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10439 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). in tg3_reset_hw()
10459 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10460 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10464 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10467 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10473 if (tp->irq_cnt > 1) in tg3_reset_hw()
10516 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10525 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10592 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10596 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10601 tp->tx_mode &= ~val; in tg3_reset_hw()
10602 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10605 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10619 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10621 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10624 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10627 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10634 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10637 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10640 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10644 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10647 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10649 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10651 /* only if the signal pre-emphasis bit is not set */ in tg3_reset_hw()
10671 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10672 /* Use hardware link auto-negotiation */ in tg3_reset_hw()
10676 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10682 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10683 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10684 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10688 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10689 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10695 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10696 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10708 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10721 limit -= 4; in tg3_reset_hw()
10781 * packet processing. Invoked with tp->lock held.
10808 if (ocir->signature != TG3_OCIR_SIG_MAGIC || in tg3_sd_scan_scratchpad()
10809 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE)) in tg3_sd_scan_scratchpad()
10822 spin_lock_bh(&tp->lock); in tg3_show_temp()
10823 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10825 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10847 if (tp->hwmon_dev) { in tg3_hwmon_close()
10848 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10849 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10857 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10873 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10875 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10876 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10877 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n"); in tg3_hwmon_open()
10888 (PSTAT)->low += __val; \
10889 if ((PSTAT)->low < __val) \
10890 (PSTAT)->high += 1; \
10895 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10897 if (!tp->link_up) in tg3_periodic_fetch_stats()
10900 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10901 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); in tg3_periodic_fetch_stats()
10902 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); in tg3_periodic_fetch_stats()
10903 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); in tg3_periodic_fetch_stats()
10904 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); in tg3_periodic_fetch_stats()
10905 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); in tg3_periodic_fetch_stats()
10906 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); in tg3_periodic_fetch_stats()
10907 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); in tg3_periodic_fetch_stats()
10908 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); in tg3_periodic_fetch_stats()
10909 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); in tg3_periodic_fetch_stats()
10910 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); in tg3_periodic_fetch_stats()
10911 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); in tg3_periodic_fetch_stats()
10912 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); in tg3_periodic_fetch_stats()
10914 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low + in tg3_periodic_fetch_stats()
10915 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) { in tg3_periodic_fetch_stats()
10924 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10925 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); in tg3_periodic_fetch_stats()
10926 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); in tg3_periodic_fetch_stats()
10927 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); in tg3_periodic_fetch_stats()
10928 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); in tg3_periodic_fetch_stats()
10929 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); in tg3_periodic_fetch_stats()
10930 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); in tg3_periodic_fetch_stats()
10931 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); in tg3_periodic_fetch_stats()
10932 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); in tg3_periodic_fetch_stats()
10933 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); in tg3_periodic_fetch_stats()
10934 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); in tg3_periodic_fetch_stats()
10935 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); in tg3_periodic_fetch_stats()
10936 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); in tg3_periodic_fetch_stats()
10937 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); in tg3_periodic_fetch_stats()
10939 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); in tg3_periodic_fetch_stats()
10944 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); in tg3_periodic_fetch_stats()
10950 sp->rx_discards.low += val; in tg3_periodic_fetch_stats()
10951 if (sp->rx_discards.low < val) in tg3_periodic_fetch_stats()
10952 sp->rx_discards.high += 1; in tg3_periodic_fetch_stats()
10954 sp->mbuf_lwm_thresh_hit = sp->rx_discards; in tg3_periodic_fetch_stats()
10956 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); in tg3_periodic_fetch_stats()
10963 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
10964 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
10967 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && in tg3_chk_missed_msi()
10968 tnapi->last_tx_cons == tnapi->tx_cons) { in tg3_chk_missed_msi()
10969 if (tnapi->chk_msi_cnt < 1) { in tg3_chk_missed_msi()
10970 tnapi->chk_msi_cnt++; in tg3_chk_missed_msi()
10976 tnapi->chk_msi_cnt = 0; in tg3_chk_missed_msi()
10977 tnapi->last_rx_cons = tnapi->rx_rcb_ptr; in tg3_chk_missed_msi()
10978 tnapi->last_tx_cons = tnapi->tx_cons; in tg3_chk_missed_msi()
10986 spin_lock(&tp->lock); in tg3_timer()
10988 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
10989 spin_unlock(&tp->lock); in tg3_timer()
11003 /* All of this garbage is because when using non-tagged in tg3_timer()
11007 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
11009 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
11011 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11016 spin_unlock(&tp->lock); in tg3_timer()
11023 if (!--tp->timer_counter) { in tg3_timer()
11027 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
11037 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
11049 if (tp->link_up && in tg3_timer()
11053 if (!tp->link_up && in tg3_timer()
11059 if (!tp->serdes_counter) { in tg3_timer()
11061 (tp->mac_mode & in tg3_timer()
11064 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11069 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11077 if (link_up != tp->link_up) in tg3_timer()
11081 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11088 * ASF needs to reset the hardware to free up the FIFO space in tg3_timer()
11101 if (!--tp->asf_counter) { in tg3_timer()
11113 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11119 spin_unlock(&tp->lock); in tg3_timer()
11122 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11123 add_timer(&tp->timer); in tg3_timer()
11131 tp->timer_offset = HZ; in tg3_timer_init()
11133 tp->timer_offset = HZ / 10; in tg3_timer_init()
11135 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11137 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11138 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11141 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11146 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11147 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11149 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11150 add_timer(&tp->timer); in tg3_timer_start()
11155 del_timer_sync(&tp->timer); in tg3_timer_stop()
11158 /* Restart hardware after configuration changes, self-test, etc.
11159 * Invoked with tp->lock held.
11162 __releases(tp->lock) in tg3_restart_hw()
11163 __acquires(tp->lock) in tg3_restart_hw()
11169 netdev_err(tp->dev, in tg3_restart_hw()
11170 "Failed to re-initialize device, aborting\n"); in tg3_restart_hw()
11174 tp->irq_sync = 0; in tg3_restart_hw()
11176 dev_close(tp->dev); in tg3_restart_hw()
11190 if (tp->pcierr_recovery || !netif_running(tp->dev) || in tg3_reset_task()
11191 tp->pdev->error_state != pci_channel_io_normal) { in tg3_reset_task()
11207 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11208 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11217 tp->irq_sync = 0; in tg3_reset_task()
11223 dev_close(tp->dev); in tg3_reset_task()
11240 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11242 if (tp->irq_cnt == 1) in tg3_request_irq()
11243 name = tp->dev->name; in tg3_request_irq()
11245 name = &tnapi->irq_lbl[0]; in tg3_request_irq()
11246 if (tnapi->tx_buffers && tnapi->rx_rcb) in tg3_request_irq()
11248 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11249 else if (tnapi->tx_buffers) in tg3_request_irq()
11251 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11252 else if (tnapi->rx_rcb) in tg3_request_irq()
11254 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11257 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11258 name[IFNAMSIZ-1] = 0; in tg3_request_irq()
11273 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); in tg3_request_irq()
11278 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11279 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11284 return -ENODEV; in tg3_test_interrupt()
11288 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11299 err = request_irq(tnapi->irq_vec, tg3_test_isr, in tg3_test_interrupt()
11300 IRQF_SHARED, dev->name, tnapi); in tg3_test_interrupt()
11304 tnapi->hw_status->status &= ~SD_STATUS_UPDATED; in tg3_test_interrupt()
11307 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11308 tnapi->coal_now); in tg3_test_interrupt()
11313 int_mbox = tr32_mailbox(tnapi->int_mbox); in tg3_test_interrupt()
11323 tnapi->hw_status->status_tag != tnapi->last_tag) in tg3_test_interrupt()
11324 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_test_interrupt()
11331 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11347 return -EIO; in tg3_test_interrupt()
11364 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11365 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11370 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11376 if (err != -EIO) in tg3_test_msi()
11380 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11384 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11386 pci_disable_msi(tp->pdev); in tg3_test_msi()
11389 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11406 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11415 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11416 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11417 tp->fw_needed); in tg3_request_firmware()
11418 return -ENOENT; in tg3_request_firmware()
11421 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11428 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11429 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11430 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11431 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11432 release_firmware(tp->fw); in tg3_request_firmware()
11433 tp->fw = NULL; in tg3_request_firmware()
11434 return -EINVAL; in tg3_request_firmware()
11438 tp->fw_needed = NULL; in tg3_request_firmware()
11444 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11448 * In multiqueue MSI-X mode, the first MSI-X vector in tg3_irq_count()
11452 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11463 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11464 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11465 if (!tp->rxq_cnt) in tg3_enable_msix()
11466 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11467 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11468 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11470 /* Disable multiple TX rings by default. Simple round-robin hardware in tg3_enable_msix()
11474 if (!tp->txq_req) in tg3_enable_msix()
11475 tp->txq_cnt = 1; in tg3_enable_msix()
11477 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11479 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11484 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11487 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11488 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11489 tp->irq_cnt, rc); in tg3_enable_msix()
11490 tp->irq_cnt = rc; in tg3_enable_msix()
11491 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11492 if (tp->txq_cnt) in tg3_enable_msix()
11493 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11496 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11497 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11499 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11500 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11504 if (tp->irq_cnt == 1) in tg3_enable_msix()
11509 if (tp->txq_cnt > 1) in tg3_enable_msix()
11512 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11524 netdev_warn(tp->dev, in tg3_ints_init()
11531 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11536 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11544 tp->irq_cnt = 1; in tg3_ints_init()
11545 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11548 if (tp->irq_cnt == 1) { in tg3_ints_init()
11549 tp->txq_cnt = 1; in tg3_ints_init()
11550 tp->rxq_cnt = 1; in tg3_ints_init()
11551 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11552 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11559 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11561 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11571 struct net_device *dev = tp->dev; in tg3_start()
11593 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11596 for (i--; i >= 0; i--) { in tg3_start()
11597 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11599 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11661 if (dev->features & NETIF_F_LOOPBACK) in tg3_start()
11662 tg3_set_loopback(dev, dev->features); in tg3_start()
11667 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11668 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11669 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11706 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11707 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11708 free_irq(tnapi->irq_vec, tnapi); in tg3_stop()
11723 if (tp->pcierr_recovery) { in tg3_open()
11726 return -EAGAIN; in tg3_open()
11729 if (tp->fw_needed) { in tg3_open()
11733 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11734 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11735 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11736 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11737 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11743 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11746 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11765 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11769 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11779 if (tp->pcierr_recovery) { in tg3_close()
11782 return -EAGAIN; in tg3_close()
11787 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11797 return ((u64)val->high << 32) | ((u64)val->low); in get_stat64()
11802 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11804 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11816 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11818 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11821 return get_stat64(&hw_stats->rx_fcs_errors); in tg3_calc_crc_errors()
11825 estats->member = old_estats->member + \
11826 get_stat64(&hw_stats->member)
11830 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11831 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
11914 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
11915 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
11920 stats->rx_packets = old_stats->rx_packets + in tg3_get_nstats()
11921 get_stat64(&hw_stats->rx_ucast_packets) + in tg3_get_nstats()
11922 get_stat64(&hw_stats->rx_mcast_packets) + in tg3_get_nstats()
11923 get_stat64(&hw_stats->rx_bcast_packets); in tg3_get_nstats()
11925 stats->tx_packets = old_stats->tx_packets + in tg3_get_nstats()
11926 get_stat64(&hw_stats->tx_ucast_packets) + in tg3_get_nstats()
11927 get_stat64(&hw_stats->tx_mcast_packets) + in tg3_get_nstats()
11928 get_stat64(&hw_stats->tx_bcast_packets); in tg3_get_nstats()
11930 stats->rx_bytes = old_stats->rx_bytes + in tg3_get_nstats()
11931 get_stat64(&hw_stats->rx_octets); in tg3_get_nstats()
11932 stats->tx_bytes = old_stats->tx_bytes + in tg3_get_nstats()
11933 get_stat64(&hw_stats->tx_octets); in tg3_get_nstats()
11935 stats->rx_errors = old_stats->rx_errors + in tg3_get_nstats()
11936 get_stat64(&hw_stats->rx_errors); in tg3_get_nstats()
11937 stats->tx_errors = old_stats->tx_errors + in tg3_get_nstats()
11938 get_stat64(&hw_stats->tx_errors) + in tg3_get_nstats()
11939 get_stat64(&hw_stats->tx_mac_errors) + in tg3_get_nstats()
11940 get_stat64(&hw_stats->tx_carrier_sense_errors) + in tg3_get_nstats()
11941 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
11943 stats->multicast = old_stats->multicast + in tg3_get_nstats()
11944 get_stat64(&hw_stats->rx_mcast_packets); in tg3_get_nstats()
11945 stats->collisions = old_stats->collisions + in tg3_get_nstats()
11946 get_stat64(&hw_stats->tx_collisions); in tg3_get_nstats()
11948 stats->rx_length_errors = old_stats->rx_length_errors + in tg3_get_nstats()
11949 get_stat64(&hw_stats->rx_frame_too_long_errors) + in tg3_get_nstats()
11950 get_stat64(&hw_stats->rx_undersize_packets); in tg3_get_nstats()
11952 stats->rx_frame_errors = old_stats->rx_frame_errors + in tg3_get_nstats()
11953 get_stat64(&hw_stats->rx_align_errors); in tg3_get_nstats()
11954 stats->tx_aborted_errors = old_stats->tx_aborted_errors + in tg3_get_nstats()
11955 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
11956 stats->tx_carrier_errors = old_stats->tx_carrier_errors + in tg3_get_nstats()
11957 get_stat64(&hw_stats->tx_carrier_sense_errors); in tg3_get_nstats()
11959 stats->rx_crc_errors = old_stats->rx_crc_errors + in tg3_get_nstats()
11962 stats->rx_missed_errors = old_stats->rx_missed_errors + in tg3_get_nstats()
11963 get_stat64(&hw_stats->rx_discards); in tg3_get_nstats()
11965 /* Aggregate per-queue counters. The per-queue counters are updated in tg3_get_nstats()
11966 * by a single writer, race-free. The result computed by this loop in tg3_get_nstats()
11973 rx_dropped = (unsigned long)(old_stats->rx_dropped); in tg3_get_nstats()
11974 tx_dropped = (unsigned long)(old_stats->tx_dropped); in tg3_get_nstats()
11976 for (i = 0; i < tp->irq_cnt; i++) { in tg3_get_nstats()
11977 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_get_nstats()
11979 rx_dropped += tnapi->rx_dropped; in tg3_get_nstats()
11980 tx_dropped += tnapi->tx_dropped; in tg3_get_nstats()
11983 stats->rx_dropped = rx_dropped; in tg3_get_nstats()
11984 stats->tx_dropped = tx_dropped; in tg3_get_nstats()
11997 regs->version = 0; in tg3_get_regs()
12001 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
12015 return tp->nvram_size; in tg3_get_eeprom_len()
12027 return -EINVAL; in tg3_get_eeprom()
12029 offset = eeprom->offset; in tg3_get_eeprom()
12030 len = eeprom->len; in tg3_get_eeprom()
12031 eeprom->len = 0; in tg3_get_eeprom()
12033 eeprom->magic = TG3_EEPROM_MAGIC; in tg3_get_eeprom()
12051 b_count = 4 - b_offset; in tg3_get_eeprom()
12056 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
12060 len -= b_count; in tg3_get_eeprom()
12062 eeprom->len += b_count; in tg3_get_eeprom()
12065 /* read bytes up to the last 4 byte boundary */ in tg3_get_eeprom()
12066 pd = &data[eeprom->len]; in tg3_get_eeprom()
12067 for (i = 0; i < (len - (len & 3)); i += 4) { in tg3_get_eeprom()
12071 i -= 4; in tg3_get_eeprom()
12072 eeprom->len += i; in tg3_get_eeprom()
12078 eeprom->len += i; in tg3_get_eeprom()
12079 ret = -EINTR; in tg3_get_eeprom()
12085 eeprom->len += i; in tg3_get_eeprom()
12089 pd = &data[eeprom->len]; in tg3_get_eeprom()
12091 b_offset = offset + len - b_count; in tg3_get_eeprom()
12096 eeprom->len += b_count; in tg3_get_eeprom()
12118 eeprom->magic != TG3_EEPROM_MAGIC) in tg3_set_eeprom()
12119 return -EINVAL; in tg3_set_eeprom()
12121 offset = eeprom->offset; in tg3_set_eeprom()
12122 len = eeprom->len; in tg3_set_eeprom()
12126 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12140 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12149 return -ENOMEM; in tg3_set_eeprom()
12153 memcpy(buf+len-4, &end, 4); in tg3_set_eeprom()
12154 memcpy(buf + b_offset, data, eeprom->len); in tg3_set_eeprom()
12173 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_link_ksettings()
12174 return -EAGAIN; in tg3_get_link_ksettings()
12175 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_get_link_ksettings()
12183 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_link_ksettings()
12187 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12193 cmd->base.port = PORT_TP; in tg3_get_link_ksettings()
12196 cmd->base.port = PORT_FIBRE; in tg3_get_link_ksettings()
12198 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, in tg3_get_link_ksettings()
12201 advertising = tp->link_config.advertising; in tg3_get_link_ksettings()
12203 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_link_ksettings()
12204 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12210 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12214 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, in tg3_get_link_ksettings()
12217 if (netif_running(dev) && tp->link_up) { in tg3_get_link_ksettings()
12218 cmd->base.speed = tp->link_config.active_speed; in tg3_get_link_ksettings()
12219 cmd->base.duplex = tp->link_config.active_duplex; in tg3_get_link_ksettings()
12221 cmd->link_modes.lp_advertising, in tg3_get_link_ksettings()
12222 tp->link_config.rmt_adv); in tg3_get_link_ksettings()
12224 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12225 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_link_ksettings()
12226 cmd->base.eth_tp_mdix = ETH_TP_MDI_X; in tg3_get_link_ksettings()
12228 cmd->base.eth_tp_mdix = ETH_TP_MDI; in tg3_get_link_ksettings()
12231 cmd->base.speed = SPEED_UNKNOWN; in tg3_get_link_ksettings()
12232 cmd->base.duplex = DUPLEX_UNKNOWN; in tg3_get_link_ksettings()
12233 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; in tg3_get_link_ksettings()
12235 cmd->base.phy_address = tp->phy_addr; in tg3_get_link_ksettings()
12236 cmd->base.autoneg = tp->link_config.autoneg; in tg3_get_link_ksettings()
12244 u32 speed = cmd->base.speed; in tg3_set_link_ksettings()
12249 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_link_ksettings()
12250 return -EAGAIN; in tg3_set_link_ksettings()
12251 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_link_ksettings()
12255 if (cmd->base.autoneg != AUTONEG_ENABLE && in tg3_set_link_ksettings()
12256 cmd->base.autoneg != AUTONEG_DISABLE) in tg3_set_link_ksettings()
12257 return -EINVAL; in tg3_set_link_ksettings()
12259 if (cmd->base.autoneg == AUTONEG_DISABLE && in tg3_set_link_ksettings()
12260 cmd->base.duplex != DUPLEX_FULL && in tg3_set_link_ksettings()
12261 cmd->base.duplex != DUPLEX_HALF) in tg3_set_link_ksettings()
12262 return -EINVAL; in tg3_set_link_ksettings()
12265 cmd->link_modes.advertising); in tg3_set_link_ksettings()
12267 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12272 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_link_ksettings()
12276 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_link_ksettings()
12286 return -EINVAL; in tg3_set_link_ksettings()
12297 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_link_ksettings()
12299 return -EINVAL; in tg3_set_link_ksettings()
12301 if (cmd->base.duplex != DUPLEX_FULL) in tg3_set_link_ksettings()
12302 return -EINVAL; in tg3_set_link_ksettings()
12306 return -EINVAL; in tg3_set_link_ksettings()
12312 tp->link_config.autoneg = cmd->base.autoneg; in tg3_set_link_ksettings()
12313 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12314 tp->link_config.advertising = (advertising | in tg3_set_link_ksettings()
12316 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_link_ksettings()
12317 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_link_ksettings()
12319 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12320 tp->link_config.speed = speed; in tg3_set_link_ksettings()
12321 tp->link_config.duplex = cmd->base.duplex; in tg3_set_link_ksettings()
12324 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_link_ksettings()
12340 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); in tg3_get_drvinfo()
12341 strscpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12342 strscpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12349 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12350 wol->supported = WAKE_MAGIC; in tg3_get_wol()
12352 wol->supported = 0; in tg3_get_wol()
12353 wol->wolopts = 0; in tg3_get_wol()
12354 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12355 wol->wolopts = WAKE_MAGIC; in tg3_get_wol()
12356 memset(&wol->sopass, 0, sizeof(wol->sopass)); in tg3_get_wol()
12362 struct device *dp = &tp->pdev->dev; in tg3_set_wol()
12364 if (wol->wolopts & ~WAKE_MAGIC) in tg3_set_wol()
12365 return -EINVAL; in tg3_set_wol()
12366 if ((wol->wolopts & WAKE_MAGIC) && in tg3_set_wol()
12368 return -EINVAL; in tg3_set_wol()
12370 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); in tg3_set_wol()
12383 return tp->msg_enable; in tg3_get_msglevel()
12389 tp->msg_enable = value; in tg3_set_msglevel()
12398 return -EAGAIN; in tg3_nway_reset()
12400 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12401 return -EINVAL; in tg3_nway_reset()
12406 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12407 return -EAGAIN; in tg3_nway_reset()
12408 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_nway_reset()
12412 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12413 r = -EINVAL; in tg3_nway_reset()
12417 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12422 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12435 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12437 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12439 ering->rx_jumbo_max_pending = 0; in tg3_get_ringparam()
12441 ering->tx_max_pending = TG3_TX_RING_SIZE - 1; in tg3_get_ringparam()
12443 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12445 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12447 ering->rx_jumbo_pending = 0; in tg3_get_ringparam()
12449 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12461 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12462 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12463 (ering->tx_pending > TG3_TX_RING_SIZE - 1) || in tg3_set_ringparam()
12464 (ering->tx_pending <= MAX_SKB_FRAGS) || in tg3_set_ringparam()
12466 (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) in tg3_set_ringparam()
12467 return -EINVAL; in tg3_set_ringparam()
12477 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12480 tp->rx_pending > 63) in tg3_set_ringparam()
12481 tp->rx_pending = 63; in tg3_set_ringparam()
12484 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12486 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12487 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12491 /* Reset PHY to avoid PHY lock up */ in tg3_set_ringparam()
12514 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12516 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12517 epause->rx_pause = 1; in tg3_get_pauseparam()
12519 epause->rx_pause = 0; in tg3_get_pauseparam()
12521 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12522 epause->tx_pause = 1; in tg3_get_pauseparam()
12524 epause->tx_pause = 0; in tg3_get_pauseparam()
12533 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12539 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_pauseparam()
12542 return -EINVAL; in tg3_set_pauseparam()
12544 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12545 phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause); in tg3_set_pauseparam()
12546 if (epause->rx_pause) { in tg3_set_pauseparam()
12547 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12549 if (epause->tx_pause) { in tg3_set_pauseparam()
12550 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12552 } else if (epause->tx_pause) { in tg3_set_pauseparam()
12553 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12556 if (epause->autoneg) in tg3_set_pauseparam()
12561 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12562 if (phydev->autoneg) { in tg3_set_pauseparam()
12573 if (!epause->autoneg) in tg3_set_pauseparam()
12586 if (epause->autoneg) in tg3_set_pauseparam()
12590 if (epause->rx_pause) in tg3_set_pauseparam()
12591 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12593 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12594 if (epause->tx_pause) in tg3_set_pauseparam()
12595 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12597 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12601 /* Reset PHY to avoid PHY lock up */ in tg3_set_pauseparam()
12615 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12628 return -EOPNOTSUPP; in tg3_get_sset_count()
12638 return -EOPNOTSUPP; in tg3_get_rxnfc()
12640 switch (info->cmd) { in tg3_get_rxnfc()
12642 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12643 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12645 info->data = num_online_cpus(); in tg3_get_rxnfc()
12646 if (info->data > TG3_RSS_MAX_NUM_QS) in tg3_get_rxnfc()
12647 info->data = TG3_RSS_MAX_NUM_QS; in tg3_get_rxnfc()
12653 return -EOPNOTSUPP; in tg3_get_rxnfc()
12679 indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12695 return -EOPNOTSUPP; in tg3_set_rxfh()
12701 tp->rss_ind_tbl[i] = indir[i]; in tg3_set_rxfh()
12722 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12723 channel->max_tx = tp->txq_max; in tg3_get_channels()
12726 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12727 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12729 if (tp->rxq_req) in tg3_get_channels()
12730 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12732 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12734 if (tp->txq_req) in tg3_get_channels()
12735 channel->tx_count = tp->txq_req; in tg3_get_channels()
12737 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12747 return -EOPNOTSUPP; in tg3_set_channels()
12749 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12750 channel->tx_count > tp->txq_max) in tg3_set_channels()
12751 return -EINVAL; in tg3_set_channels()
12753 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12754 tp->txq_req = channel->tx_count; in tg3_set_channels()
12808 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12820 if (tp->hw_stats) in tg3_get_ethtool_stats()
12866 /* The data is in little-endian format in NVRAM. in tg3_vpd_readblock()
12867 * Use the big-endian read routines to preserve in tg3_vpd_readblock()
12875 buf = pci_vpd_alloc(tp->pdev, vpdlen); in tg3_vpd_readblock()
12908 return -EIO; in tg3_test_nvram()
12935 return -EIO; in tg3_test_nvram()
12942 return -EIO; in tg3_test_nvram()
12946 return -ENOMEM; in tg3_test_nvram()
12948 err = -EIO; in tg3_test_nvram()
12980 err = -EIO; in tg3_test_nvram()
13014 err = -EIO; in tg3_test_nvram()
13027 err = -EIO; in tg3_test_nvram()
13043 return -ENOMEM; in tg3_test_nvram()
13061 if (!netif_running(tp->dev)) in tg3_test_link()
13062 return -ENODEV; in tg3_test_link()
13064 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13070 if (tp->link_up) in tg3_test_link()
13077 return -EIO; in tg3_test_link()
13258 /* Determine the read-only value. */ in tg3_test_registers()
13261 /* Write zero to the register, then make sure the read-only bits in tg3_test_registers()
13268 /* Test the read-only and read/write bits. */ in tg3_test_registers()
13273 * make sure the read-only bits are not changed and the in tg3_test_registers()
13280 /* Test the read-only bits. */ in tg3_test_registers()
13295 netdev_err(tp->dev, in tg3_test_registers()
13298 return -EIO; in tg3_test_registers()
13314 return -EIO; in tg3_do_mem_test()
13424 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13426 tnapi = &tp->napi[0]; in tg3_run_loopback()
13427 rnapi = &tp->napi[0]; in tg3_run_loopback()
13428 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13430 rnapi = &tp->napi[1]; in tg3_run_loopback()
13432 tnapi = &tp->napi[1]; in tg3_run_loopback()
13434 coal_now = tnapi->coal_now | rnapi->coal_now; in tg3_run_loopback()
13436 err = -EIO; in tg3_run_loopback()
13439 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13441 return -ENOMEM; in tg3_run_loopback()
13444 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13459 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); in tg3_run_loopback()
13463 iph->tot_len = htons((u16)(mss + hdr_len)); in tg3_run_loopback()
13474 th->check = 0; in tg3_run_loopback()
13505 map = dma_map_single(&tp->pdev->dev, skb->data, tx_len, DMA_TO_DEVICE); in tg3_run_loopback()
13506 if (dma_mapping_error(&tp->pdev->dev, map)) { in tg3_run_loopback()
13508 return -EIO; in tg3_run_loopback()
13511 val = tnapi->tx_prod; in tg3_run_loopback()
13512 tnapi->tx_buffers[val].skb = skb; in tg3_run_loopback()
13513 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); in tg3_run_loopback()
13515 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13516 rnapi->coal_now); in tg3_run_loopback()
13520 rx_start_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13525 tnapi->tx_buffers[val].skb = NULL; in tg3_run_loopback()
13527 return -EIO; in tg3_run_loopback()
13530 tnapi->tx_prod++; in tg3_run_loopback()
13535 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); in tg3_run_loopback()
13536 tr32_mailbox(tnapi->prodmbox); in tg3_run_loopback()
13542 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13547 tx_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_run_loopback()
13548 rx_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13549 if ((tx_idx == tnapi->tx_prod) && in tg3_run_loopback()
13554 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); in tg3_run_loopback()
13557 if (tx_idx != tnapi->tx_prod) in tg3_run_loopback()
13565 desc = &rnapi->rx_rcb[rx_start_idx++]; in tg3_run_loopback()
13566 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_run_loopback()
13567 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_run_loopback()
13569 if ((desc->err_vlan & RXD_ERR_MASK) != 0 && in tg3_run_loopback()
13570 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) in tg3_run_loopback()
13573 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) in tg3_run_loopback()
13574 - ETH_FCS_LEN; in tg3_run_loopback()
13580 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { in tg3_run_loopback()
13587 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_run_loopback()
13588 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_run_loopback()
13594 rx_data = tpr->rx_std_buffers[desc_idx].data; in tg3_run_loopback()
13595 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], in tg3_run_loopback()
13598 rx_data = tpr->rx_jmb_buffers[desc_idx].data; in tg3_run_loopback()
13599 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], in tg3_run_loopback()
13604 dma_sync_single_for_cpu(&tp->pdev->dev, map, rx_len, in tg3_run_loopback()
13631 int err = -EIO; in tg3_test_loopback()
13635 if (tp->dma_limit) in tg3_test_loopback()
13636 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13638 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13639 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13641 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13667 /* HW errata - mac loopback fails in some cases on 5780. in tg3_test_loopback()
13686 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13711 /* All link indications report up, but the hardware in tg3_test_loopback()
13730 /* Re-enable gphy autopowerdown. */ in tg3_test_loopback()
13731 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13736 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0; in tg3_test_loopback()
13739 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13748 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; in tg3_self_test()
13750 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13752 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13762 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13766 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13769 if (etest->flags & ETH_TEST_FL_OFFLINE) { in tg3_self_test()
13787 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13791 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13796 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13801 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; in tg3_self_test()
13804 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13809 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13828 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13839 return -EOPNOTSUPP; in tg3_hwtstamp_set()
13841 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) in tg3_hwtstamp_set()
13842 return -EFAULT; in tg3_hwtstamp_set()
13846 return -ERANGE; in tg3_hwtstamp_set()
13850 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13853 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13857 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13861 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13865 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13869 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13873 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13877 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13881 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13885 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13889 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13893 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13897 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13901 return -ERANGE; in tg3_hwtstamp_set()
13904 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
13906 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
13913 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_set()
13914 -EFAULT : 0; in tg3_hwtstamp_set()
13923 return -EOPNOTSUPP; in tg3_hwtstamp_get()
13929 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
13971 return -ERANGE; in tg3_hwtstamp_get()
13974 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_get()
13975 -EFAULT : 0; in tg3_hwtstamp_get()
13986 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
13987 return -EAGAIN; in tg3_ioctl()
13988 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_ioctl()
13994 data->phy_id = tp->phy_addr; in tg3_ioctl()
14000 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14004 return -EAGAIN; in tg3_ioctl()
14006 spin_lock_bh(&tp->lock); in tg3_ioctl()
14007 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14008 data->reg_num & 0x1f, &mii_regval); in tg3_ioctl()
14009 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14011 data->val_out = mii_regval; in tg3_ioctl()
14017 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14021 return -EAGAIN; in tg3_ioctl()
14023 spin_lock_bh(&tp->lock); in tg3_ioctl()
14024 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14025 data->reg_num & 0x1f, data->val_in); in tg3_ioctl()
14026 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14040 return -EOPNOTSUPP; in tg3_ioctl()
14050 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14070 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || in tg3_set_coalesce()
14071 (!ec->rx_coalesce_usecs) || in tg3_set_coalesce()
14072 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || in tg3_set_coalesce()
14073 (!ec->tx_coalesce_usecs) || in tg3_set_coalesce()
14074 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || in tg3_set_coalesce()
14075 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || in tg3_set_coalesce()
14076 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || in tg3_set_coalesce()
14077 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || in tg3_set_coalesce()
14078 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || in tg3_set_coalesce()
14079 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || in tg3_set_coalesce()
14080 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || in tg3_set_coalesce()
14081 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) in tg3_set_coalesce()
14082 return -EINVAL; in tg3_set_coalesce()
14085 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14086 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14087 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14088 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14089 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14090 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14091 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14092 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14093 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14097 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14107 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14108 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14109 return -EOPNOTSUPP; in tg3_set_eee()
14112 if (edata->advertised != tp->eee.advertised) { in tg3_set_eee()
14113 netdev_warn(tp->dev, in tg3_set_eee()
14115 return -EINVAL; in tg3_set_eee()
14118 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) { in tg3_set_eee()
14119 netdev_warn(tp->dev, in tg3_set_eee()
14122 return -EINVAL; in tg3_set_eee()
14125 tp->eee = *edata; in tg3_set_eee()
14127 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14130 if (netif_running(tp->dev)) { in tg3_set_eee()
14144 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14145 netdev_warn(tp->dev, in tg3_get_eee()
14147 return -EOPNOTSUPP; in tg3_get_eee()
14150 *edata = tp->eee; in tg3_get_eee()
14201 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14202 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) { in tg3_get_stats64()
14203 *stats = tp->net_stats_prev; in tg3_get_stats64()
14204 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14209 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14227 dev->mtu = new_mtu; in tg3_set_mtu()
14253 * device is up'd. in tg3_change_mtu()
14313 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14330 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14340 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14359 * 16-bit value at offset 0xf2. The tg3_nvram_read() in tg3_get_nvram_size()
14363 * want will always reside in the lower 16-bits. in tg3_get_nvram_size()
14366 * opposite the endianness of the CPU. The 16-bit in tg3_get_nvram_size()
14369 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14373 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14392 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14393 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14397 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14398 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14401 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14402 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14406 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14407 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14411 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14412 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14416 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14417 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14421 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14422 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14431 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14434 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14437 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14440 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14443 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14446 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14449 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14467 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14471 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14478 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14488 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14513 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14516 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14519 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14522 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14525 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14531 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14534 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14536 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14540 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14544 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14562 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14564 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14573 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14576 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14581 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14584 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14611 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14615 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14625 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14628 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14633 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14640 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14646 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14652 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14658 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14666 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14668 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14680 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14682 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14694 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14702 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14706 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14710 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14717 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14723 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14726 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14729 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14739 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14753 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14755 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14767 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14777 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14780 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14794 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14805 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14808 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14818 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14841 tp->nvram_pagesize = 4096; in tg3_get_5720_nvram_info()
14842 tp->nvram_jedecnum = JEDEC_MACRONIX; in tg3_get_5720_nvram_info()
14847 tp->nvram_size = in tg3_get_5720_nvram_info()
14871 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14877 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14879 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14893 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14901 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14906 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14910 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14914 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14936 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
14945 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14951 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14957 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14961 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14971 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
15014 netdev_warn(tp->dev, in tg3_nvram_init()
15021 tp->nvram_size = 0; in tg3_nvram_init()
15047 if (tp->nvram_size == 0) in tg3_nvram_init()
15136 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15138 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15148 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15149 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15166 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15179 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15212 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15215 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15217 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15229 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15233 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15237 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15244 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15249 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15252 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15257 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15263 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15267 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15269 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15277 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15278 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15281 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15285 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15287 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15288 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15305 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15312 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15316 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15318 /* serdes signal pre-emphasis in register 0x590 set by */ in tg3_get_eeprom_hw_cfg()
15321 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15327 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15338 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15340 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15351 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15355 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15358 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15391 return -EBUSY; in tg3_ape_otp_read()
15402 /* Wait for up to 1 ms for command to execute. */ in tg3_issue_otp_command()
15410 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; in tg3_issue_otp_command()
15414 * configuration is a 32-bit value that straddles the alignment boundary.
15415 * We do two 32-bit reads and then shift and merge the results.
15445 u32 adv = ADVERTISED_Autoneg; in tg3_phy_init_link_config() local
15447 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15448 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15449 adv |= ADVERTISED_1000baseT_Half; in tg3_phy_init_link_config()
15450 adv |= ADVERTISED_1000baseT_Full; in tg3_phy_init_link_config()
15453 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15454 adv |= ADVERTISED_100baseT_Half | in tg3_phy_init_link_config()
15460 adv |= ADVERTISED_FIBRE; in tg3_phy_init_link_config()
15462 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15463 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15464 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15465 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15466 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15467 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15469 tp->old_link = -1; in tg3_phy_init_link_config()
15480 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15483 switch (tp->pci_fn) { in tg3_phy_probe()
15485 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15488 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15491 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15494 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15500 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15501 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15502 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15517 * to either the hard-coded table based PHY_ID and failing in tg3_phy_probe()
15531 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15533 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15535 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15537 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15538 /* Do nothing, phy ID already set up in in tg3_phy_probe()
15549 tp->phy_id = p->phy_id; in tg3_phy_probe()
15558 return -ENODEV; in tg3_phy_probe()
15561 if (!tp->phy_id || in tg3_phy_probe()
15562 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15563 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15567 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15576 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15578 tp->eee.supported = SUPPORTED_100baseT_Full | in tg3_phy_probe()
15580 tp->eee.advertised = ADVERTISED_100baseT_Full | in tg3_phy_probe()
15582 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15583 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15584 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15589 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15590 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15607 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15608 tp->link_config.flowctrl); in tg3_phy_probe()
15616 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15650 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15651 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, vpd_data + i); in tg3_read_vpd()
15662 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15666 if (tp->board_part_number[0]) in tg3_read_vpd()
15671 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15672 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15673 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15674 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15675 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15679 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15680 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15681 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15682 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15683 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15684 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15685 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15686 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15690 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15691 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15692 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15693 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15694 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15695 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15696 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15697 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15698 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15699 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15700 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15701 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15705 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15706 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15707 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15708 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15709 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15710 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15711 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15712 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15716 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15719 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15759 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15762 if (TG3_VER_SIZE - dst_off < 16 || in tg3_read_bc_ver()
15766 offset = offset + ver_offset - start; in tg3_read_bc_ver()
15772 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15783 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15801 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15808 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15848 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15849 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15853 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15854 if (offset < TG3_VER_SIZE - 1) in tg3_read_sb_ver()
15855 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15879 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15887 offset += val - start; in tg3_read_mgmtfw_ver()
15889 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15891 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15892 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
15901 if (vlen > TG3_VER_SIZE - sizeof(v)) { in tg3_read_mgmtfw_ver()
15902 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
15906 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
15937 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
15942 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
15944 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
15972 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
15973 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
15982 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
15986 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
16011 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
16034 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16037 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16038 if (peer && peer != tp->pdev) in tg3_find_peer()
16042 /* 5704 can be configured in single-port mode, set peer to in tg3_find_peer()
16043 * tp->pdev in that case. in tg3_find_peer()
16046 peer = tp->pdev; in tg3_find_peer()
16061 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16070 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16071 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16072 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16073 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16074 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16075 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16076 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16077 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16078 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16079 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16080 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16082 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16083 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16084 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16085 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16086 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16087 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16088 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16089 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16090 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16091 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16096 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16103 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16106 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16154 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16157 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) { in tg3_10_100_only_device()
16159 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100) in tg3_10_100_only_device()
16184 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16186 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16188 /* Important! -- Make sure register accesses are byteswapped in tg3_get_invariants()
16193 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16195 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16197 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16198 tp->misc_host_ctrl); in tg3_get_invariants()
16208 * will drive special cycles with non-zero data during the in tg3_get_invariants()
16211 * non-zero address during special cycles. However, only in tg3_get_invariants()
16212 * these ICH bridges are known to drive non-zero addresses in tg3_get_invariants()
16239 while (pci_id->vendor != 0) { in tg3_get_invariants()
16240 bridge = pci_get_device(pci_id->vendor, pci_id->device, in tg3_get_invariants()
16246 if (pci_id->rev != PCI_ANY_ID) { in tg3_get_invariants()
16247 if (bridge->revision > pci_id->rev) in tg3_get_invariants()
16250 if (bridge->subordinate && in tg3_get_invariants()
16251 (bridge->subordinate->number == in tg3_get_invariants()
16252 tp->pdev->bus->number)) { in tg3_get_invariants()
16272 while (pci_id->vendor != 0) { in tg3_get_invariants()
16273 bridge = pci_get_device(pci_id->vendor, in tg3_get_invariants()
16274 pci_id->device, in tg3_get_invariants()
16280 if (bridge->subordinate && in tg3_get_invariants()
16281 (bridge->subordinate->number <= in tg3_get_invariants()
16282 tp->pdev->bus->number) && in tg3_get_invariants()
16283 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16284 tp->pdev->bus->number)) { in tg3_get_invariants()
16293 * DMA addresses > 40-bit. This bridge may have other additional in tg3_get_invariants()
16294 * 57xx devices behind it in some 4-port NIC designs for example. in tg3_get_invariants()
16295 * Any tg3 device found behind the bridge will also need the 40-bit in tg3_get_invariants()
16300 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16308 if (bridge && bridge->subordinate && in tg3_get_invariants()
16309 (bridge->subordinate->number <= in tg3_get_invariants()
16310 tp->pdev->bus->number) && in tg3_get_invariants()
16311 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16312 tp->pdev->bus->number)) { in tg3_get_invariants()
16322 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16344 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16346 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16362 tp->fw_needed = NULL; in tg3_get_invariants()
16366 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16369 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16371 tp->irq_max = 1; in tg3_get_invariants()
16379 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16389 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16393 tp->txq_max = 1; in tg3_get_invariants()
16394 tp->rxq_max = 1; in tg3_get_invariants()
16395 if (tp->irq_max > 1) { in tg3_get_invariants()
16396 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16401 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16409 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16426 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16429 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16434 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16456 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16457 if (!tp->pcix_cap) { in tg3_get_invariants()
16458 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16459 "Cannot find PCI-X capability, aborting\n"); in tg3_get_invariants()
16460 return -EIO; in tg3_get_invariants()
16477 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16478 &tp->pci_cacheline_sz); in tg3_get_invariants()
16479 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16480 &tp->pci_lat_timer); in tg3_get_invariants()
16482 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16483 tp->pci_lat_timer = 64; in tg3_get_invariants()
16484 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16485 tp->pci_lat_timer); in tg3_get_invariants()
16488 /* Important! -- It is critical that the PCI-X hw workaround in tg3_get_invariants()
16497 /* If we are in PCI-X mode, enable register write workaround. in tg3_get_invariants()
16511 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16512 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16516 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16517 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16521 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16523 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16532 /* Chip-specific fixup from Broadcom driver */ in tg3_get_invariants()
16536 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16540 tp->read32 = tg3_read32; in tg3_get_invariants()
16541 tp->write32 = tg3_write32; in tg3_get_invariants()
16542 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16543 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16544 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16545 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16549 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16560 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16564 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16566 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16570 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16571 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16572 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16573 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16574 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16575 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16577 iounmap(tp->regs); in tg3_get_invariants()
16578 tp->regs = NULL; in tg3_get_invariants()
16580 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16582 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16585 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16586 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16587 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16588 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16591 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16605 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16609 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16610 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16612 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16622 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16624 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16629 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16630 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16646 tp->fw_needed = NULL; in tg3_get_invariants()
16656 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16660 tp->ape_hb_interval = in tg3_get_invariants()
16664 /* Set up tp->grc_local_ctrl before calling in tg3_get_invariants()
16669 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16672 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16675 * are no pull-up resistors on unused GPIO pins. in tg3_get_invariants()
16678 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16683 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16685 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16686 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16688 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16691 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16696 tp->grc_local_ctrl |= in tg3_get_invariants()
16705 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16719 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16726 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16727 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16728 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16732 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16734 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16737 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16745 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16746 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16747 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16748 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16749 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16751 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16756 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16757 if (tp->phy_otp == 0) in tg3_get_invariants()
16758 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16762 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16764 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16766 tp->coalesce_mode = 0; in tg3_get_invariants()
16769 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16776 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16777 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16800 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16810 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16824 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16840 tp->fw_needed = NULL; in tg3_get_invariants()
16854 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16857 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16858 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16859 tp->misc_host_ctrl); in tg3_get_invariants()
16864 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16866 tp->mac_mode = 0; in tg3_get_invariants()
16869 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16873 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16881 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16882 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16885 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16887 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16903 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
16905 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
16906 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16911 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
16919 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
16920 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
16923 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
16925 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
16929 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
16930 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
16931 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
16933 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
16941 tp->rx_std_max_post = 8; in tg3_get_invariants()
16944 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
16956 if (!eth_platform_get_mac_address(&tp->pdev->dev, addr)) in tg3_get_device_address()
16960 err = ssb_gige_get_macaddr(tp->pdev, addr); in tg3_get_device_address()
16975 if (tp->pci_fn & 1) in tg3_get_device_address()
16977 if (tp->pci_fn > 1) in tg3_get_device_address()
17020 return -EINVAL; in tg3_get_device_address()
17033 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17066 * when a device tries to burst across a cache-line boundary. in tg3_calc_dma_bndry()
17069 * Unfortunately, for PCI-E there are only limited in tg3_calc_dma_bndry()
17070 * write-side controls for this, and thus for reads in tg3_calc_dma_bndry()
17200 * Broadcom noted the GRC reset will also reset all sub-components. in tg3_do_test_dma()
17219 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17221 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17223 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17230 ret = -ENODEV; in tg3_do_test_dma()
17262 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17265 ret = -ENOMEM; in tg3_test_dma()
17269 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17272 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17279 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17283 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17285 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17298 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17300 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17305 tp->dma_rwctrl |= in tg3_test_dma()
17311 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17314 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17316 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17320 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17324 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17329 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17339 * on those chips to enable a PCI-X workaround. in tg3_test_dma()
17341 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17344 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17354 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17355 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17356 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17367 dev_err(&tp->pdev->dev, in tg3_test_dma()
17376 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17386 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17388 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17389 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17390 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17393 dev_err(&tp->pdev->dev, in tg3_test_dma()
17396 ret = -ENODEV; in tg3_test_dma()
17407 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17414 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17415 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17418 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17421 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17425 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17433 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17435 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17437 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17440 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17442 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17444 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17447 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17449 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17451 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17454 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17456 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17460 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17462 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17464 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17467 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17469 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17471 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17474 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17476 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17478 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17482 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17483 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17488 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17548 strcat(str, ":32-bit"); in tg3_bus_string()
17550 strcat(str, ":64-bit"); in tg3_bus_string()
17556 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17559 ec->cmd = ETHTOOL_GCOALESCE; in tg3_init_coal()
17560 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; in tg3_init_coal()
17561 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; in tg3_init_coal()
17562 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; in tg3_init_coal()
17563 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; in tg3_init_coal()
17564 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; in tg3_init_coal()
17565 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; in tg3_init_coal()
17566 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; in tg3_init_coal()
17567 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; in tg3_init_coal()
17568 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; in tg3_init_coal()
17570 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17572 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17573 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17574 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17575 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17579 ec->rx_coalesce_usecs_irq = 0; in tg3_init_coal()
17580 ec->tx_coalesce_usecs_irq = 0; in tg3_init_coal()
17581 ec->stats_block_coalesce_usecs = 0; in tg3_init_coal()
17599 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in tg3_init_one()
17605 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); in tg3_init_one()
17613 err = -ENOMEM; in tg3_init_one()
17617 SET_NETDEV_DEV(dev, &pdev->dev); in tg3_init_one()
17620 tp->pdev = pdev; in tg3_init_one()
17621 tp->dev = dev; in tg3_init_one()
17622 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17623 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17624 tp->irq_sync = 1; in tg3_init_one()
17625 tp->pcierr_recovery = false; in tg3_init_one()
17628 tp->msg_enable = tg3_debug; in tg3_init_one()
17630 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17650 tp->misc_host_ctrl = in tg3_init_one()
17656 /* The NONFRM (non-frame) byte/word swap controls take effect in tg3_init_one()
17660 * are running in big-endian mode. in tg3_init_one()
17662 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17665 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17667 spin_lock_init(&tp->lock); in tg3_init_one()
17668 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17669 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17671 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17672 if (!tp->regs) { in tg3_init_one()
17673 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); in tg3_init_one()
17674 err = -ENOMEM; in tg3_init_one()
17678 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17679 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17680 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17681 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17682 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17683 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17684 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17685 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17686 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17687 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17688 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17689 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17690 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17691 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17692 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17694 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17695 if (!tp->aperegs) { in tg3_init_one()
17696 dev_err(&pdev->dev, in tg3_init_one()
17698 err = -ENOMEM; in tg3_init_one()
17703 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17704 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17706 dev->ethtool_ops = &tg3_ethtool_ops; in tg3_init_one()
17707 dev->watchdog_timeo = TG3_TX_TIMEOUT; in tg3_init_one()
17708 dev->netdev_ops = &tg3_netdev_ops; in tg3_init_one()
17709 dev->irq = pdev->irq; in tg3_init_one()
17713 dev_err(&pdev->dev, in tg3_init_one()
17719 * device behind the EPB cannot support DMA addresses > 40-bit. in tg3_init_one()
17720 * On 64-bit systems with IOMMU, use 40-bit dma_mask. in tg3_init_one()
17721 * On 64-bit systems without IOMMU, use 64-bit dma_mask and in tg3_init_one()
17739 err = dma_set_mask(&pdev->dev, dma_mask); in tg3_init_one()
17742 err = dma_set_coherent_mask(&pdev->dev, in tg3_init_one()
17745 dev_err(&pdev->dev, "Unable to obtain 64 bit " in tg3_init_one()
17752 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in tg3_init_one()
17754 dev_err(&pdev->dev, in tg3_init_one()
17793 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX | in tg3_init_one()
17795 dev->vlan_features |= features; in tg3_init_one()
17799 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY in tg3_init_one()
17807 dev->hw_features |= features; in tg3_init_one()
17808 dev->priv_flags |= IFF_UNICAST_FLT; in tg3_init_one()
17810 /* MTU range: 60 - 9000 or 1500, depending on hardware */ in tg3_init_one()
17811 dev->min_mtu = TG3_MIN_MTU; in tg3_init_one()
17812 dev->max_mtu = TG3_MAX_MTU(tp); in tg3_init_one()
17818 tp->rx_pending = 63; in tg3_init_one()
17823 dev_err(&pdev->dev, in tg3_init_one()
17832 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17833 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17835 tnapi->tp = tp; in tg3_init_one()
17836 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; in tg3_init_one()
17838 tnapi->int_mbox = intmbx; in tg3_init_one()
17841 tnapi->consmbox = rcvmbx; in tg3_init_one()
17842 tnapi->prodmbox = sndmbx; in tg3_init_one()
17845 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); in tg3_init_one()
17847 tnapi->coal_now = HOSTCC_MODE_NOW; in tg3_init_one()
17865 sndmbx -= 0x4; in tg3_init_one()
17885 dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); in tg3_init_one()
17904 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); in tg3_init_one()
17910 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
17911 &tp->pdev->dev); in tg3_init_one()
17912 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
17913 tp->ptp_clock = NULL; in tg3_init_one()
17917 tp->board_part_number, in tg3_init_one()
17920 dev->dev_addr); in tg3_init_one()
17922 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { in tg3_init_one()
17925 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
17926 ethtype = "10/100Base-TX"; in tg3_init_one()
17927 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
17928 ethtype = "1000Base-SX"; in tg3_init_one()
17930 ethtype = "10/100/1000Base-T"; in tg3_init_one()
17935 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
17936 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
17940 (dev->features & NETIF_F_RXCSUM) != 0, in tg3_init_one()
17942 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
17945 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", in tg3_init_one()
17946 tp->dma_rwctrl, in tg3_init_one()
17947 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : in tg3_init_one()
17948 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); in tg3_init_one()
17955 if (tp->aperegs) { in tg3_init_one()
17956 iounmap(tp->aperegs); in tg3_init_one()
17957 tp->aperegs = NULL; in tg3_init_one()
17961 if (tp->regs) { in tg3_init_one()
17962 iounmap(tp->regs); in tg3_init_one()
17963 tp->regs = NULL; in tg3_init_one()
17987 release_firmware(tp->fw); in tg3_remove_one()
17997 if (tp->aperegs) { in tg3_remove_one()
17998 iounmap(tp->aperegs); in tg3_remove_one()
17999 tp->aperegs = NULL; in tg3_remove_one()
18001 if (tp->regs) { in tg3_remove_one()
18002 iounmap(tp->regs); in tg3_remove_one()
18003 tp->regs = NULL; in tg3_remove_one()
18087 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18132 * tg3_io_error_detected - called when PCI error is detected
18154 if (!netdev || tp->pcierr_recovery || !netif_running(netdev)) in tg3_io_error_detected()
18159 tp->pcierr_recovery = true; in tg3_io_error_detected()
18169 /* Clean up software state, even if MMIO is blocked */ in tg3_io_error_detected()
18191 * tg3_io_slot_reset - called after the pci bus has been reset.
18194 * Restart the card from scratch, as if from a cold-boot.
18197 * set up identically to what it was at cold boot.
18209 dev_err(&pdev->dev, in tg3_io_slot_reset()
18210 "Cannot re-enable PCI device after reset.\n"); in tg3_io_slot_reset()
18240 * tg3_io_resume - called when traffic can start flowing again.
18278 tp->pcierr_recovery = false; in tg3_io_resume()