Lines Matching +full:tp +full:- +full:link
7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
93 #define tg3_flag(tp, flag) \ argument
94 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define tg3_flag_set(tp, flag) \ argument
96 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
97 #define tg3_flag_clear(tp, flag) \ argument
98 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
124 * and dev->tx_timeout() should be called to fix the problem
131 #define TG3_MAX_MTU(tp) \ argument
132 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
138 #define TG3_RX_STD_RING_SIZE(tp) \ argument
139 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
142 #define TG3_RX_JMB_RING_SIZE(tp) \ argument
143 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
147 /* Do not place this n-ring entries value into the tp struct itself,
151 * replace things like '% foo' with '& (foo - 1)'.
155 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
157 #define TG3_RX_STD_RING_BYTES(tp) \ argument
158 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
159 #define TG3_RX_JMB_RING_BYTES(tp) \ argument
160 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
161 #define TG3_RX_RCB_RING_BYTES(tp) \ argument
162 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
165 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
177 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \ argument
178 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
180 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \ argument
181 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
196 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD argument
198 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh) argument
202 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset) argument
204 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD) argument
208 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
214 #define TG3_MAX_UCAST_ADDR(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 3) argument
215 #define TG3_UCAST_ADDR_IDX(tp) (tg3_flag((tp), ENABLE_ASF) ? 2 : 1) argument
233 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
459 [TG3_LINK_TEST] = { "link test (online) " },
471 static void tg3_write32(struct tg3 *tp, u32 off, u32 val) in tg3_write32() argument
473 writel(val, tp->regs + off); in tg3_write32()
476 static u32 tg3_read32(struct tg3 *tp, u32 off) in tg3_read32() argument
478 return readl(tp->regs + off); in tg3_read32()
481 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val) in tg3_ape_write32() argument
483 writel(val, tp->aperegs + off); in tg3_ape_write32()
486 static u32 tg3_ape_read32(struct tg3 *tp, u32 off) in tg3_ape_read32() argument
488 return readl(tp->aperegs + off); in tg3_ape_read32()
491 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) in tg3_write_indirect_reg32() argument
495 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
496 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_write_indirect_reg32()
497 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_reg32()
498 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_reg32()
501 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val) in tg3_write_flush_reg32() argument
503 writel(val, tp->regs + off); in tg3_write_flush_reg32()
504 readl(tp->regs + off); in tg3_write_flush_reg32()
507 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off) in tg3_read_indirect_reg32() argument
512 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
513 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off); in tg3_read_indirect_reg32()
514 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_reg32()
515 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_reg32()
519 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val) in tg3_write_indirect_mbox() argument
524 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX + in tg3_write_indirect_mbox()
529 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX + in tg3_write_indirect_mbox()
534 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
535 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_write_indirect_mbox()
536 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val); in tg3_write_indirect_mbox()
537 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_indirect_mbox()
544 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL, in tg3_write_indirect_mbox()
545 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT); in tg3_write_indirect_mbox()
549 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off) in tg3_read_indirect_mbox() argument
554 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
555 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600); in tg3_read_indirect_mbox()
556 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val); in tg3_read_indirect_mbox()
557 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_indirect_mbox()
566 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait) in _tw32_flush() argument
568 if (tg3_flag(tp, PCIX_TARGET_HWBUG) || tg3_flag(tp, ICH_WORKAROUND)) in _tw32_flush()
569 /* Non-posted methods */ in _tw32_flush()
570 tp->write32(tp, off, val); in _tw32_flush()
573 tg3_write32(tp, off, val); in _tw32_flush()
576 tp->read32(tp, off); in _tw32_flush()
585 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val) in tw32_mailbox_flush() argument
587 tp->write32_mbox(tp, off, val); in tw32_mailbox_flush()
588 if (tg3_flag(tp, FLUSH_POSTED_WRITES) || in tw32_mailbox_flush()
589 (!tg3_flag(tp, MBOX_WRITE_REORDER) && in tw32_mailbox_flush()
590 !tg3_flag(tp, ICH_WORKAROUND))) in tw32_mailbox_flush()
591 tp->read32_mbox(tp, off); in tw32_mailbox_flush()
594 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val) in tg3_write32_tx_mbox() argument
596 void __iomem *mbox = tp->regs + off; in tg3_write32_tx_mbox()
598 if (tg3_flag(tp, TXD_MBOX_HWBUG)) in tg3_write32_tx_mbox()
600 if (tg3_flag(tp, MBOX_WRITE_REORDER) || in tg3_write32_tx_mbox()
601 tg3_flag(tp, FLUSH_POSTED_WRITES)) in tg3_write32_tx_mbox()
605 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off) in tg3_read32_mbox_5906() argument
607 return readl(tp->regs + off + GRCMBOX_BASE); in tg3_read32_mbox_5906()
610 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val) in tg3_write32_mbox_5906() argument
612 writel(val, tp->regs + off + GRCMBOX_BASE); in tg3_write32_mbox_5906()
615 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
616 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
617 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
618 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
619 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
621 #define tw32(reg, val) tp->write32(tp, reg, val)
622 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
623 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
624 #define tr32(reg) tp->read32(tp, reg)
626 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val) in tg3_write_mem() argument
630 if (tg3_asic_rev(tp) == ASIC_REV_5906 && in tg3_write_mem()
634 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_write_mem()
635 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_write_mem()
636 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_write_mem()
637 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_write_mem()
640 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_write_mem()
648 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_write_mem()
651 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val) in tg3_read_mem() argument
655 if (tg3_asic_rev(tp) == ASIC_REV_5906 && in tg3_read_mem()
661 spin_lock_irqsave(&tp->indirect_lock, flags); in tg3_read_mem()
662 if (tg3_flag(tp, SRAM_USE_CONFIG)) { in tg3_read_mem()
663 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off); in tg3_read_mem()
664 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_read_mem()
667 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_read_mem()
675 spin_unlock_irqrestore(&tp->indirect_lock, flags); in tg3_read_mem()
678 static void tg3_ape_lock_init(struct tg3 *tp) in tg3_ape_lock_init() argument
683 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_lock_init()
698 if (!tp->pci_fn) in tg3_ape_lock_init()
701 bit = 1 << tp->pci_fn; in tg3_ape_lock_init()
703 tg3_ape_write32(tp, regbase + 4 * i, bit); in tg3_ape_lock_init()
708 static int tg3_ape_lock(struct tg3 *tp, int locknum) in tg3_ape_lock() argument
714 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_lock()
719 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_lock()
724 if (!tp->pci_fn) in tg3_ape_lock()
727 bit = 1 << tp->pci_fn; in tg3_ape_lock()
736 return -EINVAL; in tg3_ape_lock()
739 if (tg3_asic_rev(tp) == ASIC_REV_5761) { in tg3_ape_lock()
749 tg3_ape_write32(tp, req + off, bit); in tg3_ape_lock()
753 status = tg3_ape_read32(tp, gnt + off); in tg3_ape_lock()
756 if (pci_channel_offline(tp->pdev)) in tg3_ape_lock()
764 tg3_ape_write32(tp, gnt + off, bit); in tg3_ape_lock()
765 ret = -EBUSY; in tg3_ape_lock()
771 static void tg3_ape_unlock(struct tg3 *tp, int locknum) in tg3_ape_unlock() argument
775 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_unlock()
780 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_unlock()
785 if (!tp->pci_fn) in tg3_ape_unlock()
788 bit = 1 << tp->pci_fn; in tg3_ape_unlock()
800 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_ape_unlock()
805 tg3_ape_write32(tp, gnt + 4 * locknum, bit); in tg3_ape_unlock()
808 static int tg3_ape_event_lock(struct tg3 *tp, u32 timeout_us) in tg3_ape_event_lock() argument
813 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM)) in tg3_ape_event_lock()
814 return -EBUSY; in tg3_ape_event_lock()
816 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); in tg3_ape_event_lock()
820 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_event_lock()
823 timeout_us -= (timeout_us > 10) ? 10 : timeout_us; in tg3_ape_event_lock()
826 return timeout_us ? 0 : -EBUSY; in tg3_ape_event_lock()
830 static int tg3_ape_wait_for_event(struct tg3 *tp, u32 timeout_us) in tg3_ape_wait_for_event() argument
835 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS); in tg3_ape_wait_for_event()
846 static int tg3_ape_scratchpad_read(struct tg3 *tp, u32 *data, u32 base_off, in tg3_ape_scratchpad_read() argument
852 if (!tg3_flag(tp, APE_HAS_NCSI)) in tg3_ape_scratchpad_read()
855 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_ape_scratchpad_read()
857 return -ENODEV; in tg3_ape_scratchpad_read()
859 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_scratchpad_read()
861 return -EAGAIN; in tg3_ape_scratchpad_read()
863 bufoff = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_OFF) + in tg3_ape_scratchpad_read()
866 maxlen = tg3_ape_read32(tp, TG3_APE_SEG_MSG_BUF_LEN); in tg3_ape_scratchpad_read()
873 len -= length; in tg3_ape_scratchpad_read()
875 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_scratchpad_read()
877 return -EAGAIN; in tg3_ape_scratchpad_read()
880 err = tg3_ape_event_lock(tp, 1000); in tg3_ape_scratchpad_read()
887 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, apedata); in tg3_ape_scratchpad_read()
889 tg3_ape_write32(tp, bufoff, base_off); in tg3_ape_scratchpad_read()
890 tg3_ape_write32(tp, bufoff + sizeof(u32), length); in tg3_ape_scratchpad_read()
892 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_scratchpad_read()
893 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); in tg3_ape_scratchpad_read()
897 if (tg3_ape_wait_for_event(tp, 30000)) in tg3_ape_scratchpad_read()
898 return -EAGAIN; in tg3_ape_scratchpad_read()
900 for (i = 0; length; i += 4, length -= 4) { in tg3_ape_scratchpad_read()
901 u32 val = tg3_ape_read32(tp, msgoff + i); in tg3_ape_scratchpad_read()
911 static int tg3_ape_send_event(struct tg3 *tp, u32 event) in tg3_ape_send_event() argument
916 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_ape_send_event()
918 return -EAGAIN; in tg3_ape_send_event()
920 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_ape_send_event()
922 return -EAGAIN; in tg3_ape_send_event()
925 err = tg3_ape_event_lock(tp, 20000); in tg3_ape_send_event()
929 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS, in tg3_ape_send_event()
932 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM); in tg3_ape_send_event()
933 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1); in tg3_ape_send_event()
938 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind) in tg3_ape_driver_state_change() argument
943 if (!tg3_flag(tp, ENABLE_APE)) in tg3_ape_driver_state_change()
948 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_ape_driver_state_change()
949 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, in tg3_ape_driver_state_change()
951 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN, in tg3_ape_driver_state_change()
953 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT); in tg3_ape_driver_state_change()
954 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata); in tg3_ape_driver_state_change()
955 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID, in tg3_ape_driver_state_change()
957 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR, in tg3_ape_driver_state_change()
959 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, in tg3_ape_driver_state_change()
965 if (device_may_wakeup(&tp->pdev->dev) && in tg3_ape_driver_state_change()
966 tg3_flag(tp, WOL_ENABLE)) { in tg3_ape_driver_state_change()
967 tg3_ape_write32(tp, TG3_APE_HOST_WOL_SPEED, in tg3_ape_driver_state_change()
973 tg3_ape_write32(tp, TG3_APE_HOST_DRVR_STATE, apedata); in tg3_ape_driver_state_change()
983 tg3_ape_send_event(tp, event); in tg3_ape_driver_state_change()
986 static void tg3_send_ape_heartbeat(struct tg3 *tp, in tg3_send_ape_heartbeat() argument
990 if (!tg3_flag(tp, ENABLE_APE) || in tg3_send_ape_heartbeat()
991 time_before(jiffies, tp->ape_hb_jiffies + interval)) in tg3_send_ape_heartbeat()
994 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_COUNT, tp->ape_hb++); in tg3_send_ape_heartbeat()
995 tp->ape_hb_jiffies = jiffies; in tg3_send_ape_heartbeat()
998 static void tg3_disable_ints(struct tg3 *tp) in tg3_disable_ints() argument
1003 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_disable_ints()
1004 for (i = 0; i < tp->irq_max; i++) in tg3_disable_ints()
1005 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001); in tg3_disable_ints()
1008 static void tg3_enable_ints(struct tg3 *tp) in tg3_enable_ints() argument
1012 tp->irq_sync = 0; in tg3_enable_ints()
1016 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT)); in tg3_enable_ints()
1018 tp->coal_now = tp->coalesce_mode | HOSTCC_MODE_ENABLE; in tg3_enable_ints()
1019 for (i = 0; i < tp->irq_cnt; i++) { in tg3_enable_ints()
1020 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_enable_ints()
1022 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1023 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_enable_ints()
1024 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_enable_ints()
1026 tp->coal_now |= tnapi->coal_now; in tg3_enable_ints()
1030 if (!tg3_flag(tp, TAGGED_STATUS) && in tg3_enable_ints()
1031 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED)) in tg3_enable_ints()
1032 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_enable_ints()
1034 tw32(HOSTCC_MODE, tp->coal_now); in tg3_enable_ints()
1036 tp->coal_now &= ~(tp->napi[0].coal_now | tp->napi[1].coal_now); in tg3_enable_ints()
1041 struct tg3 *tp = tnapi->tp; in tg3_has_work() local
1042 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_has_work()
1046 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_has_work()
1047 if (sblk->status & SD_STATUS_LINK_CHG) in tg3_has_work()
1052 if (sblk->idx[0].tx_consumer != tnapi->tx_cons) in tg3_has_work()
1056 if (tnapi->rx_rcb_prod_idx && in tg3_has_work()
1057 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_has_work()
1070 struct tg3 *tp = tnapi->tp; in tg3_int_reenable() local
1072 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_int_reenable()
1078 if (!tg3_flag(tp, TAGGED_STATUS) && tg3_has_work(tnapi)) in tg3_int_reenable()
1079 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_int_reenable()
1080 HOSTCC_MODE_ENABLE | tnapi->coal_now); in tg3_int_reenable()
1083 static void tg3_switch_clocks(struct tg3 *tp) in tg3_switch_clocks() argument
1088 if (tg3_flag(tp, CPMU_PRESENT) || tg3_flag(tp, 5780_CLASS)) in tg3_switch_clocks()
1097 tp->pci_clock_ctrl = clock_ctrl; in tg3_switch_clocks()
1099 if (tg3_flag(tp, 5705_PLUS)) { in tg3_switch_clocks()
1118 static int __tg3_readphy(struct tg3 *tp, unsigned int phy_addr, int reg, in __tg3_readphy() argument
1125 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1127 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_readphy()
1131 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_readphy()
1153 loops -= 1; in __tg3_readphy()
1156 ret = -EBUSY; in __tg3_readphy()
1162 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_readphy()
1163 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_readphy()
1167 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_readphy()
1172 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) in tg3_readphy() argument
1174 return __tg3_readphy(tp, tp->phy_addr, reg, val); in tg3_readphy()
1177 static int __tg3_writephy(struct tg3 *tp, unsigned int phy_addr, int reg, in __tg3_writephy() argument
1184 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in __tg3_writephy()
1188 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1190 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in __tg3_writephy()
1194 tg3_ape_lock(tp, tp->phy_ape_lock); in __tg3_writephy()
1214 loops -= 1; in __tg3_writephy()
1217 ret = -EBUSY; in __tg3_writephy()
1221 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in __tg3_writephy()
1222 tw32_f(MAC_MI_MODE, tp->mi_mode); in __tg3_writephy()
1226 tg3_ape_unlock(tp, tp->phy_ape_lock); in __tg3_writephy()
1231 static int tg3_writephy(struct tg3 *tp, int reg, u32 val) in tg3_writephy() argument
1233 return __tg3_writephy(tp, tp->phy_addr, reg, val); in tg3_writephy()
1236 static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val) in tg3_phy_cl45_write() argument
1240 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_write()
1244 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_write()
1248 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_write()
1253 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_write()
1259 static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val) in tg3_phy_cl45_read() argument
1263 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad); in tg3_phy_cl45_read()
1267 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr); in tg3_phy_cl45_read()
1271 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, in tg3_phy_cl45_read()
1276 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val); in tg3_phy_cl45_read()
1282 static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val) in tg3_phydsp_read() argument
1286 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_read()
1288 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_read()
1293 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) in tg3_phydsp_write() argument
1297 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg); in tg3_phydsp_write()
1299 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write()
1304 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val) in tg3_phy_auxctl_read() argument
1308 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, in tg3_phy_auxctl_read()
1312 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val); in tg3_phy_auxctl_read()
1317 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set) in tg3_phy_auxctl_write() argument
1322 return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg); in tg3_phy_auxctl_write()
1325 static int tg3_phy_toggle_auxctl_smdsp(struct tg3 *tp, bool enable) in tg3_phy_toggle_auxctl_smdsp() argument
1330 err = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, &val); in tg3_phy_toggle_auxctl_smdsp()
1340 err = tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_toggle_auxctl_smdsp()
1346 static int tg3_phy_shdw_write(struct tg3 *tp, int reg, u32 val) in tg3_phy_shdw_write() argument
1348 return tg3_writephy(tp, MII_TG3_MISC_SHDW, in tg3_phy_shdw_write()
1352 static int tg3_bmcr_reset(struct tg3 *tp) in tg3_bmcr_reset() argument
1361 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
1363 return -EBUSY; in tg3_bmcr_reset()
1366 while (limit--) { in tg3_bmcr_reset()
1367 err = tg3_readphy(tp, MII_BMCR, &phy_control); in tg3_bmcr_reset()
1369 return -EBUSY; in tg3_bmcr_reset()
1378 return -EBUSY; in tg3_bmcr_reset()
1385 struct tg3 *tp = bp->priv; in tg3_mdio_read() local
1388 spin_lock_bh(&tp->lock); in tg3_mdio_read()
1390 if (__tg3_readphy(tp, mii_id, reg, &val)) in tg3_mdio_read()
1391 val = -EIO; in tg3_mdio_read()
1393 spin_unlock_bh(&tp->lock); in tg3_mdio_read()
1400 struct tg3 *tp = bp->priv; in tg3_mdio_write() local
1403 spin_lock_bh(&tp->lock); in tg3_mdio_write()
1405 if (__tg3_writephy(tp, mii_id, reg, val)) in tg3_mdio_write()
1406 ret = -EIO; in tg3_mdio_write()
1408 spin_unlock_bh(&tp->lock); in tg3_mdio_write()
1413 static void tg3_mdio_config_5785(struct tg3 *tp) in tg3_mdio_config_5785() argument
1418 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_config_5785()
1419 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_config_5785()
1437 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) { in tg3_mdio_config_5785()
1449 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) in tg3_mdio_config_5785()
1462 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1463 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1465 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1480 if (!tg3_flag(tp, RGMII_INBAND_DISABLE)) { in tg3_mdio_config_5785()
1481 if (tg3_flag(tp, RGMII_EXT_IBND_RX_EN)) in tg3_mdio_config_5785()
1486 if (tg3_flag(tp, RGMII_EXT_IBND_TX_EN)) in tg3_mdio_config_5785()
1494 static void tg3_mdio_start(struct tg3 *tp) in tg3_mdio_start() argument
1496 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL; in tg3_mdio_start()
1497 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_mdio_start()
1500 if (tg3_flag(tp, MDIOBUS_INITED) && in tg3_mdio_start()
1501 tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_mdio_start()
1502 tg3_mdio_config_5785(tp); in tg3_mdio_start()
1505 static int tg3_mdio_init(struct tg3 *tp) in tg3_mdio_init() argument
1511 if (tg3_flag(tp, 5717_PLUS)) { in tg3_mdio_init()
1514 tp->phy_addr = tp->pci_fn + 1; in tg3_mdio_init()
1516 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) in tg3_mdio_init()
1522 tp->phy_addr += 7; in tg3_mdio_init()
1523 } else if (tg3_flag(tp, IS_SSB_CORE) && tg3_flag(tp, ROBOSWITCH)) { in tg3_mdio_init()
1526 addr = ssb_gige_get_phyaddr(tp->pdev); in tg3_mdio_init()
1529 tp->phy_addr = addr; in tg3_mdio_init()
1531 tp->phy_addr = TG3_PHY_MII_ADDR; in tg3_mdio_init()
1533 tg3_mdio_start(tp); in tg3_mdio_init()
1535 if (!tg3_flag(tp, USE_PHYLIB) || tg3_flag(tp, MDIOBUS_INITED)) in tg3_mdio_init()
1538 tp->mdio_bus = mdiobus_alloc(); in tg3_mdio_init()
1539 if (tp->mdio_bus == NULL) in tg3_mdio_init()
1540 return -ENOMEM; in tg3_mdio_init()
1542 tp->mdio_bus->name = "tg3 mdio bus"; in tg3_mdio_init()
1543 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x", pci_dev_id(tp->pdev)); in tg3_mdio_init()
1544 tp->mdio_bus->priv = tp; in tg3_mdio_init()
1545 tp->mdio_bus->parent = &tp->pdev->dev; in tg3_mdio_init()
1546 tp->mdio_bus->read = &tg3_mdio_read; in tg3_mdio_init()
1547 tp->mdio_bus->write = &tg3_mdio_write; in tg3_mdio_init()
1548 tp->mdio_bus->phy_mask = ~(1 << tp->phy_addr); in tg3_mdio_init()
1555 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN)) in tg3_mdio_init()
1556 tg3_bmcr_reset(tp); in tg3_mdio_init()
1558 i = mdiobus_register(tp->mdio_bus); in tg3_mdio_init()
1560 dev_warn(&tp->pdev->dev, "mdiobus_reg failed (0x%x)\n", i); in tg3_mdio_init()
1561 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1565 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_mdio_init()
1567 if (!phydev || !phydev->drv) { in tg3_mdio_init()
1568 dev_warn(&tp->pdev->dev, "No PHY devices\n"); in tg3_mdio_init()
1569 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_init()
1570 mdiobus_free(tp->mdio_bus); in tg3_mdio_init()
1571 return -ENODEV; in tg3_mdio_init()
1574 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) { in tg3_mdio_init()
1576 phydev->interface = PHY_INTERFACE_MODE_GMII; in tg3_mdio_init()
1577 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1581 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE | in tg3_mdio_init()
1587 phydev->interface = PHY_INTERFACE_MODE_RGMII; in tg3_mdio_init()
1591 phydev->interface = PHY_INTERFACE_MODE_MII; in tg3_mdio_init()
1592 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE; in tg3_mdio_init()
1593 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_mdio_init()
1597 tg3_flag_set(tp, MDIOBUS_INITED); in tg3_mdio_init()
1599 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_mdio_init()
1600 tg3_mdio_config_5785(tp); in tg3_mdio_init()
1605 static void tg3_mdio_fini(struct tg3 *tp) in tg3_mdio_fini() argument
1607 if (tg3_flag(tp, MDIOBUS_INITED)) { in tg3_mdio_fini()
1608 tg3_flag_clear(tp, MDIOBUS_INITED); in tg3_mdio_fini()
1609 mdiobus_unregister(tp->mdio_bus); in tg3_mdio_fini()
1610 mdiobus_free(tp->mdio_bus); in tg3_mdio_fini()
1614 /* tp->lock is held. */
1615 static inline void tg3_generate_fw_event(struct tg3 *tp) in tg3_generate_fw_event() argument
1623 tp->last_event_jiffies = jiffies; in tg3_generate_fw_event()
1628 /* tp->lock is held. */
1629 static void tg3_wait_for_event_ack(struct tg3 *tp) in tg3_wait_for_event_ack() argument
1636 time_remain = (long)(tp->last_event_jiffies + 1 + in tg3_wait_for_event_ack()
1637 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) - in tg3_wait_for_event_ack()
1651 if (pci_channel_offline(tp->pdev)) in tg3_wait_for_event_ack()
1658 /* tp->lock is held. */
1659 static void tg3_phy_gather_ump_data(struct tg3 *tp, u32 *data) in tg3_phy_gather_ump_data() argument
1664 if (!tg3_readphy(tp, MII_BMCR, ®)) in tg3_phy_gather_ump_data()
1666 if (!tg3_readphy(tp, MII_BMSR, ®)) in tg3_phy_gather_ump_data()
1671 if (!tg3_readphy(tp, MII_ADVERTISE, ®)) in tg3_phy_gather_ump_data()
1673 if (!tg3_readphy(tp, MII_LPA, ®)) in tg3_phy_gather_ump_data()
1678 if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) { in tg3_phy_gather_ump_data()
1679 if (!tg3_readphy(tp, MII_CTRL1000, ®)) in tg3_phy_gather_ump_data()
1681 if (!tg3_readphy(tp, MII_STAT1000, ®)) in tg3_phy_gather_ump_data()
1686 if (!tg3_readphy(tp, MII_PHYADDR, ®)) in tg3_phy_gather_ump_data()
1693 /* tp->lock is held. */
1694 static void tg3_ump_link_report(struct tg3 *tp) in tg3_ump_link_report() argument
1698 if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF)) in tg3_ump_link_report()
1701 tg3_phy_gather_ump_data(tp, data); in tg3_ump_link_report()
1703 tg3_wait_for_event_ack(tp); in tg3_ump_link_report()
1705 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE); in tg3_ump_link_report()
1706 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14); in tg3_ump_link_report()
1707 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x0, data[0]); in tg3_ump_link_report()
1708 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x4, data[1]); in tg3_ump_link_report()
1709 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0x8, data[2]); in tg3_ump_link_report()
1710 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 0xc, data[3]); in tg3_ump_link_report()
1712 tg3_generate_fw_event(tp); in tg3_ump_link_report()
1715 /* tp->lock is held. */
1716 static void tg3_stop_fw(struct tg3 *tp) in tg3_stop_fw() argument
1718 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_stop_fw()
1720 tg3_wait_for_event_ack(tp); in tg3_stop_fw()
1722 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW); in tg3_stop_fw()
1724 tg3_generate_fw_event(tp); in tg3_stop_fw()
1727 tg3_wait_for_event_ack(tp); in tg3_stop_fw()
1731 /* tp->lock is held. */
1732 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) in tg3_write_sig_pre_reset() argument
1734 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX, in tg3_write_sig_pre_reset()
1737 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_pre_reset()
1740 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1745 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1750 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_pre_reset()
1760 /* tp->lock is held. */
1761 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) in tg3_write_sig_post_reset() argument
1763 if (tg3_flag(tp, ASF_NEW_HANDSHAKE)) { in tg3_write_sig_post_reset()
1766 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_post_reset()
1771 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_post_reset()
1781 /* tp->lock is held. */
1782 static void tg3_write_sig_legacy(struct tg3 *tp, int kind) in tg3_write_sig_legacy() argument
1784 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_write_sig_legacy()
1787 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1792 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1797 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX, in tg3_write_sig_legacy()
1807 static int tg3_poll_fw(struct tg3 *tp) in tg3_poll_fw() argument
1812 if (tg3_flag(tp, NO_FWARE_REPORTED)) in tg3_poll_fw()
1815 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_poll_fw()
1820 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_poll_fw()
1825 if (pci_channel_offline(tp->pdev)) in tg3_poll_fw()
1826 return -ENODEV; in tg3_poll_fw()
1830 return -ENODEV; in tg3_poll_fw()
1835 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val); in tg3_poll_fw()
1838 if (pci_channel_offline(tp->pdev)) { in tg3_poll_fw()
1839 if (!tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1840 tg3_flag_set(tp, NO_FWARE_REPORTED); in tg3_poll_fw()
1841 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1855 if (i >= 100000 && !tg3_flag(tp, NO_FWARE_REPORTED)) { in tg3_poll_fw()
1856 tg3_flag_set(tp, NO_FWARE_REPORTED); in tg3_poll_fw()
1858 netdev_info(tp->dev, "No firmware running\n"); in tg3_poll_fw()
1861 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { in tg3_poll_fw()
1871 static void tg3_link_report(struct tg3 *tp) in tg3_link_report() argument
1873 if (!netif_carrier_ok(tp->dev)) { in tg3_link_report()
1874 netif_info(tp, link, tp->dev, "Link is down\n"); in tg3_link_report()
1875 tg3_ump_link_report(tp); in tg3_link_report()
1876 } else if (netif_msg_link(tp)) { in tg3_link_report()
1877 netdev_info(tp->dev, "Link is up at %d Mbps, %s duplex\n", in tg3_link_report()
1878 (tp->link_config.active_speed == SPEED_1000 ? in tg3_link_report()
1880 (tp->link_config.active_speed == SPEED_100 ? in tg3_link_report()
1882 (tp->link_config.active_duplex == DUPLEX_FULL ? in tg3_link_report()
1885 netdev_info(tp->dev, "Flow control is %s for TX and %s for RX\n", in tg3_link_report()
1886 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ? in tg3_link_report()
1888 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ? in tg3_link_report()
1891 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_link_report()
1892 netdev_info(tp->dev, "EEE is %s\n", in tg3_link_report()
1893 tp->setlpicnt ? "enabled" : "disabled"); in tg3_link_report()
1895 tg3_ump_link_report(tp); in tg3_link_report()
1898 tp->link_up = netif_carrier_ok(tp->dev); in tg3_link_report()
1961 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) in tg3_setup_flow_control() argument
1965 u32 old_rx_mode = tp->rx_mode; in tg3_setup_flow_control()
1966 u32 old_tx_mode = tp->tx_mode; in tg3_setup_flow_control()
1968 if (tg3_flag(tp, USE_PHYLIB)) in tg3_setup_flow_control()
1969 autoneg = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)->autoneg; in tg3_setup_flow_control()
1971 autoneg = tp->link_config.autoneg; in tg3_setup_flow_control()
1973 if (autoneg == AUTONEG_ENABLE && tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_setup_flow_control()
1974 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_setup_flow_control()
1979 flowctrl = tp->link_config.flowctrl; in tg3_setup_flow_control()
1981 tp->link_config.active_flowctrl = flowctrl; in tg3_setup_flow_control()
1984 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1986 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1988 if (old_rx_mode != tp->rx_mode) in tg3_setup_flow_control()
1989 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_setup_flow_control()
1992 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1994 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; in tg3_setup_flow_control()
1996 if (old_tx_mode != tp->tx_mode) in tg3_setup_flow_control()
1997 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_setup_flow_control()
2004 struct tg3 *tp = netdev_priv(dev); in tg3_adjust_link() local
2005 struct phy_device *phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_adjust_link()
2007 spin_lock_bh(&tp->lock); in tg3_adjust_link()
2009 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK | in tg3_adjust_link()
2012 oldflowctrl = tp->link_config.active_flowctrl; in tg3_adjust_link()
2014 if (phydev->link) { in tg3_adjust_link()
2018 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10) in tg3_adjust_link()
2020 else if (phydev->speed == SPEED_1000 || in tg3_adjust_link()
2021 tg3_asic_rev(tp) != ASIC_REV_5785) in tg3_adjust_link()
2026 if (phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2030 tp->link_config.flowctrl); in tg3_adjust_link()
2032 if (phydev->pause) in tg3_adjust_link()
2034 if (phydev->asym_pause) in tg3_adjust_link()
2038 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); in tg3_adjust_link()
2042 if (mac_mode != tp->mac_mode) { in tg3_adjust_link()
2043 tp->mac_mode = mac_mode; in tg3_adjust_link()
2044 tw32_f(MAC_MODE, tp->mac_mode); in tg3_adjust_link()
2048 if (tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_adjust_link()
2049 if (phydev->speed == SPEED_10) in tg3_adjust_link()
2057 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF) in tg3_adjust_link()
2068 if (phydev->link != tp->old_link || in tg3_adjust_link()
2069 phydev->speed != tp->link_config.active_speed || in tg3_adjust_link()
2070 phydev->duplex != tp->link_config.active_duplex || in tg3_adjust_link()
2071 oldflowctrl != tp->link_config.active_flowctrl) in tg3_adjust_link()
2074 tp->old_link = phydev->link; in tg3_adjust_link()
2075 tp->link_config.active_speed = phydev->speed; in tg3_adjust_link()
2076 tp->link_config.active_duplex = phydev->duplex; in tg3_adjust_link()
2078 spin_unlock_bh(&tp->lock); in tg3_adjust_link()
2081 tg3_link_report(tp); in tg3_adjust_link()
2084 static int tg3_phy_init(struct tg3 *tp) in tg3_phy_init() argument
2088 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) in tg3_phy_init()
2092 tg3_bmcr_reset(tp); in tg3_phy_init()
2094 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_init()
2097 phydev = phy_connect(tp->dev, phydev_name(phydev), in tg3_phy_init()
2098 tg3_adjust_link, phydev->interface); in tg3_phy_init()
2100 dev_err(&tp->pdev->dev, "Could not attach to PHY\n"); in tg3_phy_init()
2105 switch (phydev->interface) { in tg3_phy_init()
2108 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init()
2119 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_init()
2120 return -EINVAL; in tg3_phy_init()
2123 tp->phy_flags |= TG3_PHYFLG_IS_CONNECTED; in tg3_phy_init()
2130 static void tg3_phy_start(struct tg3 *tp) in tg3_phy_start() argument
2134 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_start()
2137 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_phy_start()
2139 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_phy_start()
2140 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_phy_start()
2141 phydev->speed = tp->link_config.speed; in tg3_phy_start()
2142 phydev->duplex = tp->link_config.duplex; in tg3_phy_start()
2143 phydev->autoneg = tp->link_config.autoneg; in tg3_phy_start()
2145 phydev->advertising, tp->link_config.advertising); in tg3_phy_start()
2153 static void tg3_phy_stop(struct tg3 *tp) in tg3_phy_stop() argument
2155 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_phy_stop()
2158 phy_stop(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_stop()
2161 static void tg3_phy_fini(struct tg3 *tp) in tg3_phy_fini() argument
2163 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_phy_fini()
2164 phy_disconnect(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_phy_fini()
2165 tp->phy_flags &= ~TG3_PHYFLG_IS_CONNECTED; in tg3_phy_fini()
2169 static int tg3_phy_set_extloopbk(struct tg3 *tp) in tg3_phy_set_extloopbk() argument
2174 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_set_extloopbk()
2177 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_set_extloopbk()
2178 /* Cannot do read-modify-write on 5401 */ in tg3_phy_set_extloopbk()
2179 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2186 err = tg3_phy_auxctl_read(tp, in tg3_phy_set_extloopbk()
2192 err = tg3_phy_auxctl_write(tp, in tg3_phy_set_extloopbk()
2199 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) in tg3_phy_fet_toggle_apd() argument
2203 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_phy_fet_toggle_apd()
2206 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_fet_toggle_apd()
2208 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) { in tg3_phy_fet_toggle_apd()
2213 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy); in tg3_phy_fet_toggle_apd()
2215 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_phy_fet_toggle_apd()
2219 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable) in tg3_phy_toggle_apd() argument
2223 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_apd()
2224 (tg3_flag(tp, 5717_PLUS) && in tg3_phy_toggle_apd()
2225 (tp->phy_flags & TG3_PHYFLG_MII_SERDES))) in tg3_phy_toggle_apd()
2228 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_apd()
2229 tg3_phy_fet_toggle_apd(tp, enable); in tg3_phy_toggle_apd()
2237 if (tg3_asic_rev(tp) != ASIC_REV_5784 || !enable) in tg3_phy_toggle_apd()
2240 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_SCR5_SEL, reg); in tg3_phy_toggle_apd()
2247 tg3_phy_shdw_write(tp, MII_TG3_MISC_SHDW_APD_SEL, reg); in tg3_phy_toggle_apd()
2250 static void tg3_phy_toggle_automdix(struct tg3 *tp, bool enable) in tg3_phy_toggle_automdix() argument
2254 if (!tg3_flag(tp, 5705_PLUS) || in tg3_phy_toggle_automdix()
2255 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_toggle_automdix()
2258 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_toggle_automdix()
2261 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) { in tg3_phy_toggle_automdix()
2264 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_phy_toggle_automdix()
2266 if (!tg3_readphy(tp, reg, &phy)) { in tg3_phy_toggle_automdix()
2271 tg3_writephy(tp, reg, phy); in tg3_phy_toggle_automdix()
2273 tg3_writephy(tp, MII_TG3_FET_TEST, ephy); in tg3_phy_toggle_automdix()
2278 ret = tg3_phy_auxctl_read(tp, in tg3_phy_toggle_automdix()
2285 tg3_phy_auxctl_write(tp, in tg3_phy_toggle_automdix()
2291 static void tg3_phy_set_wirespeed(struct tg3 *tp) in tg3_phy_set_wirespeed() argument
2296 if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) in tg3_phy_set_wirespeed()
2299 ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val); in tg3_phy_set_wirespeed()
2301 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, in tg3_phy_set_wirespeed()
2305 static void tg3_phy_apply_otp(struct tg3 *tp) in tg3_phy_apply_otp() argument
2309 if (!tp->phy_otp) in tg3_phy_apply_otp()
2312 otp = tp->phy_otp; in tg3_phy_apply_otp()
2314 if (tg3_phy_toggle_auxctl_smdsp(tp, true)) in tg3_phy_apply_otp()
2319 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy); in tg3_phy_apply_otp()
2323 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy); in tg3_phy_apply_otp()
2327 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy); in tg3_phy_apply_otp()
2330 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy); in tg3_phy_apply_otp()
2333 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy); in tg3_phy_apply_otp()
2337 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy); in tg3_phy_apply_otp()
2339 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_apply_otp()
2342 static void tg3_eee_pull_config(struct tg3 *tp, struct ethtool_eee *eee) in tg3_eee_pull_config() argument
2345 struct ethtool_eee *dest = &tp->eee; in tg3_eee_pull_config()
2347 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_eee_pull_config()
2353 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, TG3_CL45_D7_EEERES_STAT, &val)) in tg3_eee_pull_config()
2359 dest->eee_active = 1; in tg3_eee_pull_config()
2361 dest->eee_active = 0; in tg3_eee_pull_config()
2364 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE, &val)) in tg3_eee_pull_config()
2366 dest->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val); in tg3_eee_pull_config()
2369 if (tg3_phy_cl45_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, &val)) in tg3_eee_pull_config()
2371 dest->eee_enabled = !!val; in tg3_eee_pull_config()
2372 dest->advertised = mmd_eee_adv_to_ethtool_adv_t(val); in tg3_eee_pull_config()
2376 dest->tx_lpi_enabled = !!(val & TG3_CPMU_EEEMD_LPI_IN_TX); in tg3_eee_pull_config()
2379 dest->tx_lpi_timer = tr32(TG3_CPMU_EEE_DBTMR1) & 0xffff; in tg3_eee_pull_config()
2382 static void tg3_phy_eee_adjust(struct tg3 *tp, bool current_link_up) in tg3_phy_eee_adjust() argument
2386 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_adjust()
2389 tp->setlpicnt = 0; in tg3_phy_eee_adjust()
2391 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_phy_eee_adjust()
2393 tp->link_config.active_duplex == DUPLEX_FULL && in tg3_phy_eee_adjust()
2394 (tp->link_config.active_speed == SPEED_100 || in tg3_phy_eee_adjust()
2395 tp->link_config.active_speed == SPEED_1000)) { in tg3_phy_eee_adjust()
2398 if (tp->link_config.active_speed == SPEED_1000) in tg3_phy_eee_adjust()
2405 tg3_eee_pull_config(tp, NULL); in tg3_phy_eee_adjust()
2406 if (tp->eee.eee_active) in tg3_phy_eee_adjust()
2407 tp->setlpicnt = 2; in tg3_phy_eee_adjust()
2410 if (!tp->setlpicnt) { in tg3_phy_eee_adjust()
2412 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_eee_adjust()
2413 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); in tg3_phy_eee_adjust()
2414 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_eee_adjust()
2422 static void tg3_phy_eee_enable(struct tg3 *tp) in tg3_phy_eee_enable() argument
2426 if (tp->link_config.active_speed == SPEED_1000 && in tg3_phy_eee_enable()
2427 (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_phy_eee_enable()
2428 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_phy_eee_enable()
2429 tg3_flag(tp, 57765_CLASS)) && in tg3_phy_eee_enable()
2430 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_eee_enable()
2433 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); in tg3_phy_eee_enable()
2434 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_eee_enable()
2441 static int tg3_wait_macro_done(struct tg3 *tp) in tg3_wait_macro_done() argument
2445 while (limit--) { in tg3_wait_macro_done()
2448 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) { in tg3_wait_macro_done()
2454 return -EBUSY; in tg3_wait_macro_done()
2459 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp) in tg3_phy_write_and_check_testpat() argument
2472 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2474 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_write_and_check_testpat()
2477 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
2480 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_write_and_check_testpat()
2481 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2483 return -EBUSY; in tg3_phy_write_and_check_testpat()
2486 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_write_and_check_testpat()
2488 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082); in tg3_phy_write_and_check_testpat()
2489 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2491 return -EBUSY; in tg3_phy_write_and_check_testpat()
2494 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802); in tg3_phy_write_and_check_testpat()
2495 if (tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2497 return -EBUSY; in tg3_phy_write_and_check_testpat()
2503 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || in tg3_phy_write_and_check_testpat()
2504 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || in tg3_phy_write_and_check_testpat()
2505 tg3_wait_macro_done(tp)) { in tg3_phy_write_and_check_testpat()
2507 return -EBUSY; in tg3_phy_write_and_check_testpat()
2513 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b); in tg3_phy_write_and_check_testpat()
2514 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
2515 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
2517 return -EBUSY; in tg3_phy_write_and_check_testpat()
2525 static int tg3_phy_reset_chanpat(struct tg3 *tp) in tg3_phy_reset_chanpat() argument
2532 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_phy_reset_chanpat()
2534 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002); in tg3_phy_reset_chanpat()
2536 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
2537 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202); in tg3_phy_reset_chanpat()
2538 if (tg3_wait_macro_done(tp)) in tg3_phy_reset_chanpat()
2539 return -EBUSY; in tg3_phy_reset_chanpat()
2545 static int tg3_phy_reset_5703_4_5(struct tg3 *tp) in tg3_phy_reset_5703_4_5() argument
2554 err = tg3_bmcr_reset(tp); in tg3_phy_reset_5703_4_5()
2561 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) in tg3_phy_reset_5703_4_5()
2565 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2567 /* Set full-duplex, 1000 mbps. */ in tg3_phy_reset_5703_4_5()
2568 tg3_writephy(tp, MII_BMCR, in tg3_phy_reset_5703_4_5()
2572 if (tg3_readphy(tp, MII_CTRL1000, &phy9_orig)) in tg3_phy_reset_5703_4_5()
2575 tg3_writephy(tp, MII_CTRL1000, in tg3_phy_reset_5703_4_5()
2578 err = tg3_phy_toggle_auxctl_smdsp(tp, true); in tg3_phy_reset_5703_4_5()
2583 tg3_phydsp_write(tp, 0x8005, 0x0800); in tg3_phy_reset_5703_4_5()
2585 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset); in tg3_phy_reset_5703_4_5()
2588 } while (--retries); in tg3_phy_reset_5703_4_5()
2590 err = tg3_phy_reset_chanpat(tp); in tg3_phy_reset_5703_4_5()
2594 tg3_phydsp_write(tp, 0x8005, 0x0000); in tg3_phy_reset_5703_4_5()
2596 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200); in tg3_phy_reset_5703_4_5()
2597 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000); in tg3_phy_reset_5703_4_5()
2599 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset_5703_4_5()
2601 tg3_writephy(tp, MII_CTRL1000, phy9_orig); in tg3_phy_reset_5703_4_5()
2603 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32); in tg3_phy_reset_5703_4_5()
2608 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2613 static void tg3_carrier_off(struct tg3 *tp) in tg3_carrier_off() argument
2615 netif_carrier_off(tp->dev); in tg3_carrier_off()
2616 tp->link_up = false; in tg3_carrier_off()
2619 static void tg3_warn_mgmt_link_flap(struct tg3 *tp) in tg3_warn_mgmt_link_flap() argument
2621 if (tg3_flag(tp, ENABLE_ASF)) in tg3_warn_mgmt_link_flap()
2622 netdev_warn(tp->dev, in tg3_warn_mgmt_link_flap()
2623 "Management side-band traffic will be interrupted during phy settings change\n"); in tg3_warn_mgmt_link_flap()
2627 * link unless the FORCE argument is non-zero.
2629 static int tg3_phy_reset(struct tg3 *tp) in tg3_phy_reset() argument
2634 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_phy_reset()
2639 err = tg3_readphy(tp, MII_BMSR, &val); in tg3_phy_reset()
2640 err |= tg3_readphy(tp, MII_BMSR, &val); in tg3_phy_reset()
2642 return -EBUSY; in tg3_phy_reset()
2644 if (netif_running(tp->dev) && tp->link_up) { in tg3_phy_reset()
2645 netif_carrier_off(tp->dev); in tg3_phy_reset()
2646 tg3_link_report(tp); in tg3_phy_reset()
2649 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_phy_reset()
2650 tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_phy_reset()
2651 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_phy_reset()
2652 err = tg3_phy_reset_5703_4_5(tp); in tg3_phy_reset()
2659 if (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_phy_reset()
2660 tg3_chip_rev(tp) != CHIPREV_5784_AX) { in tg3_phy_reset()
2667 err = tg3_bmcr_reset(tp); in tg3_phy_reset()
2673 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val); in tg3_phy_reset()
2678 if (tg3_chip_rev(tp) == CHIPREV_5784_AX || in tg3_phy_reset()
2679 tg3_chip_rev(tp) == CHIPREV_5761_AX) { in tg3_phy_reset()
2689 if (tg3_flag(tp, 5717_PLUS) && in tg3_phy_reset()
2690 (tp->phy_flags & TG3_PHYFLG_MII_SERDES)) in tg3_phy_reset()
2693 tg3_phy_apply_otp(tp); in tg3_phy_reset()
2695 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_phy_reset()
2696 tg3_phy_toggle_apd(tp, true); in tg3_phy_reset()
2698 tg3_phy_toggle_apd(tp, false); in tg3_phy_reset()
2701 if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) && in tg3_phy_reset()
2702 !tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2703 tg3_phydsp_write(tp, 0x201f, 0x2aaa); in tg3_phy_reset()
2704 tg3_phydsp_write(tp, 0x000a, 0x0323); in tg3_phy_reset()
2705 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2708 if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) { in tg3_phy_reset()
2709 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2710 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_phy_reset()
2713 if (tp->phy_flags & TG3_PHYFLG_BER_BUG) { in tg3_phy_reset()
2714 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2715 tg3_phydsp_write(tp, 0x000a, 0x310b); in tg3_phy_reset()
2716 tg3_phydsp_write(tp, 0x201f, 0x9506); in tg3_phy_reset()
2717 tg3_phydsp_write(tp, 0x401f, 0x14e2); in tg3_phy_reset()
2718 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2720 } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) { in tg3_phy_reset()
2721 if (!tg3_phy_toggle_auxctl_smdsp(tp, true)) { in tg3_phy_reset()
2722 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); in tg3_phy_reset()
2723 if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) { in tg3_phy_reset()
2724 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset()
2725 tg3_writephy(tp, MII_TG3_TEST1, in tg3_phy_reset()
2728 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); in tg3_phy_reset()
2730 tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_reset()
2736 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_reset()
2737 /* Cannot do read-modify-write on 5401 */ in tg3_phy_reset()
2738 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_phy_reset()
2739 } else if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2740 /* Set bit 14 with read-modify-write to preserve other bits */ in tg3_phy_reset()
2741 err = tg3_phy_auxctl_read(tp, in tg3_phy_reset()
2744 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, in tg3_phy_reset()
2751 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_phy_reset()
2752 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &val)) in tg3_phy_reset()
2753 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_reset()
2757 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_phy_reset()
2759 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12); in tg3_phy_reset()
2762 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5762_A0) in tg3_phy_reset()
2763 tg3_phydsp_write(tp, 0xffb, 0x4000); in tg3_phy_reset()
2765 tg3_phy_toggle_automdix(tp, true); in tg3_phy_reset()
2766 tg3_phy_set_wirespeed(tp); in tg3_phy_reset()
2786 static inline u32 tg3_set_function_status(struct tg3 *tp, u32 newstat) in tg3_set_function_status() argument
2790 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_function_status()
2791 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_set_function_status()
2792 status = tg3_ape_read32(tp, TG3_APE_GPIO_MSG); in tg3_set_function_status()
2796 shift = TG3_APE_GPIO_MSG_SHIFT + 4 * tp->pci_fn; in tg3_set_function_status()
2800 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_function_status()
2801 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_set_function_status()
2802 tg3_ape_write32(tp, TG3_APE_GPIO_MSG, status); in tg3_set_function_status()
2809 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3 *tp) in tg3_pwrsrc_switch_to_vmain() argument
2811 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vmain()
2814 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_pwrsrc_switch_to_vmain()
2815 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_pwrsrc_switch_to_vmain()
2816 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_pwrsrc_switch_to_vmain()
2817 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_pwrsrc_switch_to_vmain()
2818 return -EIO; in tg3_pwrsrc_switch_to_vmain()
2820 tg3_set_function_status(tp, TG3_GPIO_MSG_DRVR_PRES); in tg3_pwrsrc_switch_to_vmain()
2822 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2825 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); in tg3_pwrsrc_switch_to_vmain()
2827 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, in tg3_pwrsrc_switch_to_vmain()
2834 static void tg3_pwrsrc_die_with_vmain(struct tg3 *tp) in tg3_pwrsrc_die_with_vmain() argument
2838 if (!tg3_flag(tp, IS_NIC) || in tg3_pwrsrc_die_with_vmain()
2839 tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_pwrsrc_die_with_vmain()
2840 tg3_asic_rev(tp) == ASIC_REV_5701) in tg3_pwrsrc_die_with_vmain()
2843 grc_local_ctrl = tp->grc_local_ctrl | GRC_LCLCTRL_GPIO_OE1; in tg3_pwrsrc_die_with_vmain()
2858 static void tg3_pwrsrc_switch_to_vaux(struct tg3 *tp) in tg3_pwrsrc_switch_to_vaux() argument
2860 if (!tg3_flag(tp, IS_NIC)) in tg3_pwrsrc_switch_to_vaux()
2863 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_pwrsrc_switch_to_vaux()
2864 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_pwrsrc_switch_to_vaux()
2865 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2872 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_pwrsrc_switch_to_vaux()
2873 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_pwrsrc_switch_to_vaux()
2874 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */ in tg3_pwrsrc_switch_to_vaux()
2880 tp->grc_local_ctrl; in tg3_pwrsrc_switch_to_vaux()
2896 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_pwrsrc_switch_to_vaux()
2898 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl | in tg3_pwrsrc_switch_to_vaux()
2904 no_gpio2 = tp->nic_sram_data_cfg & in tg3_pwrsrc_switch_to_vaux()
2917 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2923 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2929 tp->grc_local_ctrl | grc_local_ctrl, in tg3_pwrsrc_switch_to_vaux()
2935 static void tg3_frob_aux_power_5717(struct tg3 *tp, bool wol_enable) in tg3_frob_aux_power_5717() argument
2940 if (tg3_ape_lock(tp, TG3_APE_LOCK_GPIO)) in tg3_frob_aux_power_5717()
2943 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE) || wol_enable) in tg3_frob_aux_power_5717()
2946 msg = tg3_set_function_status(tp, msg); in tg3_frob_aux_power_5717()
2952 tg3_pwrsrc_switch_to_vaux(tp); in tg3_frob_aux_power_5717()
2954 tg3_pwrsrc_die_with_vmain(tp); in tg3_frob_aux_power_5717()
2957 tg3_ape_unlock(tp, TG3_APE_LOCK_GPIO); in tg3_frob_aux_power_5717()
2960 static void tg3_frob_aux_power(struct tg3 *tp, bool include_wol) in tg3_frob_aux_power() argument
2965 if (!tg3_flag(tp, IS_NIC) || tg3_flag(tp, 57765_CLASS)) in tg3_frob_aux_power()
2968 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_frob_aux_power()
2969 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_frob_aux_power()
2970 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_frob_aux_power()
2971 tg3_frob_aux_power_5717(tp, include_wol ? in tg3_frob_aux_power()
2972 tg3_flag(tp, WOL_ENABLE) != 0 : 0); in tg3_frob_aux_power()
2976 if (tp->pdev_peer && tp->pdev_peer != tp->pdev) { in tg3_frob_aux_power()
2979 dev_peer = pci_get_drvdata(tp->pdev_peer); in tg3_frob_aux_power()
2994 if ((include_wol && tg3_flag(tp, WOL_ENABLE)) || in tg3_frob_aux_power()
2995 tg3_flag(tp, ENABLE_ASF)) in tg3_frob_aux_power()
2999 tg3_pwrsrc_switch_to_vaux(tp); in tg3_frob_aux_power()
3001 tg3_pwrsrc_die_with_vmain(tp); in tg3_frob_aux_power()
3004 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed) in tg3_5700_link_polarity() argument
3006 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2) in tg3_5700_link_polarity()
3008 else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) { in tg3_5700_link_polarity()
3017 static bool tg3_phy_power_bug(struct tg3 *tp) in tg3_phy_power_bug() argument
3019 switch (tg3_asic_rev(tp)) { in tg3_phy_power_bug()
3024 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_phy_power_bug()
3028 if (!tp->pci_fn) in tg3_phy_power_bug()
3033 if ((tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_phy_power_bug()
3034 !tp->pci_fn) in tg3_phy_power_bug()
3042 static bool tg3_phy_led_bug(struct tg3 *tp) in tg3_phy_led_bug() argument
3044 switch (tg3_asic_rev(tp)) { in tg3_phy_led_bug()
3047 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_led_bug()
3048 !tp->pci_fn) in tg3_phy_led_bug()
3056 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power) in tg3_power_down_phy() argument
3060 if (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) in tg3_power_down_phy()
3063 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_power_down_phy()
3064 if (tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_power_down_phy()
3076 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_phy()
3077 tg3_bmcr_reset(tp); in tg3_power_down_phy()
3082 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_power_down_phy()
3084 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) { in tg3_power_down_phy()
3087 tg3_writephy(tp, MII_ADVERTISE, 0); in tg3_power_down_phy()
3088 tg3_writephy(tp, MII_BMCR, in tg3_power_down_phy()
3091 tg3_writephy(tp, MII_TG3_FET_TEST, in tg3_power_down_phy()
3093 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) { in tg3_power_down_phy()
3095 tg3_writephy(tp, in tg3_power_down_phy()
3099 tg3_writephy(tp, MII_TG3_FET_TEST, phytest); in tg3_power_down_phy()
3103 if (!tg3_phy_led_bug(tp)) in tg3_power_down_phy()
3104 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_power_down_phy()
3110 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, val); in tg3_power_down_phy()
3116 if (tg3_phy_power_bug(tp)) in tg3_power_down_phy()
3119 if (tg3_chip_rev(tp) == CHIPREV_5784_AX || in tg3_power_down_phy()
3120 tg3_chip_rev(tp) == CHIPREV_5761_AX) { in tg3_power_down_phy()
3127 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN); in tg3_power_down_phy()
3130 /* tp->lock is held. */
3131 static int tg3_nvram_lock(struct tg3 *tp) in tg3_nvram_lock() argument
3133 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_lock()
3136 if (tp->nvram_lock_cnt == 0) { in tg3_nvram_lock()
3145 return -ENODEV; in tg3_nvram_lock()
3148 tp->nvram_lock_cnt++; in tg3_nvram_lock()
3153 /* tp->lock is held. */
3154 static void tg3_nvram_unlock(struct tg3 *tp) in tg3_nvram_unlock() argument
3156 if (tg3_flag(tp, NVRAM)) { in tg3_nvram_unlock()
3157 if (tp->nvram_lock_cnt > 0) in tg3_nvram_unlock()
3158 tp->nvram_lock_cnt--; in tg3_nvram_unlock()
3159 if (tp->nvram_lock_cnt == 0) in tg3_nvram_unlock()
3164 /* tp->lock is held. */
3165 static void tg3_enable_nvram_access(struct tg3 *tp) in tg3_enable_nvram_access() argument
3167 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_enable_nvram_access()
3174 /* tp->lock is held. */
3175 static void tg3_disable_nvram_access(struct tg3 *tp) in tg3_disable_nvram_access() argument
3177 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) { in tg3_disable_nvram_access()
3184 static int tg3_nvram_read_using_eeprom(struct tg3 *tp, in tg3_nvram_read_using_eeprom() argument
3191 return -EINVAL; in tg3_nvram_read_using_eeprom()
3211 return -EBUSY; in tg3_nvram_read_using_eeprom()
3226 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) in tg3_nvram_exec_cmd() argument
3240 return -EBUSY; in tg3_nvram_exec_cmd()
3245 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) in tg3_nvram_phys_addr() argument
3247 if (tg3_flag(tp, NVRAM) && in tg3_nvram_phys_addr()
3248 tg3_flag(tp, NVRAM_BUFFERED) && in tg3_nvram_phys_addr()
3249 tg3_flag(tp, FLASH) && in tg3_nvram_phys_addr()
3250 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && in tg3_nvram_phys_addr()
3251 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_phys_addr()
3253 addr = ((addr / tp->nvram_pagesize) << in tg3_nvram_phys_addr()
3255 (addr % tp->nvram_pagesize); in tg3_nvram_phys_addr()
3260 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr) in tg3_nvram_logical_addr() argument
3262 if (tg3_flag(tp, NVRAM) && in tg3_nvram_logical_addr()
3263 tg3_flag(tp, NVRAM_BUFFERED) && in tg3_nvram_logical_addr()
3264 tg3_flag(tp, FLASH) && in tg3_nvram_logical_addr()
3265 !tg3_flag(tp, NO_NVRAM_ADDR_TRANS) && in tg3_nvram_logical_addr()
3266 (tp->nvram_jedecnum == JEDEC_ATMEL)) in tg3_nvram_logical_addr()
3269 tp->nvram_pagesize) + in tg3_nvram_logical_addr()
3270 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1)); in tg3_nvram_logical_addr()
3279 * machine, the 32-bit value will be byteswapped.
3281 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) in tg3_nvram_read() argument
3285 if (!tg3_flag(tp, NVRAM)) in tg3_nvram_read()
3286 return tg3_nvram_read_using_eeprom(tp, offset, val); in tg3_nvram_read()
3288 offset = tg3_nvram_phys_addr(tp, offset); in tg3_nvram_read()
3291 return -EINVAL; in tg3_nvram_read()
3293 ret = tg3_nvram_lock(tp); in tg3_nvram_read()
3297 tg3_enable_nvram_access(tp); in tg3_nvram_read()
3300 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO | in tg3_nvram_read()
3306 tg3_disable_nvram_access(tp); in tg3_nvram_read()
3308 tg3_nvram_unlock(tp); in tg3_nvram_read()
3314 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val) in tg3_nvram_read_be32() argument
3317 int res = tg3_nvram_read(tp, offset, &v); in tg3_nvram_read_be32()
3323 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, in tg3_nvram_write_block_using_eeprom() argument
3364 rc = -EBUSY; in tg3_nvram_write_block_using_eeprom()
3373 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, in tg3_nvram_write_block_unbuffered() argument
3377 u32 pagesize = tp->nvram_pagesize; in tg3_nvram_write_block_unbuffered()
3378 u32 pagemask = pagesize - 1; in tg3_nvram_write_block_unbuffered()
3384 return -ENOMEM; in tg3_nvram_write_block_unbuffered()
3393 ret = tg3_nvram_read_be32(tp, phy_addr + j, in tg3_nvram_write_block_unbuffered()
3406 len -= size; in tg3_nvram_write_block_unbuffered()
3410 offset = offset + (pagesize - page_off); in tg3_nvram_write_block_unbuffered()
3412 tg3_enable_nvram_access(tp); in tg3_nvram_write_block_unbuffered()
3420 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3429 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3435 if (tg3_nvram_exec_cmd(tp, nvram_cmd)) in tg3_nvram_write_block_unbuffered()
3452 else if (j == (pagesize - 4)) in tg3_nvram_write_block_unbuffered()
3455 ret = tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_unbuffered()
3464 tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_unbuffered()
3472 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, in tg3_nvram_write_block_buffered() argument
3484 page_off = offset % tp->nvram_pagesize; in tg3_nvram_write_block_buffered()
3486 phy_addr = tg3_nvram_phys_addr(tp, offset); in tg3_nvram_write_block_buffered()
3492 if (page_off == (tp->nvram_pagesize - 4)) in tg3_nvram_write_block_buffered()
3495 if (i == (len - 4)) in tg3_nvram_write_block_buffered()
3499 !tg3_flag(tp, FLASH) || in tg3_nvram_write_block_buffered()
3500 !tg3_flag(tp, 57765_PLUS)) in tg3_nvram_write_block_buffered()
3503 if (tg3_asic_rev(tp) != ASIC_REV_5752 && in tg3_nvram_write_block_buffered()
3504 !tg3_flag(tp, 5755_PLUS) && in tg3_nvram_write_block_buffered()
3505 (tp->nvram_jedecnum == JEDEC_ST) && in tg3_nvram_write_block_buffered()
3510 ret = tg3_nvram_exec_cmd(tp, cmd); in tg3_nvram_write_block_buffered()
3514 if (!tg3_flag(tp, FLASH)) { in tg3_nvram_write_block_buffered()
3519 ret = tg3_nvram_exec_cmd(tp, nvram_cmd); in tg3_nvram_write_block_buffered()
3527 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) in tg3_nvram_write_block() argument
3531 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
3532 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl & in tg3_nvram_write_block()
3537 if (!tg3_flag(tp, NVRAM)) { in tg3_nvram_write_block()
3538 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf); in tg3_nvram_write_block()
3542 ret = tg3_nvram_lock(tp); in tg3_nvram_write_block()
3546 tg3_enable_nvram_access(tp); in tg3_nvram_write_block()
3547 if (tg3_flag(tp, 5750_PLUS) && !tg3_flag(tp, PROTECTED_NVRAM)) in tg3_nvram_write_block()
3553 if (tg3_flag(tp, NVRAM_BUFFERED) || !tg3_flag(tp, FLASH)) { in tg3_nvram_write_block()
3554 ret = tg3_nvram_write_block_buffered(tp, offset, len, in tg3_nvram_write_block()
3557 ret = tg3_nvram_write_block_unbuffered(tp, offset, len, in tg3_nvram_write_block()
3564 tg3_disable_nvram_access(tp); in tg3_nvram_write_block()
3565 tg3_nvram_unlock(tp); in tg3_nvram_write_block()
3568 if (tg3_flag(tp, EEPROM_WRITE_PROT)) { in tg3_nvram_write_block()
3569 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_nvram_write_block()
3581 /* tp->lock is held. */
3582 static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base) in tg3_pause_cpu() argument
3592 if (pci_channel_offline(tp->pdev)) in tg3_pause_cpu()
3593 return -EBUSY; in tg3_pause_cpu()
3596 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu()
3599 /* tp->lock is held. */
3600 static int tg3_rxcpu_pause(struct tg3 *tp) in tg3_rxcpu_pause() argument
3602 int rc = tg3_pause_cpu(tp, RX_CPU_BASE); in tg3_rxcpu_pause()
3611 /* tp->lock is held. */
3612 static int tg3_txcpu_pause(struct tg3 *tp) in tg3_txcpu_pause() argument
3614 return tg3_pause_cpu(tp, TX_CPU_BASE); in tg3_txcpu_pause()
3617 /* tp->lock is held. */
3618 static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base) in tg3_resume_cpu() argument
3624 /* tp->lock is held. */
3625 static void tg3_rxcpu_resume(struct tg3 *tp) in tg3_rxcpu_resume() argument
3627 tg3_resume_cpu(tp, RX_CPU_BASE); in tg3_rxcpu_resume()
3630 /* tp->lock is held. */
3631 static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base) in tg3_halt_cpu() argument
3635 BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)); in tg3_halt_cpu()
3637 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_halt_cpu()
3644 rc = tg3_rxcpu_pause(tp); in tg3_halt_cpu()
3650 if (tg3_flag(tp, IS_SSB_CORE)) in tg3_halt_cpu()
3653 rc = tg3_txcpu_pause(tp); in tg3_halt_cpu()
3657 netdev_err(tp->dev, "%s timed out, %s CPU\n", in tg3_halt_cpu()
3659 return -ENODEV; in tg3_halt_cpu()
3663 if (tg3_flag(tp, NVRAM)) in tg3_halt_cpu()
3668 static int tg3_fw_data_len(struct tg3 *tp, in tg3_fw_data_len() argument
3677 * tp->fw->size minus headers. in tg3_fw_data_len()
3687 if (tp->fw_len == 0xffffffff) in tg3_fw_data_len()
3688 fw_len = be32_to_cpu(fw_hdr->len); in tg3_fw_data_len()
3690 fw_len = tp->fw->size; in tg3_fw_data_len()
3692 return (fw_len - TG3_FW_HDR_LEN) / sizeof(u32); in tg3_fw_data_len()
3695 /* tp->lock is held. */
3696 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, in tg3_load_firmware_cpu() argument
3702 int total_len = tp->fw->size; in tg3_load_firmware_cpu()
3704 if (cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS)) { in tg3_load_firmware_cpu()
3705 netdev_err(tp->dev, in tg3_load_firmware_cpu()
3708 return -EINVAL; in tg3_load_firmware_cpu()
3711 if (tg3_flag(tp, 5705_PLUS) && tg3_asic_rev(tp) != ASIC_REV_57766) in tg3_load_firmware_cpu()
3716 if (tg3_asic_rev(tp) != ASIC_REV_57766) { in tg3_load_firmware_cpu()
3720 int lock_err = tg3_nvram_lock(tp); in tg3_load_firmware_cpu()
3721 err = tg3_halt_cpu(tp, cpu_base); in tg3_load_firmware_cpu()
3723 tg3_nvram_unlock(tp); in tg3_load_firmware_cpu()
3728 write_op(tp, cpu_scratch_base + i, 0); in tg3_load_firmware_cpu()
3736 total_len -= TG3_FW_HDR_LEN; in tg3_load_firmware_cpu()
3742 for (i = 0; i < tg3_fw_data_len(tp, fw_hdr); i++) in tg3_load_firmware_cpu()
3743 write_op(tp, cpu_scratch_base + in tg3_load_firmware_cpu()
3744 (be32_to_cpu(fw_hdr->base_addr) & 0xffff) + in tg3_load_firmware_cpu()
3748 total_len -= be32_to_cpu(fw_hdr->len); in tg3_load_firmware_cpu()
3752 ((void *)fw_hdr + be32_to_cpu(fw_hdr->len)); in tg3_load_firmware_cpu()
3761 /* tp->lock is held. */
3762 static int tg3_pause_cpu_and_set_pc(struct tg3 *tp, u32 cpu_base, u32 pc) in tg3_pause_cpu_and_set_pc() argument
3779 return (i == iters) ? -EBUSY : 0; in tg3_pause_cpu_and_set_pc()
3782 /* tp->lock is held. */
3783 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) in tg3_load_5701_a0_firmware_fix() argument
3788 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_5701_a0_firmware_fix()
3792 length = end_address_of_bss - start_address_of_text. in tg3_load_5701_a0_firmware_fix()
3796 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3802 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3809 err = tg3_pause_cpu_and_set_pc(tp, RX_CPU_BASE, in tg3_load_5701_a0_firmware_fix()
3810 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3812 netdev_err(tp->dev, "%s fails to set RX CPU PC, is %08x " in tg3_load_5701_a0_firmware_fix()
3815 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_5701_a0_firmware_fix()
3816 return -ENODEV; in tg3_load_5701_a0_firmware_fix()
3819 tg3_rxcpu_resume(tp); in tg3_load_5701_a0_firmware_fix()
3824 static int tg3_validate_rxcpu_state(struct tg3 *tp) in tg3_validate_rxcpu_state() argument
3841 netdev_err(tp->dev, "Boot code not ready for service patches\n"); in tg3_validate_rxcpu_state()
3842 return -EBUSY; in tg3_validate_rxcpu_state()
3845 val = tg3_read_indirect_reg32(tp, TG3_57766_FW_HANDSHAKE); in tg3_validate_rxcpu_state()
3847 netdev_warn(tp->dev, in tg3_validate_rxcpu_state()
3849 return -EEXIST; in tg3_validate_rxcpu_state()
3855 /* tp->lock is held. */
3856 static void tg3_load_57766_firmware(struct tg3 *tp) in tg3_load_57766_firmware() argument
3860 if (!tg3_flag(tp, NO_NVRAM)) in tg3_load_57766_firmware()
3863 if (tg3_validate_rxcpu_state(tp)) in tg3_load_57766_firmware()
3866 if (!tp->fw) in tg3_load_57766_firmware()
3871 * data to be written to non-contiguous locations. in tg3_load_57766_firmware()
3883 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_57766_firmware()
3884 if (be32_to_cpu(fw_hdr->base_addr) != TG3_57766_FW_BASE_ADDR) in tg3_load_57766_firmware()
3887 if (tg3_rxcpu_pause(tp)) in tg3_load_57766_firmware()
3891 tg3_load_firmware_cpu(tp, 0, TG3_57766_FW_BASE_ADDR, 0, fw_hdr); in tg3_load_57766_firmware()
3893 tg3_rxcpu_resume(tp); in tg3_load_57766_firmware()
3896 /* tp->lock is held. */
3897 static int tg3_load_tso_firmware(struct tg3 *tp) in tg3_load_tso_firmware() argument
3903 if (!tg3_flag(tp, FW_TSO)) in tg3_load_tso_firmware()
3906 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_load_tso_firmware()
3910 length = end_address_of_bss - start_address_of_text. in tg3_load_tso_firmware()
3914 cpu_scratch_size = tp->fw_len; in tg3_load_tso_firmware()
3916 if (tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_load_tso_firmware()
3925 err = tg3_load_firmware_cpu(tp, cpu_base, in tg3_load_tso_firmware()
3932 err = tg3_pause_cpu_and_set_pc(tp, cpu_base, in tg3_load_tso_firmware()
3933 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3935 netdev_err(tp->dev, in tg3_load_tso_firmware()
3938 be32_to_cpu(fw_hdr->base_addr)); in tg3_load_tso_firmware()
3939 return -ENODEV; in tg3_load_tso_firmware()
3942 tg3_resume_cpu(tp, cpu_base); in tg3_load_tso_firmware()
3946 /* tp->lock is held. */
3947 static void __tg3_set_one_mac_addr(struct tg3 *tp, const u8 *mac_addr, in __tg3_set_one_mac_addr() argument
3960 index -= 4; in __tg3_set_one_mac_addr()
3966 /* tp->lock is held. */
3967 static void __tg3_set_mac_addr(struct tg3 *tp, bool skip_mac_1) in __tg3_set_mac_addr() argument
3975 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3978 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in __tg3_set_mac_addr()
3979 tg3_asic_rev(tp) == ASIC_REV_5704) { in __tg3_set_mac_addr()
3981 __tg3_set_one_mac_addr(tp, tp->dev->dev_addr, i); in __tg3_set_mac_addr()
3984 addr_high = (tp->dev->dev_addr[0] + in __tg3_set_mac_addr()
3985 tp->dev->dev_addr[1] + in __tg3_set_mac_addr()
3986 tp->dev->dev_addr[2] + in __tg3_set_mac_addr()
3987 tp->dev->dev_addr[3] + in __tg3_set_mac_addr()
3988 tp->dev->dev_addr[4] + in __tg3_set_mac_addr()
3989 tp->dev->dev_addr[5]) & in __tg3_set_mac_addr()
3994 static void tg3_enable_register_access(struct tg3 *tp) in tg3_enable_register_access() argument
4000 pci_write_config_dword(tp->pdev, in tg3_enable_register_access()
4001 TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl); in tg3_enable_register_access()
4004 static int tg3_power_up(struct tg3 *tp) in tg3_power_up() argument
4008 tg3_enable_register_access(tp); in tg3_power_up()
4010 err = pci_set_power_state(tp->pdev, PCI_D0); in tg3_power_up()
4013 tg3_pwrsrc_switch_to_vmain(tp); in tg3_power_up()
4015 netdev_err(tp->dev, "Transition to D0 failed\n"); in tg3_power_up()
4023 static int tg3_power_down_prepare(struct tg3 *tp) in tg3_power_down_prepare() argument
4028 tg3_enable_register_access(tp); in tg3_power_down_prepare()
4031 if (tg3_flag(tp, CLKREQ_BUG)) in tg3_power_down_prepare()
4032 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_power_down_prepare()
4039 device_should_wake = device_may_wakeup(&tp->pdev->dev) && in tg3_power_down_prepare()
4040 tg3_flag(tp, WOL_ENABLE); in tg3_power_down_prepare()
4042 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_power_down_prepare()
4044 if ((tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) && in tg3_power_down_prepare()
4045 !(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_power_down_prepare()
4050 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_power_down_prepare()
4052 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4054 tp->link_config.speed = phydev->speed; in tg3_power_down_prepare()
4055 tp->link_config.duplex = phydev->duplex; in tg3_power_down_prepare()
4056 tp->link_config.autoneg = phydev->autoneg; in tg3_power_down_prepare()
4058 &tp->link_config.advertising, in tg3_power_down_prepare()
4059 phydev->advertising); in tg3_power_down_prepare()
4069 if (tg3_flag(tp, ENABLE_ASF) || device_should_wake) { in tg3_power_down_prepare()
4070 if (tg3_flag(tp, WOL_SPEED_100MB)) { in tg3_power_down_prepare()
4083 linkmode_copy(phydev->advertising, advertising); in tg3_power_down_prepare()
4086 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask; in tg3_power_down_prepare()
4098 if (!(tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) in tg3_power_down_prepare()
4099 tp->phy_flags |= TG3_PHYFLG_IS_LOW_POWER; in tg3_power_down_prepare()
4101 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_power_down_prepare()
4102 tg3_setup_phy(tp, false); in tg3_power_down_prepare()
4105 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_prepare()
4110 } else if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
4115 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val); in tg3_power_down_prepare()
4121 if (tg3_flag(tp, WOL_CAP)) in tg3_power_down_prepare()
4122 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | in tg3_power_down_prepare()
4130 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_power_down_prepare()
4132 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_power_down_prepare()
4133 tg3_phy_auxctl_write(tp, in tg3_power_down_prepare()
4141 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_power_down_prepare()
4143 else if (tp->phy_flags & in tg3_power_down_prepare()
4145 if (tp->link_config.active_speed == SPEED_1000) in tg3_power_down_prepare()
4152 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY; in tg3_power_down_prepare()
4153 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_power_down_prepare()
4154 u32 speed = tg3_flag(tp, WOL_SPEED_100MB) ? in tg3_power_down_prepare()
4156 if (tg3_5700_link_polarity(tp, speed)) in tg3_power_down_prepare()
4165 if (!tg3_flag(tp, 5750_PLUS)) in tg3_power_down_prepare()
4166 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_power_down_prepare()
4169 if ((tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) && in tg3_power_down_prepare()
4170 (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE))) in tg3_power_down_prepare()
4173 if (tg3_flag(tp, ENABLE_APE)) in tg3_power_down_prepare()
4185 if (!tg3_flag(tp, WOL_SPEED_100MB) && in tg3_power_down_prepare()
4186 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4187 tg3_asic_rev(tp) == ASIC_REV_5701)) { in tg3_power_down_prepare()
4190 base_val = tp->pci_clock_ctrl; in tg3_power_down_prepare()
4196 } else if (tg3_flag(tp, 5780_CLASS) || in tg3_power_down_prepare()
4197 tg3_flag(tp, CPMU_PRESENT) || in tg3_power_down_prepare()
4198 tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_power_down_prepare()
4200 } else if (!(tg3_flag(tp, 5750_PLUS) && tg3_flag(tp, ENABLE_ASF))) { in tg3_power_down_prepare()
4203 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4204 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_power_down_prepare()
4209 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
4217 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1, in tg3_power_down_prepare()
4220 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2, in tg3_power_down_prepare()
4223 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_power_down_prepare()
4226 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_power_down_prepare()
4227 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_power_down_prepare()
4236 tp->pci_clock_ctrl | newbits3, 40); in tg3_power_down_prepare()
4240 if (!(device_should_wake) && !tg3_flag(tp, ENABLE_ASF)) in tg3_power_down_prepare()
4241 tg3_power_down_phy(tp, do_low_power); in tg3_power_down_prepare()
4243 tg3_frob_aux_power(tp, true); in tg3_power_down_prepare()
4246 if ((!tg3_flag(tp, IS_SSB_CORE)) && in tg3_power_down_prepare()
4247 ((tg3_chip_rev(tp) == CHIPREV_5750_AX) || in tg3_power_down_prepare()
4248 (tg3_chip_rev(tp) == CHIPREV_5750_BX))) { in tg3_power_down_prepare()
4253 if (!tg3_flag(tp, ENABLE_ASF)) { in tg3_power_down_prepare()
4256 err = tg3_nvram_lock(tp); in tg3_power_down_prepare()
4257 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_power_down_prepare()
4259 tg3_nvram_unlock(tp); in tg3_power_down_prepare()
4263 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN); in tg3_power_down_prepare()
4265 tg3_ape_driver_state_change(tp, RESET_KIND_SHUTDOWN); in tg3_power_down_prepare()
4270 static void tg3_power_down(struct tg3 *tp) in tg3_power_down() argument
4272 pci_wake_from_d3(tp->pdev, tg3_flag(tp, WOL_ENABLE)); in tg3_power_down()
4273 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_power_down()
4276 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u32 *speed, u8 *duplex) in tg3_aux_stat_to_speed_duplex() argument
4310 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_aux_stat_to_speed_duplex()
4323 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) in tg3_phy_autoneg_cfg() argument
4332 err = tg3_writephy(tp, MII_ADVERTISE, new_adv); in tg3_phy_autoneg_cfg()
4336 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_autoneg_cfg()
4339 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_phy_autoneg_cfg()
4340 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) in tg3_phy_autoneg_cfg()
4343 err = tg3_writephy(tp, MII_CTRL1000, new_adv); in tg3_phy_autoneg_cfg()
4348 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_autoneg_cfg()
4354 err = tg3_phy_toggle_auxctl_smdsp(tp, true); in tg3_phy_autoneg_cfg()
4359 /* Advertise 100-BaseTX EEE ability */ in tg3_phy_autoneg_cfg()
4362 /* Advertise 1000-BaseT EEE ability */ in tg3_phy_autoneg_cfg()
4366 if (!tp->eee.eee_enabled) { in tg3_phy_autoneg_cfg()
4368 tp->eee.advertised = 0; in tg3_phy_autoneg_cfg()
4370 tp->eee.advertised = advertise & in tg3_phy_autoneg_cfg()
4375 err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); in tg3_phy_autoneg_cfg()
4379 switch (tg3_asic_rev(tp)) { in tg3_phy_autoneg_cfg()
4389 tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); in tg3_phy_autoneg_cfg()
4393 if (!tg3_phydsp_read(tp, MII_TG3_DSP_CH34TP2, &val)) in tg3_phy_autoneg_cfg()
4394 tg3_phydsp_write(tp, MII_TG3_DSP_CH34TP2, val | in tg3_phy_autoneg_cfg()
4398 err2 = tg3_phy_toggle_auxctl_smdsp(tp, false); in tg3_phy_autoneg_cfg()
4407 static void tg3_phy_copper_begin(struct tg3 *tp) in tg3_phy_copper_begin() argument
4409 if (tp->link_config.autoneg == AUTONEG_ENABLE || in tg3_phy_copper_begin()
4410 (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_phy_copper_begin()
4413 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4414 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4417 if (tg3_flag(tp, WOL_SPEED_100MB)) in tg3_phy_copper_begin()
4420 if (tp->phy_flags & TG3_PHYFLG_1G_ON_VAUX_OK) { in tg3_phy_copper_begin()
4421 if (!(tp->phy_flags & in tg3_phy_copper_begin()
4429 adv = tp->link_config.advertising; in tg3_phy_copper_begin()
4430 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_phy_copper_begin()
4434 fc = tp->link_config.flowctrl; in tg3_phy_copper_begin()
4437 tg3_phy_autoneg_cfg(tp, adv, fc); in tg3_phy_copper_begin()
4439 if ((tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) && in tg3_phy_copper_begin()
4440 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)) { in tg3_phy_copper_begin()
4443 * link flap, we leave it untouched. in tg3_phy_copper_begin()
4448 tg3_writephy(tp, MII_BMCR, in tg3_phy_copper_begin()
4454 tp->link_config.active_speed = tp->link_config.speed; in tg3_phy_copper_begin()
4455 tp->link_config.active_duplex = tp->link_config.duplex; in tg3_phy_copper_begin()
4457 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_phy_copper_begin()
4462 tg3_writephy(tp, MII_ADVERTISE, ADVERTISE_ALL); in tg3_phy_copper_begin()
4466 switch (tp->link_config.speed) { in tg3_phy_copper_begin()
4480 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_phy_copper_begin()
4483 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) && in tg3_phy_copper_begin()
4485 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK); in tg3_phy_copper_begin()
4490 if (tg3_readphy(tp, MII_BMSR, &tmp) || in tg3_phy_copper_begin()
4491 tg3_readphy(tp, MII_BMSR, &tmp)) in tg3_phy_copper_begin()
4498 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_copper_begin()
4504 static int tg3_phy_pull_config(struct tg3 *tp) in tg3_phy_pull_config() argument
4509 err = tg3_readphy(tp, MII_BMCR, &val); in tg3_phy_pull_config()
4514 tp->link_config.autoneg = AUTONEG_DISABLE; in tg3_phy_pull_config()
4515 tp->link_config.advertising = 0; in tg3_phy_pull_config()
4516 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_phy_pull_config()
4518 err = -EIO; in tg3_phy_pull_config()
4522 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4525 tp->link_config.speed = SPEED_10; in tg3_phy_pull_config()
4528 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_phy_pull_config()
4531 tp->link_config.speed = SPEED_100; in tg3_phy_pull_config()
4534 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4535 tp->link_config.speed = SPEED_1000; in tg3_phy_pull_config()
4544 tp->link_config.duplex = DUPLEX_FULL; in tg3_phy_pull_config()
4546 tp->link_config.duplex = DUPLEX_HALF; in tg3_phy_pull_config()
4548 tp->link_config.flowctrl = FLOW_CTRL_RX | FLOW_CTRL_TX; in tg3_phy_pull_config()
4554 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_pull_config()
4555 tp->link_config.advertising = ADVERTISED_Autoneg; in tg3_phy_pull_config()
4556 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_phy_pull_config()
4558 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4561 err = tg3_readphy(tp, MII_ADVERTISE, &val); in tg3_phy_pull_config()
4566 tp->link_config.advertising |= adv | ADVERTISED_TP; in tg3_phy_pull_config()
4568 tp->link_config.flowctrl = tg3_decode_flowctrl_1000T(val); in tg3_phy_pull_config()
4570 tp->link_config.advertising |= ADVERTISED_FIBRE; in tg3_phy_pull_config()
4573 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_pull_config()
4576 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_phy_pull_config()
4577 err = tg3_readphy(tp, MII_CTRL1000, &val); in tg3_phy_pull_config()
4583 err = tg3_readphy(tp, MII_ADVERTISE, &val); in tg3_phy_pull_config()
4588 tp->link_config.flowctrl = adv; in tg3_phy_pull_config()
4594 tp->link_config.advertising |= adv; in tg3_phy_pull_config()
4601 static int tg3_init_5401phy_dsp(struct tg3 *tp) in tg3_init_5401phy_dsp() argument
4607 err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20); in tg3_init_5401phy_dsp()
4609 err |= tg3_phydsp_write(tp, 0x0012, 0x1804); in tg3_init_5401phy_dsp()
4610 err |= tg3_phydsp_write(tp, 0x0013, 0x1204); in tg3_init_5401phy_dsp()
4611 err |= tg3_phydsp_write(tp, 0x8006, 0x0132); in tg3_init_5401phy_dsp()
4612 err |= tg3_phydsp_write(tp, 0x8006, 0x0232); in tg3_init_5401phy_dsp()
4613 err |= tg3_phydsp_write(tp, 0x201f, 0x0a20); in tg3_init_5401phy_dsp()
4620 static bool tg3_phy_eee_config_ok(struct tg3 *tp) in tg3_phy_eee_config_ok() argument
4624 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) in tg3_phy_eee_config_ok()
4627 tg3_eee_pull_config(tp, &eee); in tg3_phy_eee_config_ok()
4629 if (tp->eee.eee_enabled) { in tg3_phy_eee_config_ok()
4630 if (tp->eee.advertised != eee.advertised || in tg3_phy_eee_config_ok()
4631 tp->eee.tx_lpi_timer != eee.tx_lpi_timer || in tg3_phy_eee_config_ok()
4632 tp->eee.tx_lpi_enabled != eee.tx_lpi_enabled) in tg3_phy_eee_config_ok()
4643 static bool tg3_phy_copper_an_config_ok(struct tg3 *tp, u32 *lcladv) in tg3_phy_copper_an_config_ok() argument
4647 advertising = tp->link_config.advertising; in tg3_phy_copper_an_config_ok()
4651 if (tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_phy_copper_an_config_ok()
4652 tgtadv |= mii_advertise_flowctrl(tp->link_config.flowctrl); in tg3_phy_copper_an_config_ok()
4656 if (tg3_readphy(tp, MII_ADVERTISE, lcladv)) in tg3_phy_copper_an_config_ok()
4662 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_an_config_ok()
4667 if (tg3_readphy(tp, MII_CTRL1000, &tg3_ctrl)) in tg3_phy_copper_an_config_ok()
4671 (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_phy_copper_an_config_ok()
4672 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0)) { in tg3_phy_copper_an_config_ok()
4687 static bool tg3_phy_copper_fetch_rmtadv(struct tg3 *tp, u32 *rmtadv) in tg3_phy_copper_fetch_rmtadv() argument
4691 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_copper_fetch_rmtadv()
4694 if (tg3_readphy(tp, MII_STAT1000, &val)) in tg3_phy_copper_fetch_rmtadv()
4700 if (tg3_readphy(tp, MII_LPA, rmtadv)) in tg3_phy_copper_fetch_rmtadv()
4704 tp->link_config.rmt_adv = lpeth; in tg3_phy_copper_fetch_rmtadv()
4709 static bool tg3_test_and_report_link_chg(struct tg3 *tp, bool curr_link_up) in tg3_test_and_report_link_chg() argument
4711 if (curr_link_up != tp->link_up) { in tg3_test_and_report_link_chg()
4713 netif_carrier_on(tp->dev); in tg3_test_and_report_link_chg()
4715 netif_carrier_off(tp->dev); in tg3_test_and_report_link_chg()
4716 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_test_and_report_link_chg()
4717 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_test_and_report_link_chg()
4720 tg3_link_report(tp); in tg3_test_and_report_link_chg()
4727 static void tg3_clear_mac_status(struct tg3 *tp) in tg3_clear_mac_status() argument
4739 static void tg3_setup_eee(struct tg3 *tp) in tg3_setup_eee() argument
4745 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) in tg3_setup_eee()
4754 (tp->eee.tx_lpi_enabled ? TG3_CPMU_EEEMD_LPI_IN_TX : 0) | in tg3_setup_eee()
4758 if (tg3_asic_rev(tp) != ASIC_REV_5717) in tg3_setup_eee()
4761 if (tg3_flag(tp, ENABLE_APE)) in tg3_setup_eee()
4764 tw32_f(TG3_CPMU_EEE_MODE, tp->eee.eee_enabled ? val : 0); in tg3_setup_eee()
4768 (tp->eee.tx_lpi_timer & 0xffff)); in tg3_setup_eee()
4775 static int tg3_setup_copper_phy(struct tg3 *tp, bool force_reset) in tg3_setup_copper_phy() argument
4784 tg3_clear_mac_status(tp); in tg3_setup_copper_phy()
4786 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) { in tg3_setup_copper_phy()
4788 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL)); in tg3_setup_copper_phy()
4792 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0); in tg3_setup_copper_phy()
4794 /* Some third-party PHYs need to be reset on link going in tg3_setup_copper_phy()
4797 if ((tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_setup_copper_phy()
4798 tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_setup_copper_phy()
4799 tg3_asic_rev(tp) == ASIC_REV_5705) && in tg3_setup_copper_phy()
4800 tp->link_up) { in tg3_setup_copper_phy()
4801 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4802 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4807 tg3_phy_reset(tp); in tg3_setup_copper_phy()
4809 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_setup_copper_phy()
4810 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4811 if (tg3_readphy(tp, MII_BMSR, &bmsr) || in tg3_setup_copper_phy()
4812 !tg3_flag(tp, INIT_COMPLETE)) in tg3_setup_copper_phy()
4816 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
4820 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4823 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4830 if ((tp->phy_id & TG3_PHY_ID_REV_MASK) == in tg3_setup_copper_phy()
4833 tp->link_config.active_speed == SPEED_1000) { in tg3_setup_copper_phy()
4834 err = tg3_phy_reset(tp); in tg3_setup_copper_phy()
4836 err = tg3_init_5401phy_dsp(tp); in tg3_setup_copper_phy()
4841 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_setup_copper_phy()
4842 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0) { in tg3_setup_copper_phy()
4844 tg3_writephy(tp, 0x15, 0x0a75); in tg3_setup_copper_phy()
4845 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4846 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68); in tg3_setup_copper_phy()
4847 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68); in tg3_setup_copper_phy()
4851 tg3_readphy(tp, MII_TG3_ISTAT, &val); in tg3_setup_copper_phy()
4852 tg3_readphy(tp, MII_TG3_ISTAT, &val); in tg3_setup_copper_phy()
4854 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) in tg3_setup_copper_phy()
4855 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG); in tg3_setup_copper_phy()
4856 else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_setup_copper_phy()
4857 tg3_writephy(tp, MII_TG3_IMASK, ~0); in tg3_setup_copper_phy()
4859 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_setup_copper_phy()
4860 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_setup_copper_phy()
4861 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1) in tg3_setup_copper_phy()
4862 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_setup_copper_phy()
4865 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0); in tg3_setup_copper_phy()
4871 tp->phy_flags &= ~TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4872 tp->link_config.rmt_adv = 0; in tg3_setup_copper_phy()
4874 if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) { in tg3_setup_copper_phy()
4875 err = tg3_phy_auxctl_read(tp, in tg3_setup_copper_phy()
4879 tg3_phy_auxctl_write(tp, in tg3_setup_copper_phy()
4888 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4889 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_setup_copper_phy()
4898 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat); in tg3_setup_copper_phy()
4901 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) && in tg3_setup_copper_phy()
4906 tg3_aux_stat_to_speed_duplex(tp, aux_stat, in tg3_setup_copper_phy()
4912 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_copper_phy()
4913 if (tg3_readphy(tp, MII_BMCR, &bmcr)) in tg3_setup_copper_phy()
4923 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4924 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4926 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_copper_phy()
4927 bool eee_config_ok = tg3_phy_eee_config_ok(tp); in tg3_setup_copper_phy()
4931 tg3_phy_copper_an_config_ok(tp, &lcl_adv) && in tg3_setup_copper_phy()
4932 tg3_phy_copper_fetch_rmtadv(tp, &rmt_adv)) in tg3_setup_copper_phy()
4936 * reset. If we have skipped a reset due to Link Flap in tg3_setup_copper_phy()
4940 (tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_setup_copper_phy()
4942 tg3_setup_eee(tp); in tg3_setup_copper_phy()
4943 tg3_phy_reset(tp); in tg3_setup_copper_phy()
4947 tp->link_config.speed == current_speed && in tg3_setup_copper_phy()
4948 tp->link_config.duplex == current_duplex) { in tg3_setup_copper_phy()
4954 tp->link_config.active_duplex == DUPLEX_FULL) { in tg3_setup_copper_phy()
4957 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_setup_copper_phy()
4965 if (!tg3_readphy(tp, reg, &val) && (val & bit)) in tg3_setup_copper_phy()
4966 tp->phy_flags |= TG3_PHYFLG_MDIX_STATE; in tg3_setup_copper_phy()
4968 tg3_setup_flow_control(tp, lcl_adv, rmt_adv); in tg3_setup_copper_phy()
4973 if (!current_link_up || (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER)) { in tg3_setup_copper_phy()
4974 tg3_phy_copper_begin(tp); in tg3_setup_copper_phy()
4976 if (tg3_flag(tp, ROBOSWITCH)) { in tg3_setup_copper_phy()
4981 tp->link_config.active_speed = current_speed; in tg3_setup_copper_phy()
4982 tp->link_config.active_duplex = current_duplex; in tg3_setup_copper_phy()
4985 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_copper_phy()
4986 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) || in tg3_setup_copper_phy()
4987 (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_setup_copper_phy()
4991 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_copper_phy()
4993 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
4994 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
4995 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
4997 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
4998 } else if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_setup_copper_phy()
4999 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_copper_phy()
5001 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_copper_phy()
5006 if (tg3_flag(tp, RGMII_MODE)) { in tg3_setup_copper_phy()
5010 if (tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5012 else if (tp->link_config.active_speed == SPEED_100) in tg3_setup_copper_phy()
5015 else if (tp->link_config.active_speed == SPEED_1000) in tg3_setup_copper_phy()
5023 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5024 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_copper_phy()
5025 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_copper_phy()
5027 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_setup_copper_phy()
5029 tg3_5700_link_polarity(tp, tp->link_config.active_speed)) in tg3_setup_copper_phy()
5030 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5032 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_setup_copper_phy()
5038 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 && in tg3_setup_copper_phy()
5039 tg3_chip_rev_id(tp) == CHIPREV_ID_5700_ALTIMA) { in tg3_setup_copper_phy()
5040 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL; in tg3_setup_copper_phy()
5041 tw32_f(MAC_MI_MODE, tp->mi_mode); in tg3_setup_copper_phy()
5045 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_copper_phy()
5048 tg3_phy_eee_adjust(tp, current_link_up); in tg3_setup_copper_phy()
5050 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_setup_copper_phy()
5058 if (tg3_asic_rev(tp) == ASIC_REV_5700 && in tg3_setup_copper_phy()
5060 tp->link_config.active_speed == SPEED_1000 && in tg3_setup_copper_phy()
5061 (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) { in tg3_setup_copper_phy()
5067 tg3_write_mem(tp, in tg3_setup_copper_phy()
5073 if (tg3_flag(tp, CLKREQ_BUG)) { in tg3_setup_copper_phy()
5074 if (tp->link_config.active_speed == SPEED_100 || in tg3_setup_copper_phy()
5075 tp->link_config.active_speed == SPEED_10) in tg3_setup_copper_phy()
5076 pcie_capability_clear_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5079 pcie_capability_set_word(tp->pdev, PCI_EXP_LNKCTL, in tg3_setup_copper_phy()
5083 tg3_test_and_report_link_chg(tp, current_link_up); in tg3_setup_copper_phy()
5148 #define ANEG_FAILED -1
5152 static int tg3_fiber_aneg_smachine(struct tg3 *tp, in tg3_fiber_aneg_smachine() argument
5160 if (ap->state == ANEG_STATE_UNKNOWN) { in tg3_fiber_aneg_smachine()
5161 ap->rxconfig = 0; in tg3_fiber_aneg_smachine()
5162 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5163 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5164 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5165 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5166 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5167 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5168 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5170 ap->cur_time++; in tg3_fiber_aneg_smachine()
5175 if (rx_cfg_reg != ap->ability_match_cfg) { in tg3_fiber_aneg_smachine()
5176 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5177 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5178 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5180 if (++ap->ability_match_count > 1) { in tg3_fiber_aneg_smachine()
5181 ap->ability_match = 1; in tg3_fiber_aneg_smachine()
5182 ap->ability_match_cfg = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5186 ap->ack_match = 1; in tg3_fiber_aneg_smachine()
5188 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5190 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5192 ap->idle_match = 1; in tg3_fiber_aneg_smachine()
5193 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5194 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5195 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5196 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5201 ap->rxconfig = rx_cfg_reg; in tg3_fiber_aneg_smachine()
5204 switch (ap->state) { in tg3_fiber_aneg_smachine()
5206 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN)) in tg3_fiber_aneg_smachine()
5207 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5211 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX); in tg3_fiber_aneg_smachine()
5212 if (ap->flags & MR_AN_ENABLE) { in tg3_fiber_aneg_smachine()
5213 ap->link_time = 0; in tg3_fiber_aneg_smachine()
5214 ap->cur_time = 0; in tg3_fiber_aneg_smachine()
5215 ap->ability_match_cfg = 0; in tg3_fiber_aneg_smachine()
5216 ap->ability_match_count = 0; in tg3_fiber_aneg_smachine()
5217 ap->ability_match = 0; in tg3_fiber_aneg_smachine()
5218 ap->idle_match = 0; in tg3_fiber_aneg_smachine()
5219 ap->ack_match = 0; in tg3_fiber_aneg_smachine()
5221 ap->state = ANEG_STATE_RESTART_INIT; in tg3_fiber_aneg_smachine()
5223 ap->state = ANEG_STATE_DISABLE_LINK_OK; in tg3_fiber_aneg_smachine()
5228 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5229 ap->flags &= ~(MR_NP_LOADED); in tg3_fiber_aneg_smachine()
5230 ap->txconfig = 0; in tg3_fiber_aneg_smachine()
5232 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5233 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5237 ap->state = ANEG_STATE_RESTART; in tg3_fiber_aneg_smachine()
5241 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5243 ap->state = ANEG_STATE_ABILITY_DETECT_INIT; in tg3_fiber_aneg_smachine()
5253 ap->flags &= ~(MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5254 ap->txconfig = ANEG_CFG_FD; in tg3_fiber_aneg_smachine()
5255 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_fiber_aneg_smachine()
5257 ap->txconfig |= ANEG_CFG_PS1; in tg3_fiber_aneg_smachine()
5259 ap->txconfig |= ANEG_CFG_PS2; in tg3_fiber_aneg_smachine()
5260 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5261 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5262 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5265 ap->state = ANEG_STATE_ABILITY_DETECT; in tg3_fiber_aneg_smachine()
5269 if (ap->ability_match != 0 && ap->rxconfig != 0) in tg3_fiber_aneg_smachine()
5270 ap->state = ANEG_STATE_ACK_DETECT_INIT; in tg3_fiber_aneg_smachine()
5274 ap->txconfig |= ANEG_CFG_ACK; in tg3_fiber_aneg_smachine()
5275 tw32(MAC_TX_AUTO_NEG, ap->txconfig); in tg3_fiber_aneg_smachine()
5276 tp->mac_mode |= MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5277 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5280 ap->state = ANEG_STATE_ACK_DETECT; in tg3_fiber_aneg_smachine()
5284 if (ap->ack_match != 0) { in tg3_fiber_aneg_smachine()
5285 if ((ap->rxconfig & ~ANEG_CFG_ACK) == in tg3_fiber_aneg_smachine()
5286 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) { in tg3_fiber_aneg_smachine()
5287 ap->state = ANEG_STATE_COMPLETE_ACK_INIT; in tg3_fiber_aneg_smachine()
5289 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5291 } else if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5292 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5293 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5298 if (ap->rxconfig & ANEG_CFG_INVAL) { in tg3_fiber_aneg_smachine()
5302 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX | in tg3_fiber_aneg_smachine()
5311 if (ap->rxconfig & ANEG_CFG_FD) in tg3_fiber_aneg_smachine()
5312 ap->flags |= MR_LP_ADV_FULL_DUPLEX; in tg3_fiber_aneg_smachine()
5313 if (ap->rxconfig & ANEG_CFG_HD) in tg3_fiber_aneg_smachine()
5314 ap->flags |= MR_LP_ADV_HALF_DUPLEX; in tg3_fiber_aneg_smachine()
5315 if (ap->rxconfig & ANEG_CFG_PS1) in tg3_fiber_aneg_smachine()
5316 ap->flags |= MR_LP_ADV_SYM_PAUSE; in tg3_fiber_aneg_smachine()
5317 if (ap->rxconfig & ANEG_CFG_PS2) in tg3_fiber_aneg_smachine()
5318 ap->flags |= MR_LP_ADV_ASYM_PAUSE; in tg3_fiber_aneg_smachine()
5319 if (ap->rxconfig & ANEG_CFG_RF1) in tg3_fiber_aneg_smachine()
5320 ap->flags |= MR_LP_ADV_REMOTE_FAULT1; in tg3_fiber_aneg_smachine()
5321 if (ap->rxconfig & ANEG_CFG_RF2) in tg3_fiber_aneg_smachine()
5322 ap->flags |= MR_LP_ADV_REMOTE_FAULT2; in tg3_fiber_aneg_smachine()
5323 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5324 ap->flags |= MR_LP_ADV_NEXT_PAGE; in tg3_fiber_aneg_smachine()
5326 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5328 ap->flags ^= (MR_TOGGLE_TX); in tg3_fiber_aneg_smachine()
5329 if (ap->rxconfig & 0x0008) in tg3_fiber_aneg_smachine()
5330 ap->flags |= MR_TOGGLE_RX; in tg3_fiber_aneg_smachine()
5331 if (ap->rxconfig & ANEG_CFG_NP) in tg3_fiber_aneg_smachine()
5332 ap->flags |= MR_NP_RX; in tg3_fiber_aneg_smachine()
5333 ap->flags |= MR_PAGE_RX; in tg3_fiber_aneg_smachine()
5335 ap->state = ANEG_STATE_COMPLETE_ACK; in tg3_fiber_aneg_smachine()
5340 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5341 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5342 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5345 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5347 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) { in tg3_fiber_aneg_smachine()
5348 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5350 if ((ap->txconfig & ANEG_CFG_NP) == 0 && in tg3_fiber_aneg_smachine()
5351 !(ap->flags & MR_NP_RX)) { in tg3_fiber_aneg_smachine()
5352 ap->state = ANEG_STATE_IDLE_DETECT_INIT; in tg3_fiber_aneg_smachine()
5361 ap->link_time = ap->cur_time; in tg3_fiber_aneg_smachine()
5362 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in tg3_fiber_aneg_smachine()
5363 tw32_f(MAC_MODE, tp->mac_mode); in tg3_fiber_aneg_smachine()
5366 ap->state = ANEG_STATE_IDLE_DETECT; in tg3_fiber_aneg_smachine()
5371 if (ap->ability_match != 0 && in tg3_fiber_aneg_smachine()
5372 ap->rxconfig == 0) { in tg3_fiber_aneg_smachine()
5373 ap->state = ANEG_STATE_AN_ENABLE; in tg3_fiber_aneg_smachine()
5376 delta = ap->cur_time - ap->link_time; in tg3_fiber_aneg_smachine()
5379 ap->state = ANEG_STATE_LINK_OK; in tg3_fiber_aneg_smachine()
5384 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK); in tg3_fiber_aneg_smachine()
5404 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags) in fiber_autoneg() argument
5414 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK; in fiber_autoneg()
5418 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS); in fiber_autoneg()
5427 status = tg3_fiber_aneg_smachine(tp, &aninfo); in fiber_autoneg()
5434 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS; in fiber_autoneg()
5435 tw32_f(MAC_MODE, tp->mac_mode); in fiber_autoneg()
5449 static void tg3_init_bcm8002(struct tg3 *tp) in tg3_init_bcm8002() argument
5454 /* Reset when initting first time or we have a link. */ in tg3_init_bcm8002()
5455 if (tg3_flag(tp, INIT_COMPLETE) && in tg3_init_bcm8002()
5460 tg3_writephy(tp, 0x16, 0x8007); in tg3_init_bcm8002()
5463 tg3_writephy(tp, MII_BMCR, BMCR_RESET); in tg3_init_bcm8002()
5471 tg3_writephy(tp, 0x10, 0x8411); in tg3_init_bcm8002()
5473 /* Enable auto-lock and comdet, select txclk for tx. */ in tg3_init_bcm8002()
5474 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5476 tg3_writephy(tp, 0x18, 0x00a0); in tg3_init_bcm8002()
5477 tg3_writephy(tp, 0x16, 0x41ff); in tg3_init_bcm8002()
5480 tg3_writephy(tp, 0x13, 0x0400); in tg3_init_bcm8002()
5482 tg3_writephy(tp, 0x13, 0x0000); in tg3_init_bcm8002()
5484 tg3_writephy(tp, 0x11, 0x0a50); in tg3_init_bcm8002()
5486 tg3_writephy(tp, 0x11, 0x0a10); in tg3_init_bcm8002()
5496 tg3_writephy(tp, 0x10, 0x8011); in tg3_init_bcm8002()
5499 static bool tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status) in tg3_setup_fiber_hw_autoneg() argument
5512 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A0 && in tg3_setup_fiber_hw_autoneg()
5513 tg3_chip_rev_id(tp) != CHIPREV_ID_5704_A1) { in tg3_setup_fiber_hw_autoneg()
5518 /* preserve bits 0-11,13,14 for signal pre-emphasis */ in tg3_setup_fiber_hw_autoneg()
5519 /* preserve bits 20-23 for voltage regulator */ in tg3_setup_fiber_hw_autoneg()
5525 if (tp->link_config.autoneg != AUTONEG_ENABLE) { in tg3_setup_fiber_hw_autoneg()
5540 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5546 /* Want auto-negotiation. */ in tg3_setup_fiber_hw_autoneg()
5549 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_hw_autoneg()
5556 if ((tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT) && in tg3_setup_fiber_hw_autoneg()
5557 tp->serdes_counter && in tg3_setup_fiber_hw_autoneg()
5561 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5572 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5573 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5593 tp->link_config.rmt_adv = in tg3_setup_fiber_hw_autoneg()
5596 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_hw_autoneg()
5598 tp->serdes_counter = 0; in tg3_setup_fiber_hw_autoneg()
5599 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5601 if (tp->serdes_counter) in tg3_setup_fiber_hw_autoneg()
5602 tp->serdes_counter--; in tg3_setup_fiber_hw_autoneg()
5618 /* Link parallel detection - link is up */ in tg3_setup_fiber_hw_autoneg()
5624 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_hw_autoneg()
5626 tp->phy_flags |= in tg3_setup_fiber_hw_autoneg()
5628 tp->serdes_counter = in tg3_setup_fiber_hw_autoneg()
5635 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S; in tg3_setup_fiber_hw_autoneg()
5636 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_hw_autoneg()
5643 static bool tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) in tg3_setup_fiber_by_hand() argument
5650 if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_by_hand()
5654 if (fiber_autoneg(tp, &txflags, &rxflags)) { in tg3_setup_fiber_by_hand()
5667 tp->link_config.rmt_adv = in tg3_setup_fiber_by_hand()
5670 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_by_hand()
5692 tg3_setup_flow_control(tp, 0, 0); in tg3_setup_fiber_by_hand()
5694 /* Forcing 1000FD link up. */ in tg3_setup_fiber_by_hand()
5697 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS)); in tg3_setup_fiber_by_hand()
5700 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_by_hand()
5708 static int tg3_setup_fiber_phy(struct tg3 *tp, bool force_reset) in tg3_setup_fiber_phy() argument
5717 orig_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5718 orig_active_speed = tp->link_config.active_speed; in tg3_setup_fiber_phy()
5719 orig_active_duplex = tp->link_config.active_duplex; in tg3_setup_fiber_phy()
5721 if (!tg3_flag(tp, HW_AUTONEG) && in tg3_setup_fiber_phy()
5722 tp->link_up && in tg3_setup_fiber_phy()
5723 tg3_flag(tp, INIT_COMPLETE)) { in tg3_setup_fiber_phy()
5739 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX); in tg3_setup_fiber_phy()
5740 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; in tg3_setup_fiber_phy()
5741 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5744 if (tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_setup_fiber_phy()
5745 tg3_init_bcm8002(tp); in tg3_setup_fiber_phy()
5747 /* Enable link change event even when serdes polling. */ in tg3_setup_fiber_phy()
5751 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_phy()
5754 if (tg3_flag(tp, HW_AUTONEG)) in tg3_setup_fiber_phy()
5755 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status); in tg3_setup_fiber_phy()
5757 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status); in tg3_setup_fiber_phy()
5759 tp->napi[0].hw_status->status = in tg3_setup_fiber_phy()
5761 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG)); in tg3_setup_fiber_phy()
5776 if (tp->link_config.autoneg == AUTONEG_ENABLE && in tg3_setup_fiber_phy()
5777 tp->serdes_counter == 0) { in tg3_setup_fiber_phy()
5778 tw32_f(MAC_MODE, (tp->mac_mode | in tg3_setup_fiber_phy()
5781 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_phy()
5786 tp->link_config.active_speed = SPEED_1000; in tg3_setup_fiber_phy()
5787 tp->link_config.active_duplex = DUPLEX_FULL; in tg3_setup_fiber_phy()
5788 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5792 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_setup_fiber_phy()
5793 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_setup_fiber_phy()
5794 tw32(MAC_LED_CTRL, (tp->led_ctrl | in tg3_setup_fiber_phy()
5799 if (!tg3_test_and_report_link_chg(tp, current_link_up)) { in tg3_setup_fiber_phy()
5800 u32 now_pause_cfg = tp->link_config.active_flowctrl; in tg3_setup_fiber_phy()
5802 orig_active_speed != tp->link_config.active_speed || in tg3_setup_fiber_phy()
5803 orig_active_duplex != tp->link_config.active_duplex) in tg3_setup_fiber_phy()
5804 tg3_link_report(tp); in tg3_setup_fiber_phy()
5810 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, bool force_reset) in tg3_setup_fiber_mii_phy() argument
5819 if ((tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_setup_fiber_mii_phy()
5820 tg3_asic_rev(tp) == ASIC_REV_5720) && in tg3_setup_fiber_mii_phy()
5821 !tg3_readphy(tp, SERDES_TG3_1000X_STATUS, &sgsr) && in tg3_setup_fiber_mii_phy()
5825 tg3_phy_reset(tp); in tg3_setup_fiber_mii_phy()
5827 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK; in tg3_setup_fiber_mii_phy()
5830 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5835 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5838 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5841 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_setup_fiber_mii_phy()
5850 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5853 tg3_clear_mac_status(tp); in tg3_setup_fiber_mii_phy()
5858 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_setup_fiber_mii_phy()
5859 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5862 tg3_clear_mac_status(tp); in tg3_setup_fiber_mii_phy()
5865 tg3_phy_reset(tp); in tg3_setup_fiber_mii_phy()
5867 tp->link_config.rmt_adv = 0; in tg3_setup_fiber_mii_phy()
5869 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5870 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5871 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
5878 err |= tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_setup_fiber_mii_phy()
5880 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset && in tg3_setup_fiber_mii_phy()
5881 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_setup_fiber_mii_phy()
5882 /* do nothing, just check for link up at the end */ in tg3_setup_fiber_mii_phy()
5883 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) { in tg3_setup_fiber_mii_phy()
5886 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5892 newadv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl); in tg3_setup_fiber_mii_phy()
5893 newadv |= ethtool_adv_to_mii_adv_x(tp->link_config.advertising); in tg3_setup_fiber_mii_phy()
5896 tg3_writephy(tp, MII_ADVERTISE, newadv); in tg3_setup_fiber_mii_phy()
5898 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_setup_fiber_mii_phy()
5901 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S; in tg3_setup_fiber_mii_phy()
5902 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5912 if (tp->link_config.duplex == DUPLEX_FULL) in tg3_setup_fiber_mii_phy()
5922 if (tp->link_up) { in tg3_setup_fiber_mii_phy()
5925 err |= tg3_readphy(tp, MII_ADVERTISE, &adv); in tg3_setup_fiber_mii_phy()
5929 tg3_writephy(tp, MII_ADVERTISE, adv); in tg3_setup_fiber_mii_phy()
5930 tg3_writephy(tp, MII_BMCR, bmcr | in tg3_setup_fiber_mii_phy()
5934 tg3_carrier_off(tp); in tg3_setup_fiber_mii_phy()
5936 tg3_writephy(tp, MII_BMCR, new_bmcr); in tg3_setup_fiber_mii_phy()
5938 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5939 err |= tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_setup_fiber_mii_phy()
5940 if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_setup_fiber_mii_phy()
5946 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_setup_fiber_mii_phy()
5964 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv); in tg3_setup_fiber_mii_phy()
5965 err |= tg3_readphy(tp, MII_LPA, &remote_adv); in tg3_setup_fiber_mii_phy()
5974 tp->link_config.rmt_adv = in tg3_setup_fiber_mii_phy()
5976 } else if (!tg3_flag(tp, 5780_CLASS)) { in tg3_setup_fiber_mii_phy()
5977 /* Link is up via parallel detect */ in tg3_setup_fiber_mii_phy()
5986 tg3_setup_flow_control(tp, local_adv, remote_adv); in tg3_setup_fiber_mii_phy()
5988 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5989 if (tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_fiber_mii_phy()
5990 tp->mac_mode |= MAC_MODE_HALF_DUPLEX; in tg3_setup_fiber_mii_phy()
5992 tw32_f(MAC_MODE, tp->mac_mode); in tg3_setup_fiber_mii_phy()
5997 tp->link_config.active_speed = current_speed; in tg3_setup_fiber_mii_phy()
5998 tp->link_config.active_duplex = current_duplex; in tg3_setup_fiber_mii_phy()
6000 tg3_test_and_report_link_chg(tp, current_link_up); in tg3_setup_fiber_mii_phy()
6004 static void tg3_serdes_parallel_detect(struct tg3 *tp) in tg3_serdes_parallel_detect() argument
6006 if (tp->serdes_counter) { in tg3_serdes_parallel_detect()
6008 tp->serdes_counter--; in tg3_serdes_parallel_detect()
6012 if (!tp->link_up && in tg3_serdes_parallel_detect()
6013 (tp->link_config.autoneg == AUTONEG_ENABLE)) { in tg3_serdes_parallel_detect()
6016 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_serdes_parallel_detect()
6021 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x7c00); in tg3_serdes_parallel_detect()
6022 tg3_readphy(tp, MII_TG3_MISC_SHDW, &phy1); in tg3_serdes_parallel_detect()
6025 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6027 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6028 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6032 * config code words, link is up by parallel in tg3_serdes_parallel_detect()
6038 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_serdes_parallel_detect()
6039 tp->phy_flags |= TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6042 } else if (tp->link_up && in tg3_serdes_parallel_detect()
6043 (tp->link_config.autoneg == AUTONEG_ENABLE) && in tg3_serdes_parallel_detect()
6044 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT)) { in tg3_serdes_parallel_detect()
6048 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, in tg3_serdes_parallel_detect()
6050 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &phy2); in tg3_serdes_parallel_detect()
6055 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_serdes_parallel_detect()
6056 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE); in tg3_serdes_parallel_detect()
6058 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_serdes_parallel_detect()
6064 static int tg3_setup_phy(struct tg3 *tp, bool force_reset) in tg3_setup_phy() argument
6069 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_setup_phy()
6070 err = tg3_setup_fiber_phy(tp, force_reset); in tg3_setup_phy()
6071 else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_setup_phy()
6072 err = tg3_setup_fiber_mii_phy(tp, force_reset); in tg3_setup_phy()
6074 err = tg3_setup_copper_phy(tp, force_reset); in tg3_setup_phy()
6076 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { in tg3_setup_phy()
6094 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_setup_phy()
6095 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_setup_phy()
6100 if (tp->link_config.active_speed == SPEED_1000 && in tg3_setup_phy()
6101 tp->link_config.active_duplex == DUPLEX_HALF) in tg3_setup_phy()
6108 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_setup_phy()
6109 if (tp->link_up) { in tg3_setup_phy()
6111 tp->coal.stats_block_coalesce_usecs); in tg3_setup_phy()
6117 if (tg3_flag(tp, ASPM_WORKAROUND)) { in tg3_setup_phy()
6119 if (!tp->link_up) in tg3_setup_phy()
6121 tp->pwrmgmt_thresh; in tg3_setup_phy()
6130 /* tp->lock must be held */
6131 static u64 tg3_refclk_read(struct tg3 *tp, struct ptp_system_timestamp *sts) in tg3_refclk_read() argument
6143 /* tp->lock must be held */
6144 static void tg3_refclk_write(struct tg3 *tp, u64 newval) in tg3_refclk_write() argument
6154 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync);
6155 static inline void tg3_full_unlock(struct tg3 *tp);
6158 struct tg3 *tp = netdev_priv(dev); in tg3_get_ts_info() local
6160 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | in tg3_get_ts_info()
6164 if (tg3_flag(tp, PTP_CAPABLE)) { in tg3_get_ts_info()
6165 info->so_timestamping |= SOF_TIMESTAMPING_TX_HARDWARE | in tg3_get_ts_info()
6170 if (tp->ptp_clock) in tg3_get_ts_info()
6171 info->phc_index = ptp_clock_index(tp->ptp_clock); in tg3_get_ts_info()
6173 info->phc_index = -1; in tg3_get_ts_info()
6175 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON); in tg3_get_ts_info()
6177 info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) | in tg3_get_ts_info()
6186 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_adjfine() local
6197 tg3_full_lock(tp, 0); in tg3_ptp_adjfine()
6207 tg3_full_unlock(tp); in tg3_ptp_adjfine()
6214 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_adjtime() local
6216 tg3_full_lock(tp, 0); in tg3_ptp_adjtime()
6217 tp->ptp_adjust += delta; in tg3_ptp_adjtime()
6218 tg3_full_unlock(tp); in tg3_ptp_adjtime()
6227 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_gettimex() local
6229 tg3_full_lock(tp, 0); in tg3_ptp_gettimex()
6230 ns = tg3_refclk_read(tp, sts); in tg3_ptp_gettimex()
6231 ns += tp->ptp_adjust; in tg3_ptp_gettimex()
6232 tg3_full_unlock(tp); in tg3_ptp_gettimex()
6243 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_settime() local
6247 tg3_full_lock(tp, 0); in tg3_ptp_settime()
6248 tg3_refclk_write(tp, ns); in tg3_ptp_settime()
6249 tp->ptp_adjust = 0; in tg3_ptp_settime()
6250 tg3_full_unlock(tp); in tg3_ptp_settime()
6258 struct tg3 *tp = container_of(ptp, struct tg3, ptp_info); in tg3_ptp_enable() local
6262 switch (rq->type) { in tg3_ptp_enable()
6265 if (rq->perout.flags) in tg3_ptp_enable()
6266 return -EOPNOTSUPP; in tg3_ptp_enable()
6268 if (rq->perout.index != 0) in tg3_ptp_enable()
6269 return -EINVAL; in tg3_ptp_enable()
6271 tg3_full_lock(tp, 0); in tg3_ptp_enable()
6278 nsec = rq->perout.start.sec * 1000000000ULL + in tg3_ptp_enable()
6279 rq->perout.start.nsec; in tg3_ptp_enable()
6281 if (rq->perout.period.sec || rq->perout.period.nsec) { in tg3_ptp_enable()
6282 netdev_warn(tp->dev, in tg3_ptp_enable()
6283 "Device supports only a one-shot timesync output, period must be 0\n"); in tg3_ptp_enable()
6284 rval = -EINVAL; in tg3_ptp_enable()
6289 netdev_warn(tp->dev, in tg3_ptp_enable()
6291 rval = -EINVAL; in tg3_ptp_enable()
6308 tg3_full_unlock(tp); in tg3_ptp_enable()
6315 return -EOPNOTSUPP; in tg3_ptp_enable()
6334 static void tg3_hwclock_to_timestamp(struct tg3 *tp, u64 hwclock, in tg3_hwclock_to_timestamp() argument
6338 timestamp->hwtstamp = ns_to_ktime((hwclock & TG3_TSTAMP_MASK) + in tg3_hwclock_to_timestamp()
6339 tp->ptp_adjust); in tg3_hwclock_to_timestamp()
6342 /* tp->lock must be held */
6343 static void tg3_ptp_init(struct tg3 *tp) in tg3_ptp_init() argument
6345 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_ptp_init()
6349 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real())); in tg3_ptp_init()
6350 tp->ptp_adjust = 0; in tg3_ptp_init()
6351 tp->ptp_info = tg3_ptp_caps; in tg3_ptp_init()
6354 /* tp->lock must be held */
6355 static void tg3_ptp_resume(struct tg3 *tp) in tg3_ptp_resume() argument
6357 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_ptp_resume()
6360 tg3_refclk_write(tp, ktime_to_ns(ktime_get_real()) + tp->ptp_adjust); in tg3_ptp_resume()
6361 tp->ptp_adjust = 0; in tg3_ptp_resume()
6364 static void tg3_ptp_fini(struct tg3 *tp) in tg3_ptp_fini() argument
6366 if (!tg3_flag(tp, PTP_CAPABLE) || !tp->ptp_clock) in tg3_ptp_fini()
6369 ptp_clock_unregister(tp->ptp_clock); in tg3_ptp_fini()
6370 tp->ptp_clock = NULL; in tg3_ptp_fini()
6371 tp->ptp_adjust = 0; in tg3_ptp_fini()
6374 static inline int tg3_irq_sync(struct tg3 *tp) in tg3_irq_sync() argument
6376 return tp->irq_sync; in tg3_irq_sync()
6379 static inline void tg3_rd32_loop(struct tg3 *tp, u32 *dst, u32 off, u32 len) in tg3_rd32_loop() argument
6388 static void tg3_dump_legacy_regs(struct tg3 *tp, u32 *regs) in tg3_dump_legacy_regs() argument
6390 tg3_rd32_loop(tp, regs, TG3PCI_VENDOR, 0xb0); in tg3_dump_legacy_regs()
6391 tg3_rd32_loop(tp, regs, MAILBOX_INTERRUPT_0, 0x200); in tg3_dump_legacy_regs()
6392 tg3_rd32_loop(tp, regs, MAC_MODE, 0x4f0); in tg3_dump_legacy_regs()
6393 tg3_rd32_loop(tp, regs, SNDDATAI_MODE, 0xe0); in tg3_dump_legacy_regs()
6394 tg3_rd32_loop(tp, regs, SNDDATAC_MODE, 0x04); in tg3_dump_legacy_regs()
6395 tg3_rd32_loop(tp, regs, SNDBDS_MODE, 0x80); in tg3_dump_legacy_regs()
6396 tg3_rd32_loop(tp, regs, SNDBDI_MODE, 0x48); in tg3_dump_legacy_regs()
6397 tg3_rd32_loop(tp, regs, SNDBDC_MODE, 0x04); in tg3_dump_legacy_regs()
6398 tg3_rd32_loop(tp, regs, RCVLPC_MODE, 0x20); in tg3_dump_legacy_regs()
6399 tg3_rd32_loop(tp, regs, RCVLPC_SELLST_BASE, 0x15c); in tg3_dump_legacy_regs()
6400 tg3_rd32_loop(tp, regs, RCVDBDI_MODE, 0x0c); in tg3_dump_legacy_regs()
6401 tg3_rd32_loop(tp, regs, RCVDBDI_JUMBO_BD, 0x3c); in tg3_dump_legacy_regs()
6402 tg3_rd32_loop(tp, regs, RCVDBDI_BD_PROD_IDX_0, 0x44); in tg3_dump_legacy_regs()
6403 tg3_rd32_loop(tp, regs, RCVDCC_MODE, 0x04); in tg3_dump_legacy_regs()
6404 tg3_rd32_loop(tp, regs, RCVBDI_MODE, 0x20); in tg3_dump_legacy_regs()
6405 tg3_rd32_loop(tp, regs, RCVCC_MODE, 0x14); in tg3_dump_legacy_regs()
6406 tg3_rd32_loop(tp, regs, RCVLSC_MODE, 0x08); in tg3_dump_legacy_regs()
6407 tg3_rd32_loop(tp, regs, MBFREE_MODE, 0x08); in tg3_dump_legacy_regs()
6408 tg3_rd32_loop(tp, regs, HOSTCC_MODE, 0x100); in tg3_dump_legacy_regs()
6410 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_dump_legacy_regs()
6411 tg3_rd32_loop(tp, regs, HOSTCC_RXCOL_TICKS_VEC1, 0x180); in tg3_dump_legacy_regs()
6413 tg3_rd32_loop(tp, regs, MEMARB_MODE, 0x10); in tg3_dump_legacy_regs()
6414 tg3_rd32_loop(tp, regs, BUFMGR_MODE, 0x58); in tg3_dump_legacy_regs()
6415 tg3_rd32_loop(tp, regs, RDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6416 tg3_rd32_loop(tp, regs, WDMAC_MODE, 0x08); in tg3_dump_legacy_regs()
6417 tg3_rd32_loop(tp, regs, RX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6418 tg3_rd32_loop(tp, regs, RX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6419 tg3_rd32_loop(tp, regs, RX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6420 tg3_rd32_loop(tp, regs, RX_CPU_HWBKPT, 0x04); in tg3_dump_legacy_regs()
6422 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_dump_legacy_regs()
6423 tg3_rd32_loop(tp, regs, TX_CPU_MODE, 0x04); in tg3_dump_legacy_regs()
6424 tg3_rd32_loop(tp, regs, TX_CPU_STATE, 0x04); in tg3_dump_legacy_regs()
6425 tg3_rd32_loop(tp, regs, TX_CPU_PGMCTR, 0x04); in tg3_dump_legacy_regs()
6428 tg3_rd32_loop(tp, regs, GRCMBOX_INTERRUPT_0, 0x110); in tg3_dump_legacy_regs()
6429 tg3_rd32_loop(tp, regs, FTQ_RESET, 0x120); in tg3_dump_legacy_regs()
6430 tg3_rd32_loop(tp, regs, MSGINT_MODE, 0x0c); in tg3_dump_legacy_regs()
6431 tg3_rd32_loop(tp, regs, DMAC_MODE, 0x04); in tg3_dump_legacy_regs()
6432 tg3_rd32_loop(tp, regs, GRC_MODE, 0x4c); in tg3_dump_legacy_regs()
6434 if (tg3_flag(tp, NVRAM)) in tg3_dump_legacy_regs()
6435 tg3_rd32_loop(tp, regs, NVRAM_CMD, 0x24); in tg3_dump_legacy_regs()
6438 static void tg3_dump_state(struct tg3 *tp) in tg3_dump_state() argument
6446 if (tp->pdev->error_state != pci_channel_io_normal) { in tg3_dump_state()
6447 netdev_err(tp->dev, "PCI channel ERROR!\n"); in tg3_dump_state()
6455 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_dump_state()
6460 tg3_dump_legacy_regs(tp, regs); in tg3_dump_state()
6467 netdev_err(tp->dev, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", in tg3_dump_state()
6474 for (i = 0; i < tp->irq_cnt; i++) { in tg3_dump_state()
6475 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_dump_state()
6478 netdev_err(tp->dev, in tg3_dump_state()
6481 tnapi->hw_status->status, in tg3_dump_state()
6482 tnapi->hw_status->status_tag, in tg3_dump_state()
6483 tnapi->hw_status->rx_jumbo_consumer, in tg3_dump_state()
6484 tnapi->hw_status->rx_consumer, in tg3_dump_state()
6485 tnapi->hw_status->rx_mini_consumer, in tg3_dump_state()
6486 tnapi->hw_status->idx[0].rx_producer, in tg3_dump_state()
6487 tnapi->hw_status->idx[0].tx_consumer); in tg3_dump_state()
6489 netdev_err(tp->dev, in tg3_dump_state()
6492 tnapi->last_tag, tnapi->last_irq_tag, in tg3_dump_state()
6493 tnapi->tx_prod, tnapi->tx_cons, tnapi->tx_pending, in tg3_dump_state()
6494 tnapi->rx_rcb_ptr, in tg3_dump_state()
6495 tnapi->prodring.rx_std_prod_idx, in tg3_dump_state()
6496 tnapi->prodring.rx_std_cons_idx, in tg3_dump_state()
6497 tnapi->prodring.rx_jmb_prod_idx, in tg3_dump_state()
6498 tnapi->prodring.rx_jmb_cons_idx); in tg3_dump_state()
6502 /* This is called whenever we suspect that the system chipset is re-
6508 static void tg3_tx_recover(struct tg3 *tp) in tg3_tx_recover() argument
6510 BUG_ON(tg3_flag(tp, MBOX_WRITE_REORDER) || in tg3_tx_recover()
6511 tp->write32_tx_mbox == tg3_write_indirect_mbox); in tg3_tx_recover()
6513 netdev_warn(tp->dev, in tg3_tx_recover()
6514 "The system may be re-ordering memory-mapped I/O " in tg3_tx_recover()
6519 tg3_flag_set(tp, TX_RECOVERY_PENDING); in tg3_tx_recover()
6526 return tnapi->tx_pending - in tg3_tx_avail()
6527 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1)); in tg3_tx_avail()
6536 struct tg3 *tp = tnapi->tp; in tg3_tx() local
6537 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_tx()
6538 u32 sw_idx = tnapi->tx_cons; in tg3_tx()
6540 int index = tnapi - tp->napi; in tg3_tx()
6543 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx()
6544 index--; in tg3_tx()
6546 txq = netdev_get_tx_queue(tp->dev, index); in tg3_tx()
6549 struct tg3_tx_ring_info *ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6550 struct sk_buff *skb = ri->skb; in tg3_tx()
6554 tg3_tx_recover(tp); in tg3_tx()
6558 if (tnapi->tx_ring[sw_idx].len_flags & TXD_FLAG_HWTSTAMP) { in tg3_tx()
6563 tg3_hwclock_to_timestamp(tp, hwclock, ×tamp); in tg3_tx()
6568 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), in tg3_tx()
6571 ri->skb = NULL; in tg3_tx()
6573 while (ri->fragmented) { in tg3_tx()
6574 ri->fragmented = false; in tg3_tx()
6576 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6581 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { in tg3_tx()
6582 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6583 if (unlikely(ri->skb != NULL || sw_idx == hw_idx)) in tg3_tx()
6586 dma_unmap_page(&tp->pdev->dev, in tg3_tx()
6588 skb_frag_size(&skb_shinfo(skb)->frags[i]), in tg3_tx()
6591 while (ri->fragmented) { in tg3_tx()
6592 ri->fragmented = false; in tg3_tx()
6594 ri = &tnapi->tx_buffers[sw_idx]; in tg3_tx()
6601 bytes_compl += skb->len; in tg3_tx()
6606 tg3_tx_recover(tp); in tg3_tx()
6613 tnapi->tx_cons = sw_idx; in tg3_tx()
6640 static void tg3_rx_data_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz) in tg3_rx_data_free() argument
6642 unsigned int skb_size = SKB_DATA_ALIGN(map_sz + TG3_RX_OFFSET(tp)) + in tg3_rx_data_free()
6645 if (!ri->data) in tg3_rx_data_free()
6648 dma_unmap_single(&tp->pdev->dev, dma_unmap_addr(ri, mapping), map_sz, in tg3_rx_data_free()
6650 tg3_frag_free(skb_size <= PAGE_SIZE, ri->data); in tg3_rx_data_free()
6651 ri->data = NULL; in tg3_rx_data_free()
6666 static int tg3_alloc_rx_data(struct tg3 *tp, struct tg3_rx_prodring_set *tpr, in tg3_alloc_rx_data() argument
6678 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_alloc_rx_data()
6679 desc = &tpr->rx_std[dest_idx]; in tg3_alloc_rx_data()
6680 map = &tpr->rx_std_buffers[dest_idx]; in tg3_alloc_rx_data()
6681 data_size = tp->rx_pkt_map_sz; in tg3_alloc_rx_data()
6685 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_alloc_rx_data()
6686 desc = &tpr->rx_jmb[dest_idx].std; in tg3_alloc_rx_data()
6687 map = &tpr->rx_jmb_buffers[dest_idx]; in tg3_alloc_rx_data()
6692 return -EINVAL; in tg3_alloc_rx_data()
6701 skb_size = SKB_DATA_ALIGN(data_size + TG3_RX_OFFSET(tp)) + in tg3_alloc_rx_data()
6711 return -ENOMEM; in tg3_alloc_rx_data()
6713 mapping = dma_map_single(&tp->pdev->dev, data + TG3_RX_OFFSET(tp), in tg3_alloc_rx_data()
6715 if (unlikely(dma_mapping_error(&tp->pdev->dev, mapping))) { in tg3_alloc_rx_data()
6717 return -EIO; in tg3_alloc_rx_data()
6720 map->data = data; in tg3_alloc_rx_data()
6723 desc->addr_hi = ((u64)mapping >> 32); in tg3_alloc_rx_data()
6724 desc->addr_lo = ((u64)mapping & 0xffffffff); in tg3_alloc_rx_data()
6738 struct tg3 *tp = tnapi->tp; in tg3_recycle_rx() local
6741 struct tg3_rx_prodring_set *spr = &tp->napi[0].prodring; in tg3_recycle_rx()
6746 dest_idx = dest_idx_unmasked & tp->rx_std_ring_mask; in tg3_recycle_rx()
6747 dest_desc = &dpr->rx_std[dest_idx]; in tg3_recycle_rx()
6748 dest_map = &dpr->rx_std_buffers[dest_idx]; in tg3_recycle_rx()
6749 src_desc = &spr->rx_std[src_idx]; in tg3_recycle_rx()
6750 src_map = &spr->rx_std_buffers[src_idx]; in tg3_recycle_rx()
6754 dest_idx = dest_idx_unmasked & tp->rx_jmb_ring_mask; in tg3_recycle_rx()
6755 dest_desc = &dpr->rx_jmb[dest_idx].std; in tg3_recycle_rx()
6756 dest_map = &dpr->rx_jmb_buffers[dest_idx]; in tg3_recycle_rx()
6757 src_desc = &spr->rx_jmb[src_idx].std; in tg3_recycle_rx()
6758 src_map = &spr->rx_jmb_buffers[src_idx]; in tg3_recycle_rx()
6765 dest_map->data = src_map->data; in tg3_recycle_rx()
6768 dest_desc->addr_hi = src_desc->addr_hi; in tg3_recycle_rx()
6769 dest_desc->addr_lo = src_desc->addr_lo; in tg3_recycle_rx()
6776 src_map->data = NULL; in tg3_recycle_rx()
6791 * it is first placed into the on-chip ram. When the packet's length
6799 * rings, then cache lines never move beyond shared-modified state.
6805 struct tg3 *tp = tnapi->tp; in tg3_rx() local
6808 u32 sw_idx = tnapi->rx_rcb_ptr; in tg3_rx()
6811 struct tg3_rx_prodring_set *tpr = &tnapi->prodring; in tg3_rx()
6813 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6821 std_prod_idx = tpr->rx_std_prod_idx; in tg3_rx()
6822 jmb_prod_idx = tpr->rx_jmb_prod_idx; in tg3_rx()
6825 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx]; in tg3_rx()
6833 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_rx()
6834 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_rx()
6836 ri = &tp->napi[0].prodring.rx_std_buffers[desc_idx]; in tg3_rx()
6838 data = ri->data; in tg3_rx()
6842 ri = &tp->napi[0].prodring.rx_jmb_buffers[desc_idx]; in tg3_rx()
6844 data = ri->data; in tg3_rx()
6851 if (desc->err_vlan & RXD_ERR_MASK) { in tg3_rx()
6857 tnapi->rx_dropped++; in tg3_rx()
6861 prefetch(data + TG3_RX_OFFSET(tp)); in tg3_rx()
6862 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - in tg3_rx()
6865 if ((desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6867 (desc->type_flags & RXD_FLAG_PTPSTAT_MASK) == in tg3_rx()
6873 if (len > TG3_RX_COPY_THRESH(tp)) { in tg3_rx()
6877 skb_size = tg3_alloc_rx_data(tp, tpr, opaque_key, in tg3_rx()
6882 dma_unmap_single(&tp->pdev->dev, dma_addr, skb_size, in tg3_rx()
6890 ri->data = NULL; in tg3_rx()
6900 skb_reserve(skb, TG3_RX_OFFSET(tp)); in tg3_rx()
6905 skb = netdev_alloc_skb(tp->dev, in tg3_rx()
6911 dma_sync_single_for_cpu(&tp->pdev->dev, dma_addr, len, in tg3_rx()
6913 memcpy(skb->data, in tg3_rx()
6914 data + TG3_RX_OFFSET(tp), in tg3_rx()
6916 dma_sync_single_for_device(&tp->pdev->dev, dma_addr, in tg3_rx()
6922 tg3_hwclock_to_timestamp(tp, tstamp, in tg3_rx()
6925 if ((tp->dev->features & NETIF_F_RXCSUM) && in tg3_rx()
6926 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_rx()
6927 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_rx()
6929 skb->ip_summed = CHECKSUM_UNNECESSARY; in tg3_rx()
6933 skb->protocol = eth_type_trans(skb, tp->dev); in tg3_rx()
6935 if (len > (tp->dev->mtu + ETH_HLEN) && in tg3_rx()
6936 skb->protocol != htons(ETH_P_8021Q) && in tg3_rx()
6937 skb->protocol != htons(ETH_P_8021AD)) { in tg3_rx()
6942 if (desc->type_flags & RXD_FLAG_VLAN && in tg3_rx()
6943 !(tp->rx_mode & RX_MODE_KEEP_VLAN_TAG)) in tg3_rx()
6945 desc->err_vlan & RXD_VLAN_MASK); in tg3_rx()
6947 napi_gro_receive(&tnapi->napi, skb); in tg3_rx()
6950 budget--; in tg3_rx()
6955 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { in tg3_rx()
6956 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
6957 tp->rx_std_ring_mask; in tg3_rx()
6959 tpr->rx_std_prod_idx); in tg3_rx()
6965 sw_idx &= tp->rx_ret_ring_mask; in tg3_rx()
6969 hw_idx = *(tnapi->rx_rcb_prod_idx); in tg3_rx()
6975 tnapi->rx_rcb_ptr = sw_idx; in tg3_rx()
6976 tw32_rx_mbox(tnapi->consmbox, sw_idx); in tg3_rx()
6979 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_rx()
6984 tpr->rx_std_prod_idx = std_prod_idx & in tg3_rx()
6985 tp->rx_std_ring_mask; in tg3_rx()
6987 tpr->rx_std_prod_idx); in tg3_rx()
6990 tpr->rx_jmb_prod_idx = jmb_prod_idx & in tg3_rx()
6991 tp->rx_jmb_ring_mask; in tg3_rx()
6993 tpr->rx_jmb_prod_idx); in tg3_rx()
7001 tpr->rx_std_prod_idx = std_prod_idx & tp->rx_std_ring_mask; in tg3_rx()
7002 tpr->rx_jmb_prod_idx = jmb_prod_idx & tp->rx_jmb_ring_mask; in tg3_rx()
7004 if (tnapi != &tp->napi[1]) { in tg3_rx()
7005 tp->rx_refill = true; in tg3_rx()
7006 napi_schedule(&tp->napi[1].napi); in tg3_rx()
7013 static void tg3_poll_link(struct tg3 *tp) in tg3_poll_link() argument
7015 /* handle link change and other phy events */ in tg3_poll_link()
7016 if (!(tg3_flag(tp, USE_LINKCHG_REG) || tg3_flag(tp, POLL_SERDES))) { in tg3_poll_link()
7017 struct tg3_hw_status *sblk = tp->napi[0].hw_status; in tg3_poll_link()
7019 if (sblk->status & SD_STATUS_LINK_CHG) { in tg3_poll_link()
7020 sblk->status = SD_STATUS_UPDATED | in tg3_poll_link()
7021 (sblk->status & ~SD_STATUS_LINK_CHG); in tg3_poll_link()
7022 spin_lock(&tp->lock); in tg3_poll_link()
7023 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_poll_link()
7031 tg3_setup_phy(tp, false); in tg3_poll_link()
7032 spin_unlock(&tp->lock); in tg3_poll_link()
7037 static int tg3_rx_prodring_xfer(struct tg3 *tp, in tg3_rx_prodring_xfer() argument
7045 src_prod_idx = spr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7052 if (spr->rx_std_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7055 if (spr->rx_std_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7056 cpycnt = src_prod_idx - spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7058 cpycnt = tp->rx_std_ring_mask + 1 - in tg3_rx_prodring_xfer()
7059 spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7062 tp->rx_std_ring_mask + 1 - dpr->rx_std_prod_idx); in tg3_rx_prodring_xfer()
7064 si = spr->rx_std_cons_idx; in tg3_rx_prodring_xfer()
7065 di = dpr->rx_std_prod_idx; in tg3_rx_prodring_xfer()
7068 if (dpr->rx_std_buffers[i].data) { in tg3_rx_prodring_xfer()
7069 cpycnt = i - di; in tg3_rx_prodring_xfer()
7070 err = -ENOSPC; in tg3_rx_prodring_xfer()
7084 memcpy(&dpr->rx_std_buffers[di], in tg3_rx_prodring_xfer()
7085 &spr->rx_std_buffers[si], in tg3_rx_prodring_xfer()
7090 sbd = &spr->rx_std[si]; in tg3_rx_prodring_xfer()
7091 dbd = &dpr->rx_std[di]; in tg3_rx_prodring_xfer()
7092 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7093 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7096 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7097 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7098 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7099 tp->rx_std_ring_mask; in tg3_rx_prodring_xfer()
7103 src_prod_idx = spr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7110 if (spr->rx_jmb_cons_idx == src_prod_idx) in tg3_rx_prodring_xfer()
7113 if (spr->rx_jmb_cons_idx < src_prod_idx) in tg3_rx_prodring_xfer()
7114 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7116 cpycnt = tp->rx_jmb_ring_mask + 1 - in tg3_rx_prodring_xfer()
7117 spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7120 tp->rx_jmb_ring_mask + 1 - dpr->rx_jmb_prod_idx); in tg3_rx_prodring_xfer()
7122 si = spr->rx_jmb_cons_idx; in tg3_rx_prodring_xfer()
7123 di = dpr->rx_jmb_prod_idx; in tg3_rx_prodring_xfer()
7126 if (dpr->rx_jmb_buffers[i].data) { in tg3_rx_prodring_xfer()
7127 cpycnt = i - di; in tg3_rx_prodring_xfer()
7128 err = -ENOSPC; in tg3_rx_prodring_xfer()
7142 memcpy(&dpr->rx_jmb_buffers[di], in tg3_rx_prodring_xfer()
7143 &spr->rx_jmb_buffers[si], in tg3_rx_prodring_xfer()
7148 sbd = &spr->rx_jmb[si].std; in tg3_rx_prodring_xfer()
7149 dbd = &dpr->rx_jmb[di].std; in tg3_rx_prodring_xfer()
7150 dbd->addr_hi = sbd->addr_hi; in tg3_rx_prodring_xfer()
7151 dbd->addr_lo = sbd->addr_lo; in tg3_rx_prodring_xfer()
7154 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) & in tg3_rx_prodring_xfer()
7155 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7156 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) & in tg3_rx_prodring_xfer()
7157 tp->rx_jmb_ring_mask; in tg3_rx_prodring_xfer()
7165 struct tg3 *tp = tnapi->tp; in tg3_poll_work() local
7168 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) { in tg3_poll_work()
7170 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_work()
7174 if (!tnapi->rx_rcb_prod_idx) in tg3_poll_work()
7179 * code synchronizes with tg3->napi.poll() in tg3_poll_work()
7181 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr) in tg3_poll_work()
7182 work_done += tg3_rx(tnapi, budget - work_done); in tg3_poll_work()
7184 if (tg3_flag(tp, ENABLE_RSS) && tnapi == &tp->napi[1]) { in tg3_poll_work()
7185 struct tg3_rx_prodring_set *dpr = &tp->napi[0].prodring; in tg3_poll_work()
7187 u32 std_prod_idx = dpr->rx_std_prod_idx; in tg3_poll_work()
7188 u32 jmb_prod_idx = dpr->rx_jmb_prod_idx; in tg3_poll_work()
7190 tp->rx_refill = false; in tg3_poll_work()
7191 for (i = 1; i <= tp->rxq_cnt; i++) in tg3_poll_work()
7192 err |= tg3_rx_prodring_xfer(tp, dpr, in tg3_poll_work()
7193 &tp->napi[i].prodring); in tg3_poll_work()
7197 if (std_prod_idx != dpr->rx_std_prod_idx) in tg3_poll_work()
7199 dpr->rx_std_prod_idx); in tg3_poll_work()
7201 if (jmb_prod_idx != dpr->rx_jmb_prod_idx) in tg3_poll_work()
7203 dpr->rx_jmb_prod_idx); in tg3_poll_work()
7206 tw32_f(HOSTCC_MODE, tp->coal_now); in tg3_poll_work()
7212 static inline void tg3_reset_task_schedule(struct tg3 *tp) in tg3_reset_task_schedule() argument
7214 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_schedule()
7215 schedule_work(&tp->reset_task); in tg3_reset_task_schedule()
7218 static inline void tg3_reset_task_cancel(struct tg3 *tp) in tg3_reset_task_cancel() argument
7220 if (test_and_clear_bit(TG3_FLAG_RESET_TASK_PENDING, tp->tg3_flags)) in tg3_reset_task_cancel()
7221 cancel_work_sync(&tp->reset_task); in tg3_reset_task_cancel()
7222 tg3_flag_clear(tp, TX_RECOVERY_PENDING); in tg3_reset_task_cancel()
7228 struct tg3 *tp = tnapi->tp; in tg3_poll_msix() local
7230 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll_msix()
7235 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll_msix()
7241 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll_msix()
7245 tnapi->last_tag = sblk->status_tag; in tg3_poll_msix()
7246 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll_msix()
7250 if (likely(sblk->idx[0].tx_consumer == tnapi->tx_cons && in tg3_poll_msix()
7251 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr)) { in tg3_poll_msix()
7256 if (tnapi == &tp->napi[1] && tp->rx_refill) in tg3_poll_msix()
7261 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_poll_msix()
7266 if (unlikely(tnapi == &tp->napi[1] && tp->rx_refill)) { in tg3_poll_msix()
7267 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_poll_msix()
7269 tnapi->coal_now); in tg3_poll_msix()
7275 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1); in tg3_poll_msix()
7281 tg3_reset_task_schedule(tp); in tg3_poll_msix()
7285 static void tg3_process_error(struct tg3 *tp) in tg3_process_error() argument
7290 if (tg3_flag(tp, ERROR_PROCESSED)) in tg3_process_error()
7296 netdev_err(tp->dev, "FLOW Attention error. Resetting chip.\n"); in tg3_process_error()
7301 netdev_err(tp->dev, "MSI Status error. Resetting chip.\n"); in tg3_process_error()
7306 netdev_err(tp->dev, "DMA Status error. Resetting chip.\n"); in tg3_process_error()
7313 tg3_dump_state(tp); in tg3_process_error()
7315 tg3_flag_set(tp, ERROR_PROCESSED); in tg3_process_error()
7316 tg3_reset_task_schedule(tp); in tg3_process_error()
7322 struct tg3 *tp = tnapi->tp; in tg3_poll() local
7324 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_poll()
7327 if (sblk->status & SD_STATUS_ERROR) in tg3_poll()
7328 tg3_process_error(tp); in tg3_poll()
7330 tg3_poll_link(tp); in tg3_poll()
7334 if (unlikely(tg3_flag(tp, TX_RECOVERY_PENDING))) in tg3_poll()
7340 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_poll()
7341 /* tp->last_tag is used in tg3_int_reenable() below in tg3_poll()
7345 tnapi->last_tag = sblk->status_tag; in tg3_poll()
7346 tnapi->last_irq_tag = tnapi->last_tag; in tg3_poll()
7349 sblk->status &= ~SD_STATUS_UPDATED; in tg3_poll()
7358 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL << 1); in tg3_poll()
7364 tg3_reset_task_schedule(tp); in tg3_poll()
7368 static void tg3_napi_disable(struct tg3 *tp) in tg3_napi_disable() argument
7372 for (i = tp->irq_cnt - 1; i >= 0; i--) in tg3_napi_disable()
7373 napi_disable(&tp->napi[i].napi); in tg3_napi_disable()
7376 static void tg3_napi_enable(struct tg3 *tp) in tg3_napi_enable() argument
7380 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_enable()
7381 napi_enable(&tp->napi[i].napi); in tg3_napi_enable()
7384 static void tg3_napi_init(struct tg3 *tp) in tg3_napi_init() argument
7388 netif_napi_add(tp->dev, &tp->napi[0].napi, tg3_poll); in tg3_napi_init()
7389 for (i = 1; i < tp->irq_cnt; i++) in tg3_napi_init()
7390 netif_napi_add(tp->dev, &tp->napi[i].napi, tg3_poll_msix); in tg3_napi_init()
7393 static void tg3_napi_fini(struct tg3 *tp) in tg3_napi_fini() argument
7397 for (i = 0; i < tp->irq_cnt; i++) in tg3_napi_fini()
7398 netif_napi_del(&tp->napi[i].napi); in tg3_napi_fini()
7401 static inline void tg3_netif_stop(struct tg3 *tp) in tg3_netif_stop() argument
7403 netif_trans_update(tp->dev); /* prevent tx timeout */ in tg3_netif_stop()
7404 tg3_napi_disable(tp); in tg3_netif_stop()
7405 netif_carrier_off(tp->dev); in tg3_netif_stop()
7406 netif_tx_disable(tp->dev); in tg3_netif_stop()
7409 /* tp->lock must be held */
7410 static inline void tg3_netif_start(struct tg3 *tp) in tg3_netif_start() argument
7412 tg3_ptp_resume(tp); in tg3_netif_start()
7418 netif_tx_wake_all_queues(tp->dev); in tg3_netif_start()
7420 if (tp->link_up) in tg3_netif_start()
7421 netif_carrier_on(tp->dev); in tg3_netif_start()
7423 tg3_napi_enable(tp); in tg3_netif_start()
7424 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED; in tg3_netif_start()
7425 tg3_enable_ints(tp); in tg3_netif_start()
7428 static void tg3_irq_quiesce(struct tg3 *tp) in tg3_irq_quiesce() argument
7429 __releases(tp->lock) in tg3_irq_quiesce()
7430 __acquires(tp->lock) in tg3_irq_quiesce()
7434 BUG_ON(tp->irq_sync); in tg3_irq_quiesce()
7436 tp->irq_sync = 1; in tg3_irq_quiesce()
7439 spin_unlock_bh(&tp->lock); in tg3_irq_quiesce()
7441 for (i = 0; i < tp->irq_cnt; i++) in tg3_irq_quiesce()
7442 synchronize_irq(tp->napi[i].irq_vec); in tg3_irq_quiesce()
7444 spin_lock_bh(&tp->lock); in tg3_irq_quiesce()
7448 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7452 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync) in tg3_full_lock() argument
7454 spin_lock_bh(&tp->lock); in tg3_full_lock()
7456 tg3_irq_quiesce(tp); in tg3_full_lock()
7459 static inline void tg3_full_unlock(struct tg3 *tp) in tg3_full_unlock() argument
7461 spin_unlock_bh(&tp->lock); in tg3_full_unlock()
7464 /* One-shot MSI handler - Chip automatically disables interrupt
7470 struct tg3 *tp = tnapi->tp; in tg3_msi_1shot() local
7472 prefetch(tnapi->hw_status); in tg3_msi_1shot()
7473 if (tnapi->rx_rcb) in tg3_msi_1shot()
7474 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi_1shot()
7476 if (likely(!tg3_irq_sync(tp))) in tg3_msi_1shot()
7477 napi_schedule(&tnapi->napi); in tg3_msi_1shot()
7482 /* MSI ISR - No need to check for interrupt sharing and no need to
7489 struct tg3 *tp = tnapi->tp; in tg3_msi() local
7491 prefetch(tnapi->hw_status); in tg3_msi()
7492 if (tnapi->rx_rcb) in tg3_msi()
7493 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_msi()
7495 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_msi()
7496 * chip-internal interrupt pending events. in tg3_msi()
7497 * Writing non-zero to intr-mbox-0 additional tells the in tg3_msi()
7498 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_msi()
7501 tw32_mailbox(tnapi->int_mbox, 0x00000001); in tg3_msi()
7502 if (likely(!tg3_irq_sync(tp))) in tg3_msi()
7503 napi_schedule(&tnapi->napi); in tg3_msi()
7511 struct tg3 *tp = tnapi->tp; in tg3_interrupt() local
7512 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt()
7520 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) { in tg3_interrupt()
7521 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt()
7529 * Writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt()
7530 * chip-internal interrupt pending events. in tg3_interrupt()
7531 * Writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt()
7532 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt()
7535 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt()
7540 if (tg3_irq_sync(tp)) in tg3_interrupt()
7542 sblk->status &= ~SD_STATUS_UPDATED; in tg3_interrupt()
7544 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt()
7545 napi_schedule(&tnapi->napi); in tg3_interrupt()
7547 /* No work, shared interrupt perhaps? re-enable in tg3_interrupt()
7560 struct tg3 *tp = tnapi->tp; in tg3_interrupt_tagged() local
7561 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_interrupt_tagged()
7569 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) { in tg3_interrupt_tagged()
7570 if (tg3_flag(tp, CHIP_RESETTING) || in tg3_interrupt_tagged()
7578 * writing any value to intr-mbox-0 clears PCI INTA# and in tg3_interrupt_tagged()
7579 * chip-internal interrupt pending events. in tg3_interrupt_tagged()
7580 * writing non-zero to intr-mbox-0 additional tells the in tg3_interrupt_tagged()
7581 * NIC to stop sending us irqs, engaging "in-intr-handler" in tg3_interrupt_tagged()
7584 * Flush the mailbox to de-assert the IRQ immediately to prevent in tg3_interrupt_tagged()
7596 tnapi->last_irq_tag = sblk->status_tag; in tg3_interrupt_tagged()
7598 if (tg3_irq_sync(tp)) in tg3_interrupt_tagged()
7601 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]); in tg3_interrupt_tagged()
7603 napi_schedule(&tnapi->napi); in tg3_interrupt_tagged()
7613 struct tg3 *tp = tnapi->tp; in tg3_test_isr() local
7614 struct tg3_hw_status *sblk = tnapi->hw_status; in tg3_test_isr()
7616 if ((sblk->status & SD_STATUS_UPDATED) || in tg3_test_isr()
7618 tg3_disable_ints(tp); in tg3_test_isr()
7628 struct tg3 *tp = netdev_priv(dev); in tg3_poll_controller() local
7630 if (tg3_irq_sync(tp)) in tg3_poll_controller()
7633 for (i = 0; i < tp->irq_cnt; i++) in tg3_poll_controller()
7634 tg3_interrupt(tp->napi[i].irq_vec, &tp->napi[i]); in tg3_poll_controller()
7640 struct tg3 *tp = netdev_priv(dev); in tg3_tx_timeout() local
7642 if (netif_msg_tx_err(tp)) { in tg3_tx_timeout()
7644 tg3_dump_state(tp); in tg3_tx_timeout()
7647 tg3_reset_task_schedule(tp); in tg3_tx_timeout()
7661 static inline int tg3_4g_tso_overflow_test(struct tg3 *tp, dma_addr_t mapping, in tg3_4g_tso_overflow_test() argument
7664 if (tg3_asic_rev(tp) == ASIC_REV_5762 && mss) { in tg3_4g_tso_overflow_test()
7672 /* Test for DMA addresses > 40-bit */
7673 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping, in tg3_40bit_overflow_test() argument
7677 if (tg3_flag(tp, 40BIT_DMA_BUG)) in tg3_40bit_overflow_test()
7689 txbd->addr_hi = ((u64) mapping >> 32); in tg3_tx_set_bd()
7690 txbd->addr_lo = ((u64) mapping & 0xffffffff); in tg3_tx_set_bd()
7691 txbd->len_flags = (len << TXD_LEN_SHIFT) | (flags & 0x0000ffff); in tg3_tx_set_bd()
7692 txbd->vlan_tag = (mss << TXD_MSS_SHIFT) | (vlan << TXD_VLAN_TAG_SHIFT); in tg3_tx_set_bd()
7699 struct tg3 *tp = tnapi->tp; in tg3_tx_frag_set() local
7702 if (tg3_flag(tp, SHORT_DMA_BUG) && len <= 8) in tg3_tx_frag_set()
7708 if (tg3_4g_tso_overflow_test(tp, map, len, mss)) in tg3_tx_frag_set()
7711 if (tg3_40bit_overflow_test(tp, map, len)) in tg3_tx_frag_set()
7714 if (tp->dma_limit) { in tg3_tx_frag_set()
7717 while (len > tp->dma_limit && *budget) { in tg3_tx_frag_set()
7718 u32 frag_len = tp->dma_limit; in tg3_tx_frag_set()
7719 len -= tp->dma_limit; in tg3_tx_frag_set()
7723 len += tp->dma_limit / 2; in tg3_tx_frag_set()
7724 frag_len = tp->dma_limit / 2; in tg3_tx_frag_set()
7727 tnapi->tx_buffers[*entry].fragmented = true; in tg3_tx_frag_set()
7729 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7731 *budget -= 1; in tg3_tx_frag_set()
7740 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7742 *budget -= 1; in tg3_tx_frag_set()
7746 tnapi->tx_buffers[prvidx].fragmented = false; in tg3_tx_frag_set()
7750 tg3_tx_set_bd(&tnapi->tx_ring[*entry], map, in tg3_tx_frag_set()
7762 struct tg3_tx_ring_info *txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7764 skb = txb->skb; in tg3_tx_skb_unmap()
7765 txb->skb = NULL; in tg3_tx_skb_unmap()
7767 dma_unmap_single(&tnapi->tp->pdev->dev, dma_unmap_addr(txb, mapping), in tg3_tx_skb_unmap()
7770 while (txb->fragmented) { in tg3_tx_skb_unmap()
7771 txb->fragmented = false; in tg3_tx_skb_unmap()
7773 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7777 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_tx_skb_unmap()
7780 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7782 dma_unmap_page(&tnapi->tp->pdev->dev, in tg3_tx_skb_unmap()
7786 while (txb->fragmented) { in tg3_tx_skb_unmap()
7787 txb->fragmented = false; in tg3_tx_skb_unmap()
7789 txb = &tnapi->tx_buffers[entry]; in tg3_tx_skb_unmap()
7794 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7800 struct tg3 *tp = tnapi->tp; in tigon3_dma_hwbug_workaround() local
7805 if (tg3_asic_rev(tp) != ASIC_REV_5701) in tigon3_dma_hwbug_workaround()
7808 int more_headroom = 4 - ((unsigned long)skb->data & 3); in tigon3_dma_hwbug_workaround()
7816 ret = -1; in tigon3_dma_hwbug_workaround()
7819 new_addr = dma_map_single(&tp->pdev->dev, new_skb->data, in tigon3_dma_hwbug_workaround()
7820 new_skb->len, DMA_TO_DEVICE); in tigon3_dma_hwbug_workaround()
7822 if (dma_mapping_error(&tp->pdev->dev, new_addr)) { in tigon3_dma_hwbug_workaround()
7824 ret = -1; in tigon3_dma_hwbug_workaround()
7830 tnapi->tx_buffers[*entry].skb = new_skb; in tigon3_dma_hwbug_workaround()
7831 dma_unmap_addr_set(&tnapi->tx_buffers[*entry], in tigon3_dma_hwbug_workaround()
7835 new_skb->len, base_flags, in tigon3_dma_hwbug_workaround()
7837 tg3_tx_skb_unmap(tnapi, save_entry, -1); in tigon3_dma_hwbug_workaround()
7839 ret = -1; in tigon3_dma_hwbug_workaround()
7854 return skb_shinfo(skb)->gso_segs < tnapi->tx_pending / 3; in tg3_tso_bug_gso_check()
7862 static int tg3_tso_bug(struct tg3 *tp, struct tg3_napi *tnapi, in tg3_tso_bug() argument
7865 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3; in tg3_tso_bug()
7884 segs = skb_gso_segment(skb, tp->dev->features & in tg3_tso_bug()
7887 tnapi->tx_dropped++; in tg3_tso_bug()
7893 tg3_start_xmit(seg, tp->dev); in tg3_tso_bug()
7905 struct tg3 *tp = netdev_priv(dev); in tg3_start_xmit() local
7908 int i = -1, would_hit_hwbug; in tg3_start_xmit()
7919 tnapi = &tp->napi[skb_get_queue_mapping(skb)]; in tg3_start_xmit()
7920 if (tg3_flag(tp, ENABLE_TSS)) in tg3_start_xmit()
7926 * and TX reclaim runs via tp->napi.poll inside of a software in tg3_start_xmit()
7930 if (unlikely(budget <= (skb_shinfo(skb)->nr_frags + 1))) { in tg3_start_xmit()
7941 entry = tnapi->tx_prod; in tg3_start_xmit()
7944 mss = skb_shinfo(skb)->gso_size; in tg3_start_xmit()
7954 hdr_len = skb_tcp_all_headers(skb) - ETH_HLEN; in tg3_start_xmit()
7959 if (skb->protocol == htons(ETH_P_8021Q) || in tg3_start_xmit()
7960 skb->protocol == htons(ETH_P_8021AD)) { in tg3_start_xmit()
7962 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
7968 tg3_flag(tp, TSO_BUG)) { in tg3_start_xmit()
7970 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
7973 ip_csum = iph->check; in tg3_start_xmit()
7974 ip_tot_len = iph->tot_len; in tg3_start_xmit()
7975 iph->check = 0; in tg3_start_xmit()
7976 iph->tot_len = htons(mss + hdr_len); in tg3_start_xmit()
7983 tcp_csum = tcph->check; in tg3_start_xmit()
7985 if (tg3_flag(tp, HW_TSO_1) || in tg3_start_xmit()
7986 tg3_flag(tp, HW_TSO_2) || in tg3_start_xmit()
7987 tg3_flag(tp, HW_TSO_3)) { in tg3_start_xmit()
7988 tcph->check = 0; in tg3_start_xmit()
7991 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, in tg3_start_xmit()
7995 if (tg3_flag(tp, HW_TSO_3)) { in tg3_start_xmit()
8000 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_start_xmit()
8002 else if (tg3_flag(tp, HW_TSO_1) || in tg3_start_xmit()
8003 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_start_xmit()
8004 if (tcp_opt_len || iph->ihl > 5) { in tg3_start_xmit()
8007 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in tg3_start_xmit()
8011 if (tcp_opt_len || iph->ihl > 5) { in tg3_start_xmit()
8014 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2); in tg3_start_xmit()
8018 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { in tg3_start_xmit()
8022 if (skb->protocol == htons(ETH_P_8021Q) || in tg3_start_xmit()
8023 skb->protocol == htons(ETH_P_8021AD)) { in tg3_start_xmit()
8031 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in tg3_start_xmit()
8032 !mss && skb->len > VLAN_ETH_FRAME_LEN) in tg3_start_xmit()
8040 if ((unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) && in tg3_start_xmit()
8041 tg3_flag(tp, TX_TSTAMP_EN)) { in tg3_start_xmit()
8042 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; in tg3_start_xmit()
8048 mapping = dma_map_single(&tp->pdev->dev, skb->data, len, in tg3_start_xmit()
8050 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8054 tnapi->tx_buffers[entry].skb = skb; in tg3_start_xmit()
8055 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping); in tg3_start_xmit()
8059 if (tg3_flag(tp, 5701_DMA_BUG)) in tg3_start_xmit()
8063 ((skb_shinfo(skb)->nr_frags == 0) ? TXD_FLAG_END : 0), in tg3_start_xmit()
8066 } else if (skb_shinfo(skb)->nr_frags > 0) { in tg3_start_xmit()
8069 if (!tg3_flag(tp, HW_TSO_1) && in tg3_start_xmit()
8070 !tg3_flag(tp, HW_TSO_2) && in tg3_start_xmit()
8071 !tg3_flag(tp, HW_TSO_3)) in tg3_start_xmit()
8077 last = skb_shinfo(skb)->nr_frags - 1; in tg3_start_xmit()
8079 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; in tg3_start_xmit()
8082 mapping = skb_frag_dma_map(&tp->pdev->dev, frag, 0, in tg3_start_xmit()
8085 tnapi->tx_buffers[entry].skb = NULL; in tg3_start_xmit()
8086 dma_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, in tg3_start_xmit()
8088 if (dma_mapping_error(&tp->pdev->dev, mapping)) in tg3_start_xmit()
8103 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, i); in tg3_start_xmit()
8110 iph->check = ip_csum; in tg3_start_xmit()
8111 iph->tot_len = ip_tot_len; in tg3_start_xmit()
8113 tcph->check = tcp_csum; in tg3_start_xmit()
8114 return tg3_tso_bug(tp, tnapi, txq, skb); in tg3_start_xmit()
8120 entry = tnapi->tx_prod; in tg3_start_xmit()
8128 netdev_tx_sent_queue(txq, skb->len); in tg3_start_xmit()
8133 tnapi->tx_prod = entry; in tg3_start_xmit()
8149 tw32_tx_mbox(tnapi->prodmbox, entry); in tg3_start_xmit()
8155 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod, --i); in tg3_start_xmit()
8156 tnapi->tx_buffers[tnapi->tx_prod].skb = NULL; in tg3_start_xmit()
8160 tnapi->tx_dropped++; in tg3_start_xmit()
8164 static void tg3_mac_loopback(struct tg3 *tp, bool enable) in tg3_mac_loopback() argument
8167 tp->mac_mode &= ~(MAC_MODE_HALF_DUPLEX | in tg3_mac_loopback()
8170 tp->mac_mode |= MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8172 if (!tg3_flag(tp, 5705_PLUS)) in tg3_mac_loopback()
8173 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8175 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_mac_loopback()
8176 tp->mac_mode |= MAC_MODE_PORT_MODE_MII; in tg3_mac_loopback()
8178 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; in tg3_mac_loopback()
8180 tp->mac_mode &= ~MAC_MODE_PORT_INT_LPBACK; in tg3_mac_loopback()
8182 if (tg3_flag(tp, 5705_PLUS) || in tg3_mac_loopback()
8183 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) || in tg3_mac_loopback()
8184 tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_mac_loopback()
8185 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY; in tg3_mac_loopback()
8188 tw32(MAC_MODE, tp->mac_mode); in tg3_mac_loopback()
8192 static int tg3_phy_lpbk_set(struct tg3 *tp, u32 speed, bool extlpbk) in tg3_phy_lpbk_set() argument
8196 tg3_phy_toggle_apd(tp, false); in tg3_phy_lpbk_set()
8197 tg3_phy_toggle_automdix(tp, false); in tg3_phy_lpbk_set()
8199 if (extlpbk && tg3_phy_set_extloopbk(tp)) in tg3_phy_lpbk_set()
8200 return -EIO; in tg3_phy_lpbk_set()
8211 if (tp->phy_flags & TG3_PHYFLG_IS_FET) { in tg3_phy_lpbk_set()
8221 if (!(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_phy_lpbk_set()
8222 tg3_readphy(tp, MII_CTRL1000, &val); in tg3_phy_lpbk_set()
8225 tg3_writephy(tp, MII_CTRL1000, val); in tg3_phy_lpbk_set()
8229 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest); in tg3_phy_lpbk_set()
8234 tg3_writephy(tp, MII_BMCR, bmcr); in tg3_phy_lpbk_set()
8237 if (tp->phy_flags & TG3_PHYFLG_IS_FET) in tg3_phy_lpbk_set()
8238 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_phy_lpbk_set()
8242 if ((tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_phy_lpbk_set()
8243 tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_phy_lpbk_set()
8244 tg3_writephy(tp, MII_TG3_FET_PTEST, ptest | in tg3_phy_lpbk_set()
8249 tg3_readphy(tp, MII_TG3_FET_PTEST, &val); in tg3_phy_lpbk_set()
8253 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_phy_lpbk_set()
8254 tg3_flag(tp, 5780_CLASS)) { in tg3_phy_lpbk_set()
8257 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_phy_lpbk_set()
8260 mac_mode = tp->mac_mode & in tg3_phy_lpbk_set()
8267 if (tg3_asic_rev(tp) == ASIC_REV_5700) { in tg3_phy_lpbk_set()
8268 u32 masked_phy_id = tp->phy_id & TG3_PHY_ID_MASK; in tg3_phy_lpbk_set()
8275 tg3_writephy(tp, MII_TG3_EXT_CTRL, in tg3_phy_lpbk_set()
8287 struct tg3 *tp = netdev_priv(dev); in tg3_set_loopback() local
8290 if (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK) in tg3_set_loopback()
8293 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8294 tg3_mac_loopback(tp, true); in tg3_set_loopback()
8295 netif_carrier_on(tp->dev); in tg3_set_loopback()
8296 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8299 if (!(tp->mac_mode & MAC_MODE_PORT_INT_LPBACK)) in tg3_set_loopback()
8302 spin_lock_bh(&tp->lock); in tg3_set_loopback()
8303 tg3_mac_loopback(tp, false); in tg3_set_loopback()
8304 /* Force link status check */ in tg3_set_loopback()
8305 tg3_setup_phy(tp, true); in tg3_set_loopback()
8306 spin_unlock_bh(&tp->lock); in tg3_set_loopback()
8314 struct tg3 *tp = netdev_priv(dev); in tg3_fix_features() local
8316 if (dev->mtu > ETH_DATA_LEN && tg3_flag(tp, 5780_CLASS)) in tg3_fix_features()
8324 netdev_features_t changed = dev->features ^ features; in tg3_set_features()
8332 static void tg3_rx_prodring_free(struct tg3 *tp, in tg3_rx_prodring_free() argument
8337 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_free()
8338 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx; in tg3_rx_prodring_free()
8339 i = (i + 1) & tp->rx_std_ring_mask) in tg3_rx_prodring_free()
8340 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8341 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8343 if (tg3_flag(tp, JUMBO_CAPABLE)) { in tg3_rx_prodring_free()
8344 for (i = tpr->rx_jmb_cons_idx; in tg3_rx_prodring_free()
8345 i != tpr->rx_jmb_prod_idx; in tg3_rx_prodring_free()
8346 i = (i + 1) & tp->rx_jmb_ring_mask) { in tg3_rx_prodring_free()
8347 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8355 for (i = 0; i <= tp->rx_std_ring_mask; i++) in tg3_rx_prodring_free()
8356 tg3_rx_data_free(tp, &tpr->rx_std_buffers[i], in tg3_rx_prodring_free()
8357 tp->rx_pkt_map_sz); in tg3_rx_prodring_free()
8359 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_free()
8360 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) in tg3_rx_prodring_free()
8361 tg3_rx_data_free(tp, &tpr->rx_jmb_buffers[i], in tg3_rx_prodring_free()
8370 * end up in the driver. tp->{tx,}lock are held and thus
8373 static int tg3_rx_prodring_alloc(struct tg3 *tp, in tg3_rx_prodring_alloc() argument
8378 tpr->rx_std_cons_idx = 0; in tg3_rx_prodring_alloc()
8379 tpr->rx_std_prod_idx = 0; in tg3_rx_prodring_alloc()
8380 tpr->rx_jmb_cons_idx = 0; in tg3_rx_prodring_alloc()
8381 tpr->rx_jmb_prod_idx = 0; in tg3_rx_prodring_alloc()
8383 if (tpr != &tp->napi[0].prodring) { in tg3_rx_prodring_alloc()
8384 memset(&tpr->rx_std_buffers[0], 0, in tg3_rx_prodring_alloc()
8385 TG3_RX_STD_BUFF_RING_SIZE(tp)); in tg3_rx_prodring_alloc()
8386 if (tpr->rx_jmb_buffers) in tg3_rx_prodring_alloc()
8387 memset(&tpr->rx_jmb_buffers[0], 0, in tg3_rx_prodring_alloc()
8388 TG3_RX_JMB_BUFF_RING_SIZE(tp)); in tg3_rx_prodring_alloc()
8393 memset(tpr->rx_std, 0, TG3_RX_STD_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8396 if (tg3_flag(tp, 5780_CLASS) && in tg3_rx_prodring_alloc()
8397 tp->dev->mtu > ETH_DATA_LEN) in tg3_rx_prodring_alloc()
8399 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz); in tg3_rx_prodring_alloc()
8405 for (i = 0; i <= tp->rx_std_ring_mask; i++) { in tg3_rx_prodring_alloc()
8408 rxd = &tpr->rx_std[i]; in tg3_rx_prodring_alloc()
8409 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8410 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT); in tg3_rx_prodring_alloc()
8411 rxd->opaque = (RXD_OPAQUE_RING_STD | in tg3_rx_prodring_alloc()
8416 for (i = 0; i < tp->rx_pending; i++) { in tg3_rx_prodring_alloc()
8419 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_STD, i, in tg3_rx_prodring_alloc()
8421 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8424 "successfully\n", i, tp->rx_pending); in tg3_rx_prodring_alloc()
8427 tp->rx_pending = i; in tg3_rx_prodring_alloc()
8432 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_rx_prodring_alloc()
8435 memset(tpr->rx_jmb, 0, TG3_RX_JMB_RING_BYTES(tp)); in tg3_rx_prodring_alloc()
8437 if (!tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_rx_prodring_alloc()
8440 for (i = 0; i <= tp->rx_jmb_ring_mask; i++) { in tg3_rx_prodring_alloc()
8443 rxd = &tpr->rx_jmb[i].std; in tg3_rx_prodring_alloc()
8444 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT; in tg3_rx_prodring_alloc()
8445 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) | in tg3_rx_prodring_alloc()
8447 rxd->opaque = (RXD_OPAQUE_RING_JUMBO | in tg3_rx_prodring_alloc()
8451 for (i = 0; i < tp->rx_jumbo_pending; i++) { in tg3_rx_prodring_alloc()
8454 if (tg3_alloc_rx_data(tp, tpr, RXD_OPAQUE_RING_JUMBO, i, in tg3_rx_prodring_alloc()
8456 netdev_warn(tp->dev, in tg3_rx_prodring_alloc()
8459 "successfully\n", i, tp->rx_jumbo_pending); in tg3_rx_prodring_alloc()
8462 tp->rx_jumbo_pending = i; in tg3_rx_prodring_alloc()
8471 tg3_rx_prodring_free(tp, tpr); in tg3_rx_prodring_alloc()
8472 return -ENOMEM; in tg3_rx_prodring_alloc()
8475 static void tg3_rx_prodring_fini(struct tg3 *tp, in tg3_rx_prodring_fini() argument
8478 kfree(tpr->rx_std_buffers); in tg3_rx_prodring_fini()
8479 tpr->rx_std_buffers = NULL; in tg3_rx_prodring_fini()
8480 kfree(tpr->rx_jmb_buffers); in tg3_rx_prodring_fini()
8481 tpr->rx_jmb_buffers = NULL; in tg3_rx_prodring_fini()
8482 if (tpr->rx_std) { in tg3_rx_prodring_fini()
8483 dma_free_coherent(&tp->pdev->dev, TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_fini()
8484 tpr->rx_std, tpr->rx_std_mapping); in tg3_rx_prodring_fini()
8485 tpr->rx_std = NULL; in tg3_rx_prodring_fini()
8487 if (tpr->rx_jmb) { in tg3_rx_prodring_fini()
8488 dma_free_coherent(&tp->pdev->dev, TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_fini()
8489 tpr->rx_jmb, tpr->rx_jmb_mapping); in tg3_rx_prodring_fini()
8490 tpr->rx_jmb = NULL; in tg3_rx_prodring_fini()
8494 static int tg3_rx_prodring_init(struct tg3 *tp, in tg3_rx_prodring_init() argument
8497 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8499 if (!tpr->rx_std_buffers) in tg3_rx_prodring_init()
8500 return -ENOMEM; in tg3_rx_prodring_init()
8502 tpr->rx_std = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8503 TG3_RX_STD_RING_BYTES(tp), in tg3_rx_prodring_init()
8504 &tpr->rx_std_mapping, in tg3_rx_prodring_init()
8506 if (!tpr->rx_std) in tg3_rx_prodring_init()
8509 if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) { in tg3_rx_prodring_init()
8510 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp), in tg3_rx_prodring_init()
8512 if (!tpr->rx_jmb_buffers) in tg3_rx_prodring_init()
8515 tpr->rx_jmb = dma_alloc_coherent(&tp->pdev->dev, in tg3_rx_prodring_init()
8516 TG3_RX_JMB_RING_BYTES(tp), in tg3_rx_prodring_init()
8517 &tpr->rx_jmb_mapping, in tg3_rx_prodring_init()
8519 if (!tpr->rx_jmb) in tg3_rx_prodring_init()
8526 tg3_rx_prodring_fini(tp, tpr); in tg3_rx_prodring_init()
8527 return -ENOMEM; in tg3_rx_prodring_init()
8534 * end up in the driver. tp->{tx,}lock is not held and we are not
8537 static void tg3_free_rings(struct tg3 *tp) in tg3_free_rings() argument
8541 for (j = 0; j < tp->irq_cnt; j++) { in tg3_free_rings()
8542 struct tg3_napi *tnapi = &tp->napi[j]; in tg3_free_rings()
8544 tg3_rx_prodring_free(tp, &tnapi->prodring); in tg3_free_rings()
8546 if (!tnapi->tx_buffers) in tg3_free_rings()
8550 struct sk_buff *skb = tnapi->tx_buffers[i].skb; in tg3_free_rings()
8556 skb_shinfo(skb)->nr_frags - 1); in tg3_free_rings()
8560 netdev_tx_reset_queue(netdev_get_tx_queue(tp->dev, j)); in tg3_free_rings()
8568 * end up in the driver. tp->{tx,}lock are held and thus
8571 static int tg3_init_rings(struct tg3 *tp) in tg3_init_rings() argument
8576 tg3_free_rings(tp); in tg3_init_rings()
8578 for (i = 0; i < tp->irq_cnt; i++) { in tg3_init_rings()
8579 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_rings()
8581 tnapi->last_tag = 0; in tg3_init_rings()
8582 tnapi->last_irq_tag = 0; in tg3_init_rings()
8583 tnapi->hw_status->status = 0; in tg3_init_rings()
8584 tnapi->hw_status->status_tag = 0; in tg3_init_rings()
8585 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_init_rings()
8587 tnapi->tx_prod = 0; in tg3_init_rings()
8588 tnapi->tx_cons = 0; in tg3_init_rings()
8589 if (tnapi->tx_ring) in tg3_init_rings()
8590 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES); in tg3_init_rings()
8592 tnapi->rx_rcb_ptr = 0; in tg3_init_rings()
8593 if (tnapi->rx_rcb) in tg3_init_rings()
8594 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp)); in tg3_init_rings()
8596 if (tnapi->prodring.rx_std && in tg3_init_rings()
8597 tg3_rx_prodring_alloc(tp, &tnapi->prodring)) { in tg3_init_rings()
8598 tg3_free_rings(tp); in tg3_init_rings()
8599 return -ENOMEM; in tg3_init_rings()
8606 static void tg3_mem_tx_release(struct tg3 *tp) in tg3_mem_tx_release() argument
8610 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_tx_release()
8611 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_tx_release()
8613 if (tnapi->tx_ring) { in tg3_mem_tx_release()
8614 dma_free_coherent(&tp->pdev->dev, TG3_TX_RING_BYTES, in tg3_mem_tx_release()
8615 tnapi->tx_ring, tnapi->tx_desc_mapping); in tg3_mem_tx_release()
8616 tnapi->tx_ring = NULL; in tg3_mem_tx_release()
8619 kfree(tnapi->tx_buffers); in tg3_mem_tx_release()
8620 tnapi->tx_buffers = NULL; in tg3_mem_tx_release()
8624 static int tg3_mem_tx_acquire(struct tg3 *tp) in tg3_mem_tx_acquire() argument
8627 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_mem_tx_acquire()
8632 if (tg3_flag(tp, ENABLE_TSS)) in tg3_mem_tx_acquire()
8635 for (i = 0; i < tp->txq_cnt; i++, tnapi++) { in tg3_mem_tx_acquire()
8636 tnapi->tx_buffers = kcalloc(TG3_TX_RING_SIZE, in tg3_mem_tx_acquire()
8639 if (!tnapi->tx_buffers) in tg3_mem_tx_acquire()
8642 tnapi->tx_ring = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_tx_acquire()
8644 &tnapi->tx_desc_mapping, in tg3_mem_tx_acquire()
8646 if (!tnapi->tx_ring) in tg3_mem_tx_acquire()
8653 tg3_mem_tx_release(tp); in tg3_mem_tx_acquire()
8654 return -ENOMEM; in tg3_mem_tx_acquire()
8657 static void tg3_mem_rx_release(struct tg3 *tp) in tg3_mem_rx_release() argument
8661 for (i = 0; i < tp->irq_max; i++) { in tg3_mem_rx_release()
8662 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_release()
8664 tg3_rx_prodring_fini(tp, &tnapi->prodring); in tg3_mem_rx_release()
8666 if (!tnapi->rx_rcb) in tg3_mem_rx_release()
8669 dma_free_coherent(&tp->pdev->dev, in tg3_mem_rx_release()
8670 TG3_RX_RCB_RING_BYTES(tp), in tg3_mem_rx_release()
8671 tnapi->rx_rcb, in tg3_mem_rx_release()
8672 tnapi->rx_rcb_mapping); in tg3_mem_rx_release()
8673 tnapi->rx_rcb = NULL; in tg3_mem_rx_release()
8677 static int tg3_mem_rx_acquire(struct tg3 *tp) in tg3_mem_rx_acquire() argument
8681 limit = tp->rxq_cnt; in tg3_mem_rx_acquire()
8686 if (tg3_flag(tp, ENABLE_RSS)) in tg3_mem_rx_acquire()
8690 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_mem_rx_acquire()
8692 if (tg3_rx_prodring_init(tp, &tnapi->prodring)) in tg3_mem_rx_acquire()
8699 if (!i && tg3_flag(tp, ENABLE_RSS)) in tg3_mem_rx_acquire()
8702 tnapi->rx_rcb = dma_alloc_coherent(&tp->pdev->dev, in tg3_mem_rx_acquire()
8703 TG3_RX_RCB_RING_BYTES(tp), in tg3_mem_rx_acquire()
8704 &tnapi->rx_rcb_mapping, in tg3_mem_rx_acquire()
8706 if (!tnapi->rx_rcb) in tg3_mem_rx_acquire()
8713 tg3_mem_rx_release(tp); in tg3_mem_rx_acquire()
8714 return -ENOMEM; in tg3_mem_rx_acquire()
8721 static void tg3_free_consistent(struct tg3 *tp) in tg3_free_consistent() argument
8725 for (i = 0; i < tp->irq_cnt; i++) { in tg3_free_consistent()
8726 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_free_consistent()
8728 if (tnapi->hw_status) { in tg3_free_consistent()
8729 dma_free_coherent(&tp->pdev->dev, TG3_HW_STATUS_SIZE, in tg3_free_consistent()
8730 tnapi->hw_status, in tg3_free_consistent()
8731 tnapi->status_mapping); in tg3_free_consistent()
8732 tnapi->hw_status = NULL; in tg3_free_consistent()
8736 tg3_mem_rx_release(tp); in tg3_free_consistent()
8737 tg3_mem_tx_release(tp); in tg3_free_consistent()
8739 /* tp->hw_stats can be referenced safely: in tg3_free_consistent()
8741 * 2. or under tp->lock if TG3_FLAG_INIT_COMPLETE is set. in tg3_free_consistent()
8743 if (tp->hw_stats) { in tg3_free_consistent()
8744 dma_free_coherent(&tp->pdev->dev, sizeof(struct tg3_hw_stats), in tg3_free_consistent()
8745 tp->hw_stats, tp->stats_mapping); in tg3_free_consistent()
8746 tp->hw_stats = NULL; in tg3_free_consistent()
8754 static int tg3_alloc_consistent(struct tg3 *tp) in tg3_alloc_consistent() argument
8758 tp->hw_stats = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8760 &tp->stats_mapping, GFP_KERNEL); in tg3_alloc_consistent()
8761 if (!tp->hw_stats) in tg3_alloc_consistent()
8764 for (i = 0; i < tp->irq_cnt; i++) { in tg3_alloc_consistent()
8765 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_alloc_consistent()
8768 tnapi->hw_status = dma_alloc_coherent(&tp->pdev->dev, in tg3_alloc_consistent()
8770 &tnapi->status_mapping, in tg3_alloc_consistent()
8772 if (!tnapi->hw_status) in tg3_alloc_consistent()
8775 sblk = tnapi->hw_status; in tg3_alloc_consistent()
8777 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_alloc_consistent()
8788 prodptr = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8791 prodptr = &sblk->rx_jumbo_consumer; in tg3_alloc_consistent()
8794 prodptr = &sblk->reserved; in tg3_alloc_consistent()
8797 prodptr = &sblk->rx_mini_consumer; in tg3_alloc_consistent()
8800 tnapi->rx_rcb_prod_idx = prodptr; in tg3_alloc_consistent()
8802 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer; in tg3_alloc_consistent()
8806 if (tg3_mem_tx_acquire(tp) || tg3_mem_rx_acquire(tp)) in tg3_alloc_consistent()
8812 tg3_free_consistent(tp); in tg3_alloc_consistent()
8813 return -ENOMEM; in tg3_alloc_consistent()
8819 * clears. tp->lock is held.
8821 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, bool silent) in tg3_stop_block() argument
8826 if (tg3_flag(tp, 5705_PLUS)) { in tg3_stop_block()
8848 if (pci_channel_offline(tp->pdev)) { in tg3_stop_block()
8849 dev_err(&tp->pdev->dev, in tg3_stop_block()
8853 return -ENODEV; in tg3_stop_block()
8863 dev_err(&tp->pdev->dev, in tg3_stop_block()
8866 return -ENODEV; in tg3_stop_block()
8872 /* tp->lock is held. */
8873 static int tg3_abort_hw(struct tg3 *tp, bool silent) in tg3_abort_hw() argument
8877 tg3_disable_ints(tp); in tg3_abort_hw()
8879 if (pci_channel_offline(tp->pdev)) { in tg3_abort_hw()
8880 tp->rx_mode &= ~(RX_MODE_ENABLE | TX_MODE_ENABLE); in tg3_abort_hw()
8881 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8882 err = -ENODEV; in tg3_abort_hw()
8886 tp->rx_mode &= ~RX_MODE_ENABLE; in tg3_abort_hw()
8887 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_abort_hw()
8890 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8891 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent); in tg3_abort_hw()
8892 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent); in tg3_abort_hw()
8893 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8894 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent); in tg3_abort_hw()
8895 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent); in tg3_abort_hw()
8897 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent); in tg3_abort_hw()
8898 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent); in tg3_abort_hw()
8899 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent); in tg3_abort_hw()
8900 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8901 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent); in tg3_abort_hw()
8902 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8903 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent); in tg3_abort_hw()
8905 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE; in tg3_abort_hw()
8906 tw32_f(MAC_MODE, tp->mac_mode); in tg3_abort_hw()
8909 tp->tx_mode &= ~TX_MODE_ENABLE; in tg3_abort_hw()
8910 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_abort_hw()
8918 dev_err(&tp->pdev->dev, in tg3_abort_hw()
8921 err |= -ENODEV; in tg3_abort_hw()
8924 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent); in tg3_abort_hw()
8925 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent); in tg3_abort_hw()
8926 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent); in tg3_abort_hw()
8931 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent); in tg3_abort_hw()
8932 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent); in tg3_abort_hw()
8935 for (i = 0; i < tp->irq_cnt; i++) { in tg3_abort_hw()
8936 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_abort_hw()
8937 if (tnapi->hw_status) in tg3_abort_hw()
8938 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_abort_hw()
8945 static void tg3_save_pci_state(struct tg3 *tp) in tg3_save_pci_state() argument
8947 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd); in tg3_save_pci_state()
8951 static void tg3_restore_pci_state(struct tg3 *tp) in tg3_restore_pci_state() argument
8955 /* Re-enable indirect register accesses. */ in tg3_restore_pci_state()
8956 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_restore_pci_state()
8957 tp->misc_host_ctrl); in tg3_restore_pci_state()
8961 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && in tg3_restore_pci_state()
8962 tg3_flag(tp, PCIX_MODE)) in tg3_restore_pci_state()
8965 if (tg3_flag(tp, ENABLE_APE)) in tg3_restore_pci_state()
8969 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); in tg3_restore_pci_state()
8971 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd); in tg3_restore_pci_state()
8973 if (!tg3_flag(tp, PCI_EXPRESS)) { in tg3_restore_pci_state()
8974 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_restore_pci_state()
8975 tp->pci_cacheline_sz); in tg3_restore_pci_state()
8976 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_restore_pci_state()
8977 tp->pci_lat_timer); in tg3_restore_pci_state()
8980 /* Make sure PCI-X relaxed ordering bit is clear. */ in tg3_restore_pci_state()
8981 if (tg3_flag(tp, PCIX_MODE)) { in tg3_restore_pci_state()
8984 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8987 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_restore_pci_state()
8991 if (tg3_flag(tp, 5780_CLASS)) { in tg3_restore_pci_state()
8996 if (tg3_flag(tp, USING_MSI)) { in tg3_restore_pci_state()
8999 pci_read_config_word(tp->pdev, in tg3_restore_pci_state()
9000 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9002 pci_write_config_word(tp->pdev, in tg3_restore_pci_state()
9003 tp->msi_cap + PCI_MSI_FLAGS, in tg3_restore_pci_state()
9011 static void tg3_override_clk(struct tg3 *tp) in tg3_override_clk() argument
9015 switch (tg3_asic_rev(tp)) { in tg3_override_clk()
9032 static void tg3_restore_clk(struct tg3 *tp) in tg3_restore_clk() argument
9036 switch (tg3_asic_rev(tp)) { in tg3_restore_clk()
9054 /* tp->lock is held. */
9055 static int tg3_chip_reset(struct tg3 *tp) in tg3_chip_reset() argument
9056 __releases(tp->lock) in tg3_chip_reset()
9057 __acquires(tp->lock) in tg3_chip_reset()
9063 if (!pci_device_is_present(tp->pdev)) in tg3_chip_reset()
9064 return -ENODEV; in tg3_chip_reset()
9066 tg3_nvram_lock(tp); in tg3_chip_reset()
9068 tg3_ape_lock(tp, TG3_APE_LOCK_GRC); in tg3_chip_reset()
9073 tp->nvram_lock_cnt = 0; in tg3_chip_reset()
9079 tg3_save_pci_state(tp); in tg3_chip_reset()
9081 if (tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_chip_reset()
9082 tg3_flag(tp, 5755_PLUS)) in tg3_chip_reset()
9091 write_op = tp->write32; in tg3_chip_reset()
9093 tp->write32 = tg3_write32; in tg3_chip_reset()
9101 tg3_flag_set(tp, CHIP_RESETTING); in tg3_chip_reset()
9102 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chip_reset()
9103 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chip_reset()
9104 if (tnapi->hw_status) { in tg3_chip_reset()
9105 tnapi->hw_status->status = 0; in tg3_chip_reset()
9106 tnapi->hw_status->status_tag = 0; in tg3_chip_reset()
9108 tnapi->last_tag = 0; in tg3_chip_reset()
9109 tnapi->last_irq_tag = 0; in tg3_chip_reset()
9113 tg3_full_unlock(tp); in tg3_chip_reset()
9115 for (i = 0; i < tp->irq_cnt; i++) in tg3_chip_reset()
9116 synchronize_irq(tp->napi[i].irq_vec); in tg3_chip_reset()
9118 tg3_full_lock(tp, 0); in tg3_chip_reset()
9120 if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_chip_reset()
9128 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_chip_reset()
9130 if (tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_chip_reset()
9131 !tg3_flag(tp, 57765_PLUS) && in tg3_chip_reset()
9136 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) { in tg3_chip_reset()
9142 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_chip_reset()
9148 /* Set the clock to the highest frequency to avoid timeouts. With link in tg3_chip_reset()
9153 tg3_override_clk(tp); in tg3_chip_reset()
9156 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
9162 tp->write32 = write_op; in tg3_chip_reset()
9185 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val); in tg3_chip_reset()
9189 if (tg3_flag(tp, PCI_EXPRESS) && pci_is_pcie(tp->pdev)) { in tg3_chip_reset()
9192 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0) { in tg3_chip_reset()
9196 /* Wait for link training to complete. */ in tg3_chip_reset()
9200 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val); in tg3_chip_reset()
9201 pci_write_config_dword(tp->pdev, 0xc4, in tg3_chip_reset()
9211 if (!tg3_flag(tp, CPMU_PRESENT)) in tg3_chip_reset()
9213 pcie_capability_clear_word(tp->pdev, PCI_EXP_DEVCTL, val16); in tg3_chip_reset()
9216 pcie_capability_write_word(tp->pdev, PCI_EXP_DEVSTA, in tg3_chip_reset()
9223 tg3_restore_pci_state(tp); in tg3_chip_reset()
9225 tg3_flag_clear(tp, CHIP_RESETTING); in tg3_chip_reset()
9226 tg3_flag_clear(tp, ERROR_PROCESSED); in tg3_chip_reset()
9229 if (tg3_flag(tp, 5780_CLASS)) in tg3_chip_reset()
9233 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A3) { in tg3_chip_reset()
9234 tg3_stop_fw(tp); in tg3_chip_reset()
9238 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_chip_reset()
9244 tg3_stop_fw(tp); in tg3_chip_reset()
9245 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_chip_reset()
9248 err = tg3_poll_fw(tp); in tg3_chip_reset()
9252 tw32(GRC_MODE, tp->grc_mode); in tg3_chip_reset()
9254 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) { in tg3_chip_reset()
9260 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 && in tg3_chip_reset()
9261 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_chip_reset()
9262 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE; in tg3_chip_reset()
9263 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A0) in tg3_chip_reset()
9264 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN; in tg3_chip_reset()
9265 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_chip_reset()
9268 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_chip_reset()
9269 tp->mac_mode = MAC_MODE_PORT_MODE_TBI; in tg3_chip_reset()
9270 val = tp->mac_mode; in tg3_chip_reset()
9271 } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_chip_reset()
9272 tp->mac_mode = MAC_MODE_PORT_MODE_GMII; in tg3_chip_reset()
9273 val = tp->mac_mode; in tg3_chip_reset()
9280 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC); in tg3_chip_reset()
9282 tg3_mdio_start(tp); in tg3_chip_reset()
9284 if (tg3_flag(tp, PCI_EXPRESS) && in tg3_chip_reset()
9285 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && in tg3_chip_reset()
9286 tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_chip_reset()
9287 !tg3_flag(tp, 57765_PLUS)) { in tg3_chip_reset()
9293 tg3_restore_clk(tp); in tg3_chip_reset()
9296 * with 100Mbps link speed. in tg3_chip_reset()
9298 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_chip_reset()
9305 tg3_flag_clear(tp, ENABLE_ASF); in tg3_chip_reset()
9306 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_chip_reset()
9309 tg3_flag_clear(tp, ASF_NEW_HANDSHAKE); in tg3_chip_reset()
9310 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); in tg3_chip_reset()
9314 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); in tg3_chip_reset()
9316 tg3_flag_set(tp, ENABLE_ASF); in tg3_chip_reset()
9317 tp->last_event_jiffies = jiffies; in tg3_chip_reset()
9318 if (tg3_flag(tp, 5750_PLUS)) in tg3_chip_reset()
9319 tg3_flag_set(tp, ASF_NEW_HANDSHAKE); in tg3_chip_reset()
9321 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &nic_cfg); in tg3_chip_reset()
9323 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_chip_reset()
9325 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_chip_reset()
9336 /* tp->lock is held. */
9337 static int tg3_halt(struct tg3 *tp, int kind, bool silent) in tg3_halt() argument
9341 tg3_stop_fw(tp); in tg3_halt()
9343 tg3_write_sig_pre_reset(tp, kind); in tg3_halt()
9345 tg3_abort_hw(tp, silent); in tg3_halt()
9346 err = tg3_chip_reset(tp); in tg3_halt()
9348 __tg3_set_mac_addr(tp, false); in tg3_halt()
9350 tg3_write_sig_legacy(tp, kind); in tg3_halt()
9351 tg3_write_sig_post_reset(tp, kind); in tg3_halt()
9353 if (tp->hw_stats) { in tg3_halt()
9355 tg3_get_nstats(tp, &tp->net_stats_prev); in tg3_halt()
9356 tg3_get_estats(tp, &tp->estats_prev); in tg3_halt()
9359 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats)); in tg3_halt()
9362 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_halt()
9364 tnapi->rx_dropped = 0; in tg3_halt()
9365 tnapi->tx_dropped = 0; in tg3_halt()
9374 struct tg3 *tp = netdev_priv(dev); in tg3_set_mac_addr() local
9379 if (!is_valid_ether_addr(addr->sa_data)) in tg3_set_mac_addr()
9380 return -EADDRNOTAVAIL; in tg3_set_mac_addr()
9382 eth_hw_addr_set(dev, addr->sa_data); in tg3_set_mac_addr()
9387 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_set_mac_addr()
9400 spin_lock_bh(&tp->lock); in tg3_set_mac_addr()
9401 __tg3_set_mac_addr(tp, skip_mac_1); in tg3_set_mac_addr()
9403 spin_unlock_bh(&tp->lock); in tg3_set_mac_addr()
9408 /* tp->lock is held. */
9409 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr, in tg3_set_bdinfo() argument
9413 tg3_write_mem(tp, in tg3_set_bdinfo()
9416 tg3_write_mem(tp, in tg3_set_bdinfo()
9419 tg3_write_mem(tp, in tg3_set_bdinfo()
9423 if (!tg3_flag(tp, 5705_PLUS)) in tg3_set_bdinfo()
9424 tg3_write_mem(tp, in tg3_set_bdinfo()
9430 static void tg3_coal_tx_init(struct tg3 *tp, struct ethtool_coalesce *ec) in tg3_coal_tx_init() argument
9434 if (!tg3_flag(tp, ENABLE_TSS)) { in tg3_coal_tx_init()
9435 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9436 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9437 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9443 for (; i < tp->txq_cnt; i++) { in tg3_coal_tx_init()
9447 tw32(reg, ec->tx_coalesce_usecs); in tg3_coal_tx_init()
9449 tw32(reg, ec->tx_max_coalesced_frames); in tg3_coal_tx_init()
9451 tw32(reg, ec->tx_max_coalesced_frames_irq); in tg3_coal_tx_init()
9455 for (; i < tp->irq_max - 1; i++) { in tg3_coal_tx_init()
9462 static void tg3_coal_rx_init(struct tg3 *tp, struct ethtool_coalesce *ec) in tg3_coal_rx_init() argument
9465 u32 limit = tp->rxq_cnt; in tg3_coal_rx_init()
9467 if (!tg3_flag(tp, ENABLE_RSS)) { in tg3_coal_rx_init()
9468 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9469 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9470 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9471 limit--; in tg3_coal_rx_init()
9482 tw32(reg, ec->rx_coalesce_usecs); in tg3_coal_rx_init()
9484 tw32(reg, ec->rx_max_coalesced_frames); in tg3_coal_rx_init()
9486 tw32(reg, ec->rx_max_coalesced_frames_irq); in tg3_coal_rx_init()
9489 for (; i < tp->irq_max - 1; i++) { in tg3_coal_rx_init()
9496 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec) in __tg3_set_coalesce() argument
9498 tg3_coal_tx_init(tp, ec); in __tg3_set_coalesce()
9499 tg3_coal_rx_init(tp, ec); in __tg3_set_coalesce()
9501 if (!tg3_flag(tp, 5705_PLUS)) { in __tg3_set_coalesce()
9502 u32 val = ec->stats_block_coalesce_usecs; in __tg3_set_coalesce()
9504 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq); in __tg3_set_coalesce()
9505 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq); in __tg3_set_coalesce()
9507 if (!tp->link_up) in __tg3_set_coalesce()
9514 /* tp->lock is held. */
9515 static void tg3_tx_rcbs_disable(struct tg3 *tp) in tg3_tx_rcbs_disable() argument
9520 if (!tg3_flag(tp, 5705_PLUS)) in tg3_tx_rcbs_disable()
9522 else if (tg3_flag(tp, 5717_PLUS)) in tg3_tx_rcbs_disable()
9524 else if (tg3_flag(tp, 57765_CLASS) || in tg3_tx_rcbs_disable()
9525 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_tx_rcbs_disable()
9532 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS, in tg3_tx_rcbs_disable()
9536 /* tp->lock is held. */
9537 static void tg3_tx_rcbs_init(struct tg3 *tp) in tg3_tx_rcbs_init() argument
9542 if (tg3_flag(tp, ENABLE_TSS)) in tg3_tx_rcbs_init()
9545 for (; i < tp->irq_max; i++, txrcb += TG3_BDINFO_SIZE) { in tg3_tx_rcbs_init()
9546 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_tx_rcbs_init()
9548 if (!tnapi->tx_ring) in tg3_tx_rcbs_init()
9551 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping, in tg3_tx_rcbs_init()
9557 /* tp->lock is held. */
9558 static void tg3_rx_ret_rcbs_disable(struct tg3 *tp) in tg3_rx_ret_rcbs_disable() argument
9563 if (tg3_flag(tp, 5717_PLUS)) in tg3_rx_ret_rcbs_disable()
9565 else if (!tg3_flag(tp, 5705_PLUS)) in tg3_rx_ret_rcbs_disable()
9567 else if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_rx_ret_rcbs_disable()
9568 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_rx_ret_rcbs_disable()
9569 tg3_flag(tp, 57765_CLASS)) in tg3_rx_ret_rcbs_disable()
9576 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS, in tg3_rx_ret_rcbs_disable()
9580 /* tp->lock is held. */
9581 static void tg3_rx_ret_rcbs_init(struct tg3 *tp) in tg3_rx_ret_rcbs_init() argument
9586 if (tg3_flag(tp, ENABLE_RSS)) in tg3_rx_ret_rcbs_init()
9589 for (; i < tp->irq_max; i++, rxrcb += TG3_BDINFO_SIZE) { in tg3_rx_ret_rcbs_init()
9590 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_rx_ret_rcbs_init()
9592 if (!tnapi->rx_rcb) in tg3_rx_ret_rcbs_init()
9595 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping, in tg3_rx_ret_rcbs_init()
9596 (tp->rx_ret_ring_mask + 1) << in tg3_rx_ret_rcbs_init()
9601 /* tp->lock is held. */
9602 static void tg3_rings_reset(struct tg3 *tp) in tg3_rings_reset() argument
9606 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_rings_reset()
9608 tg3_tx_rcbs_disable(tp); in tg3_rings_reset()
9610 tg3_rx_ret_rcbs_disable(tp); in tg3_rings_reset()
9613 tw32_mailbox_f(tp->napi[0].int_mbox, 1); in tg3_rings_reset()
9614 tp->napi[0].chk_msi_cnt = 0; in tg3_rings_reset()
9615 tp->napi[0].last_rx_cons = 0; in tg3_rings_reset()
9616 tp->napi[0].last_tx_cons = 0; in tg3_rings_reset()
9619 if (tg3_flag(tp, SUPPORT_MSIX)) { in tg3_rings_reset()
9620 for (i = 1; i < tp->irq_max; i++) { in tg3_rings_reset()
9621 tp->napi[i].tx_prod = 0; in tg3_rings_reset()
9622 tp->napi[i].tx_cons = 0; in tg3_rings_reset()
9623 if (tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
9624 tw32_mailbox(tp->napi[i].prodmbox, 0); in tg3_rings_reset()
9625 tw32_rx_mbox(tp->napi[i].consmbox, 0); in tg3_rings_reset()
9626 tw32_mailbox_f(tp->napi[i].int_mbox, 1); in tg3_rings_reset()
9627 tp->napi[i].chk_msi_cnt = 0; in tg3_rings_reset()
9628 tp->napi[i].last_rx_cons = 0; in tg3_rings_reset()
9629 tp->napi[i].last_tx_cons = 0; in tg3_rings_reset()
9631 if (!tg3_flag(tp, ENABLE_TSS)) in tg3_rings_reset()
9632 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9634 tp->napi[0].tx_prod = 0; in tg3_rings_reset()
9635 tp->napi[0].tx_cons = 0; in tg3_rings_reset()
9636 tw32_mailbox(tp->napi[0].prodmbox, 0); in tg3_rings_reset()
9637 tw32_rx_mbox(tp->napi[0].consmbox, 0); in tg3_rings_reset()
9640 /* Make sure the NIC-based send BD rings are disabled. */ in tg3_rings_reset()
9641 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_rings_reset()
9648 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9652 ((u64) tnapi->status_mapping >> 32)); in tg3_rings_reset()
9654 ((u64) tnapi->status_mapping & 0xffffffff)); in tg3_rings_reset()
9658 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) { in tg3_rings_reset()
9659 u64 mapping = (u64)tnapi->status_mapping; in tg3_rings_reset()
9665 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE); in tg3_rings_reset()
9668 tg3_tx_rcbs_init(tp); in tg3_rings_reset()
9669 tg3_rx_ret_rcbs_init(tp); in tg3_rings_reset()
9672 static void tg3_setup_rxbd_thresholds(struct tg3 *tp) in tg3_setup_rxbd_thresholds() argument
9676 if (!tg3_flag(tp, 5750_PLUS) || in tg3_setup_rxbd_thresholds()
9677 tg3_flag(tp, 5780_CLASS) || in tg3_setup_rxbd_thresholds()
9678 tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_setup_rxbd_thresholds()
9679 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_setup_rxbd_thresholds()
9680 tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9682 else if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_setup_rxbd_thresholds()
9683 tg3_asic_rev(tp) == ASIC_REV_5787) in tg3_setup_rxbd_thresholds()
9688 nic_rep_thresh = min(bdcache_maxcnt / 2, tp->rx_std_max_post); in tg3_setup_rxbd_thresholds()
9689 host_rep_thresh = max_t(u32, tp->rx_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9694 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9697 if (!tg3_flag(tp, JUMBO_CAPABLE) || tg3_flag(tp, 5780_CLASS)) in tg3_setup_rxbd_thresholds()
9702 host_rep_thresh = max_t(u32, tp->rx_jumbo_pending / 8, 1); in tg3_setup_rxbd_thresholds()
9707 if (tg3_flag(tp, 57765_PLUS)) in tg3_setup_rxbd_thresholds()
9735 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all) in tg3_set_multi() argument
9746 struct tg3 *tp = netdev_priv(dev); in __tg3_set_rx_mode() local
9749 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC | in __tg3_set_rx_mode()
9756 if (!tg3_flag(tp, ENABLE_ASF)) in __tg3_set_rx_mode()
9760 if (dev->flags & IFF_PROMISC) { in __tg3_set_rx_mode()
9763 } else if (dev->flags & IFF_ALLMULTI) { in __tg3_set_rx_mode()
9765 tg3_set_multi(tp, 1); in __tg3_set_rx_mode()
9768 tg3_set_multi(tp, 0); in __tg3_set_rx_mode()
9778 crc = calc_crc(ha->addr, ETH_ALEN); in __tg3_set_rx_mode()
9791 if (netdev_uc_count(dev) > TG3_MAX_UCAST_ADDR(tp)) { in __tg3_set_rx_mode()
9793 } else if (!(dev->flags & IFF_PROMISC)) { in __tg3_set_rx_mode()
9799 __tg3_set_one_mac_addr(tp, ha->addr, in __tg3_set_rx_mode()
9800 i + TG3_UCAST_ADDR_IDX(tp)); in __tg3_set_rx_mode()
9805 if (rx_mode != tp->rx_mode) { in __tg3_set_rx_mode()
9806 tp->rx_mode = rx_mode; in __tg3_set_rx_mode()
9812 static void tg3_rss_init_dflt_indir_tbl(struct tg3 *tp, u32 qcnt) in tg3_rss_init_dflt_indir_tbl() argument
9817 tp->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, qcnt); in tg3_rss_init_dflt_indir_tbl()
9820 static void tg3_rss_check_indir_tbl(struct tg3 *tp) in tg3_rss_check_indir_tbl() argument
9824 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_rss_check_indir_tbl()
9827 if (tp->rxq_cnt == 1) { in tg3_rss_check_indir_tbl()
9828 memset(&tp->rss_ind_tbl[0], 0, sizeof(tp->rss_ind_tbl)); in tg3_rss_check_indir_tbl()
9834 if (tp->rss_ind_tbl[i] >= tp->rxq_cnt) in tg3_rss_check_indir_tbl()
9839 tg3_rss_init_dflt_indir_tbl(tp, tp->rxq_cnt); in tg3_rss_check_indir_tbl()
9842 static void tg3_rss_write_indir_tbl(struct tg3 *tp) in tg3_rss_write_indir_tbl() argument
9848 u32 val = tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9852 val |= tp->rss_ind_tbl[i]; in tg3_rss_write_indir_tbl()
9859 static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp) in tg3_lso_rd_dma_workaround_bit() argument
9861 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_lso_rd_dma_workaround_bit()
9867 /* tp->lock is held. */
9868 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy) in tg3_reset_hw() argument
9872 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_reset_hw()
9874 tg3_disable_ints(tp); in tg3_reset_hw()
9876 tg3_stop_fw(tp); in tg3_reset_hw()
9878 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT); in tg3_reset_hw()
9880 if (tg3_flag(tp, INIT_COMPLETE)) in tg3_reset_hw()
9881 tg3_abort_hw(tp, 1); in tg3_reset_hw()
9883 if ((tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_reset_hw()
9884 !(tp->phy_flags & TG3_PHYFLG_USER_CONFIGURED)) { in tg3_reset_hw()
9885 tg3_phy_pull_config(tp); in tg3_reset_hw()
9886 tg3_eee_pull_config(tp, NULL); in tg3_reset_hw()
9887 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_reset_hw()
9891 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP) in tg3_reset_hw()
9892 tg3_setup_eee(tp); in tg3_reset_hw()
9895 tg3_phy_reset(tp); in tg3_reset_hw()
9897 err = tg3_chip_reset(tp); in tg3_reset_hw()
9901 tg3_write_sig_legacy(tp, RESET_KIND_INIT); in tg3_reset_hw()
9903 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) { in tg3_reset_hw()
9924 if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_reset_hw()
9939 if (tg3_flag(tp, L1PLLPD_EN)) { in tg3_reset_hw()
9953 if (tg3_flag(tp, 57765_CLASS)) { in tg3_reset_hw()
9954 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) { in tg3_reset_hw()
9969 if (tg3_chip_rev(tp) != CHIPREV_57765_AX) { in tg3_reset_hw()
10003 if (!tg3_flag(tp, CPMU_PRESENT)) { in tg3_reset_hw()
10004 if (!tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
10005 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT; in tg3_reset_hw()
10006 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); in tg3_reset_hw()
10009 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0 && in tg3_reset_hw()
10010 tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
10016 if (tg3_flag(tp, ENABLE_APE)) { in tg3_reset_hw()
10027 if (tg3_chip_rev(tp) == CHIPREV_5704_BX) { in tg3_reset_hw()
10039 err = tg3_init_rings(tp); in tg3_reset_hw()
10043 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10046 if (tg3_chip_rev_id(tp) == CHIPREV_ID_57765_A0) in tg3_reset_hw()
10048 if (!tg3_flag(tp, 57765_CLASS) && in tg3_reset_hw()
10049 tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_reset_hw()
10050 tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_reset_hw()
10052 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl); in tg3_reset_hw()
10053 } else if (tg3_asic_rev(tp) != ASIC_REV_5784 && in tg3_reset_hw()
10054 tg3_asic_rev(tp) != ASIC_REV_5761) { in tg3_reset_hw()
10058 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_reset_hw()
10061 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS | in tg3_reset_hw()
10065 tp->grc_mode |= GRC_MODE_HOST_SENDBDS; in tg3_reset_hw()
10067 /* Pseudo-header checksum is done by hardware logic and not in tg3_reset_hw()
10068 * the offload processers, so make the chip do the pseudo- in tg3_reset_hw()
10070 * convenient to do the pseudo-header checksum in software in tg3_reset_hw()
10073 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM; in tg3_reset_hw()
10076 if (tp->rxptpctl) in tg3_reset_hw()
10078 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_reset_hw()
10080 if (tg3_flag(tp, PTP_CAPABLE)) in tg3_reset_hw()
10083 tw32(GRC_MODE, tp->grc_mode | val); in tg3_reset_hw()
10089 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_reset_hw()
10090 tp->pdev->subsystem_device == TG3PCI_SUBDEVICE_ID_DELL_5762) { in tg3_reset_hw()
10102 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
10104 } else if (tg3_asic_rev(tp) != ASIC_REV_5705) { in tg3_reset_hw()
10106 if (tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_reset_hw()
10112 } else if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10115 fw_len = tp->fw_len; in tg3_reset_hw()
10116 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1); in tg3_reset_hw()
10120 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00); in tg3_reset_hw()
10123 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10125 tp->bufmgr_config.mbuf_read_dma_low_water); in tg3_reset_hw()
10127 tp->bufmgr_config.mbuf_mac_rx_low_water); in tg3_reset_hw()
10129 tp->bufmgr_config.mbuf_high_water); in tg3_reset_hw()
10132 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo); in tg3_reset_hw()
10134 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo); in tg3_reset_hw()
10136 tp->bufmgr_config.mbuf_high_water_jumbo); in tg3_reset_hw()
10139 tp->bufmgr_config.dma_low_water); in tg3_reset_hw()
10141 tp->bufmgr_config.dma_high_water); in tg3_reset_hw()
10144 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_reset_hw()
10146 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_reset_hw()
10147 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_reset_hw()
10148 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10149 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) in tg3_reset_hw()
10158 netdev_err(tp->dev, "%s cannot enable BUFMGR\n", __func__); in tg3_reset_hw()
10159 return -ENODEV; in tg3_reset_hw()
10162 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5906_A1) in tg3_reset_hw()
10165 tg3_setup_rxbd_thresholds(tp); in tg3_reset_hw()
10185 ((u64) tpr->rx_std_mapping >> 32)); in tg3_reset_hw()
10187 ((u64) tpr->rx_std_mapping & 0xffffffff)); in tg3_reset_hw()
10188 if (!tg3_flag(tp, 5717_PLUS)) in tg3_reset_hw()
10193 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10200 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10201 (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS))) { in tg3_reset_hw()
10203 if (tg3_flag(tp, JUMBO_RING_ENABLE)) { in tg3_reset_hw()
10205 ((u64) tpr->rx_jmb_mapping >> 32)); in tg3_reset_hw()
10207 ((u64) tpr->rx_jmb_mapping & 0xffffffff)); in tg3_reset_hw()
10208 val = TG3_RX_JMB_RING_SIZE(tp) << in tg3_reset_hw()
10212 if (!tg3_flag(tp, USE_JUMBO_BDFLAG) || in tg3_reset_hw()
10213 tg3_flag(tp, 57765_CLASS) || in tg3_reset_hw()
10214 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10222 if (tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10223 val = TG3_RX_STD_RING_SIZE(tp); in tg3_reset_hw()
10233 tpr->rx_std_prod_idx = tp->rx_pending; in tg3_reset_hw()
10234 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx); in tg3_reset_hw()
10236 tpr->rx_jmb_prod_idx = in tg3_reset_hw()
10237 tg3_flag(tp, JUMBO_RING_ENABLE) ? tp->rx_jumbo_pending : 0; in tg3_reset_hw()
10238 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); in tg3_reset_hw()
10240 tg3_rings_reset(tp); in tg3_reset_hw()
10243 __tg3_set_mac_addr(tp, false); in tg3_reset_hw()
10247 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN); in tg3_reset_hw()
10256 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10257 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10277 if (tg3_asic_rev(tp) == ASIC_REV_5717) in tg3_reset_hw()
10280 if (tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_reset_hw()
10281 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10282 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_reset_hw()
10287 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_reset_hw()
10288 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_reset_hw()
10289 if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10292 !tg3_flag(tp, IS_5788)) { in tg3_reset_hw()
10297 if (tg3_flag(tp, PCI_EXPRESS)) in tg3_reset_hw()
10300 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_reset_hw()
10301 tp->dma_limit = 0; in tg3_reset_hw()
10302 if (tp->dev->mtu <= ETH_DATA_LEN) { in tg3_reset_hw()
10304 tp->dma_limit = TG3_TX_BD_DMA_MAX_2K; in tg3_reset_hw()
10308 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
10309 tg3_flag(tp, HW_TSO_2) || in tg3_reset_hw()
10310 tg3_flag(tp, HW_TSO_3)) in tg3_reset_hw()
10313 if (tg3_flag(tp, 57765_PLUS) || in tg3_reset_hw()
10314 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10315 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_reset_hw()
10318 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10319 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10322 if (tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_reset_hw()
10323 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_reset_hw()
10324 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_reset_hw()
10325 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_reset_hw()
10326 tg3_flag(tp, 57765_PLUS)) { in tg3_reset_hw()
10329 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10335 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_reset_hw()
10336 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10347 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_reset_hw()
10348 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10349 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10352 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10364 if (tg3_flag(tp, 5750_PLUS)) { in tg3_reset_hw()
10369 tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10390 __tg3_set_coalesce(tp, &tp->coal); in tg3_reset_hw()
10392 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
10398 ((u64) tp->stats_mapping >> 32)); in tg3_reset_hw()
10400 ((u64) tp->stats_mapping & 0xffffffff)); in tg3_reset_hw()
10409 tg3_write_mem(tp, i, 0); in tg3_reset_hw()
10414 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode); in tg3_reset_hw()
10418 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10421 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { in tg3_reset_hw()
10422 tp->phy_flags &= ~TG3_PHYFLG_PARALLEL_DETECT; in tg3_reset_hw()
10428 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | in tg3_reset_hw()
10431 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
10432 tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_reset_hw()
10433 if (!tg3_flag(tp, 5705_PLUS) && in tg3_reset_hw()
10434 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10435 tg3_asic_rev(tp) != ASIC_REV_5700) in tg3_reset_hw()
10436 tp->mac_mode |= MAC_MODE_LINK_POLARITY; in tg3_reset_hw()
10437 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR); in tg3_reset_hw()
10440 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants(). in tg3_reset_hw()
10446 if (!tg3_flag(tp, IS_NIC)) { in tg3_reset_hw()
10453 if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_reset_hw()
10457 if (tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_reset_hw()
10460 tp->grc_local_ctrl &= ~gpio_mask; in tg3_reset_hw()
10461 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask; in tg3_reset_hw()
10464 if (tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_reset_hw()
10465 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_reset_hw()
10468 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10471 if (tg3_flag(tp, USING_MSIX)) { in tg3_reset_hw()
10474 if (tp->irq_cnt > 1) in tg3_reset_hw()
10476 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_reset_hw()
10481 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_reset_hw()
10492 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_reset_hw()
10493 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_reset_hw()
10494 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_reset_hw()
10495 (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 || in tg3_reset_hw()
10496 tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A2)) { in tg3_reset_hw()
10499 !tg3_flag(tp, IS_5788)) { in tg3_reset_hw()
10505 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
10508 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_reset_hw()
10514 if (tg3_flag(tp, PCIX_MODE)) { in tg3_reset_hw()
10517 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10519 if (tg3_asic_rev(tp) == ASIC_REV_5703) { in tg3_reset_hw()
10522 } else if (tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_reset_hw()
10526 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD, in tg3_reset_hw()
10533 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_reset_hw()
10534 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_reset_hw()
10536 if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp)) in tg3_reset_hw()
10541 val |= tg3_lso_rd_dma_workaround_bit(tp); in tg3_reset_hw()
10543 tg3_flag_set(tp, 5719_5720_RDMA_BUG); in tg3_reset_hw()
10548 if (!tg3_flag(tp, 5705_PLUS)) in tg3_reset_hw()
10551 if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_reset_hw()
10560 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_reset_hw()
10564 if (tg3_flag(tp, HW_TSO_1) || in tg3_reset_hw()
10565 tg3_flag(tp, HW_TSO_2) || in tg3_reset_hw()
10566 tg3_flag(tp, HW_TSO_3)) in tg3_reset_hw()
10569 if (tg3_flag(tp, ENABLE_TSS)) in tg3_reset_hw()
10574 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { in tg3_reset_hw()
10575 err = tg3_load_5701_a0_firmware_fix(tp); in tg3_reset_hw()
10580 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_reset_hw()
10584 tg3_load_57766_firmware(tp); in tg3_reset_hw()
10587 if (tg3_flag(tp, TSO_CAPABLE)) { in tg3_reset_hw()
10588 err = tg3_load_tso_firmware(tp); in tg3_reset_hw()
10593 tp->tx_mode = TX_MODE_ENABLE; in tg3_reset_hw()
10595 if (tg3_flag(tp, 5755_PLUS) || in tg3_reset_hw()
10596 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_reset_hw()
10597 tp->tx_mode |= TX_MODE_MBUF_LOCKUP_FIX; in tg3_reset_hw()
10599 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_reset_hw()
10600 tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_reset_hw()
10602 tp->tx_mode &= ~val; in tg3_reset_hw()
10603 tp->tx_mode |= tr32(MAC_TX_MODE) & val; in tg3_reset_hw()
10606 tw32_f(MAC_TX_MODE, tp->tx_mode); in tg3_reset_hw()
10609 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_reset_hw()
10612 tg3_rss_write_indir_tbl(tp); in tg3_reset_hw()
10620 tp->rx_mode = RX_MODE_ENABLE; in tg3_reset_hw()
10621 if (tg3_flag(tp, 5755_PLUS)) in tg3_reset_hw()
10622 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE; in tg3_reset_hw()
10624 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_reset_hw()
10625 tp->rx_mode |= RX_MODE_IPV4_FRAG_FIX; in tg3_reset_hw()
10627 if (tg3_flag(tp, ENABLE_RSS)) in tg3_reset_hw()
10628 tp->rx_mode |= RX_MODE_RSS_ENABLE | in tg3_reset_hw()
10635 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10638 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_reset_hw()
10641 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10645 tw32_f(MAC_RX_MODE, tp->rx_mode); in tg3_reset_hw()
10648 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_reset_hw()
10649 if ((tg3_asic_rev(tp) == ASIC_REV_5704) && in tg3_reset_hw()
10650 !(tp->phy_flags & TG3_PHYFLG_SERDES_PREEMPHASIS)) { in tg3_reset_hw()
10652 /* only if the signal pre-emphasis bit is not set */ in tg3_reset_hw()
10658 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) in tg3_reset_hw()
10665 if (tg3_flag(tp, 57765_CLASS)) in tg3_reset_hw()
10671 if (tg3_asic_rev(tp) == ASIC_REV_5704 && in tg3_reset_hw()
10672 (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_reset_hw()
10673 /* Use hardware link auto-negotiation */ in tg3_reset_hw()
10674 tg3_flag_set(tp, HW_AUTONEG); in tg3_reset_hw()
10677 if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_reset_hw()
10678 tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_reset_hw()
10683 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT; in tg3_reset_hw()
10684 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT; in tg3_reset_hw()
10685 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl); in tg3_reset_hw()
10688 if (!tg3_flag(tp, USE_PHYLIB)) { in tg3_reset_hw()
10689 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_reset_hw()
10690 tp->phy_flags &= ~TG3_PHYFLG_IS_LOW_POWER; in tg3_reset_hw()
10692 err = tg3_setup_phy(tp, false); in tg3_reset_hw()
10696 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_reset_hw()
10697 !(tp->phy_flags & TG3_PHYFLG_IS_FET)) { in tg3_reset_hw()
10701 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) { in tg3_reset_hw()
10702 tg3_writephy(tp, MII_TG3_TEST1, in tg3_reset_hw()
10704 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &tmp); in tg3_reset_hw()
10709 __tg3_set_rx_mode(tp->dev); in tg3_reset_hw()
10717 if (tg3_flag(tp, 5705_PLUS) && !tg3_flag(tp, 5780_CLASS)) in tg3_reset_hw()
10721 if (tg3_flag(tp, ENABLE_ASF)) in tg3_reset_hw()
10722 limit -= 4; in tg3_reset_hw()
10771 if (tg3_flag(tp, ENABLE_APE)) in tg3_reset_hw()
10773 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS, in tg3_reset_hw()
10776 tg3_write_sig_post_reset(tp, RESET_KIND_INIT); in tg3_reset_hw()
10782 * packet processing. Invoked with tp->lock held.
10784 static int tg3_init_hw(struct tg3 *tp, bool reset_phy) in tg3_init_hw() argument
10790 tg3_enable_register_access(tp); in tg3_init_hw()
10791 tg3_poll_fw(tp); in tg3_init_hw()
10793 tg3_switch_clocks(tp); in tg3_init_hw()
10797 return tg3_reset_hw(tp, reset_phy); in tg3_init_hw()
10801 static void tg3_sd_scan_scratchpad(struct tg3 *tp, struct tg3_ocir *ocir) in tg3_sd_scan_scratchpad() argument
10807 tg3_ape_scratchpad_read(tp, (u32 *) ocir, off, len); in tg3_sd_scan_scratchpad()
10809 if (ocir->signature != TG3_OCIR_SIG_MAGIC || in tg3_sd_scan_scratchpad()
10810 !(ocir->version_flags & TG3_OCIR_FLAG_ACTIVE)) in tg3_sd_scan_scratchpad()
10820 struct tg3 *tp = dev_get_drvdata(dev); in tg3_show_temp() local
10823 spin_lock_bh(&tp->lock); in tg3_show_temp()
10824 tg3_ape_scratchpad_read(tp, &temperature, attr->index, in tg3_show_temp()
10826 spin_unlock_bh(&tp->lock); in tg3_show_temp()
10846 static void tg3_hwmon_close(struct tg3 *tp) in tg3_hwmon_close() argument
10848 if (tp->hwmon_dev) { in tg3_hwmon_close()
10849 hwmon_device_unregister(tp->hwmon_dev); in tg3_hwmon_close()
10850 tp->hwmon_dev = NULL; in tg3_hwmon_close()
10854 static void tg3_hwmon_open(struct tg3 *tp) in tg3_hwmon_open() argument
10858 struct pci_dev *pdev = tp->pdev; in tg3_hwmon_open()
10861 tg3_sd_scan_scratchpad(tp, ocirs); in tg3_hwmon_open()
10874 tp->hwmon_dev = hwmon_device_register_with_groups(&pdev->dev, "tg3", in tg3_hwmon_open()
10875 tp, tg3_groups); in tg3_hwmon_open()
10876 if (IS_ERR(tp->hwmon_dev)) { in tg3_hwmon_open()
10877 tp->hwmon_dev = NULL; in tg3_hwmon_open()
10878 dev_err(&pdev->dev, "Cannot register hwmon device, aborting\n"); in tg3_hwmon_open()
10882 static inline void tg3_hwmon_close(struct tg3 *tp) { } in tg3_hwmon_close() argument
10883 static inline void tg3_hwmon_open(struct tg3 *tp) { } in tg3_hwmon_open() argument
10889 (PSTAT)->low += __val; \
10890 if ((PSTAT)->low < __val) \
10891 (PSTAT)->high += 1; \
10894 static void tg3_periodic_fetch_stats(struct tg3 *tp) in tg3_periodic_fetch_stats() argument
10896 struct tg3_hw_stats *sp = tp->hw_stats; in tg3_periodic_fetch_stats()
10898 if (!tp->link_up) in tg3_periodic_fetch_stats()
10901 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10902 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS); in tg3_periodic_fetch_stats()
10903 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT); in tg3_periodic_fetch_stats()
10904 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT); in tg3_periodic_fetch_stats()
10905 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS); in tg3_periodic_fetch_stats()
10906 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS); in tg3_periodic_fetch_stats()
10907 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS); in tg3_periodic_fetch_stats()
10908 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED); in tg3_periodic_fetch_stats()
10909 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL); in tg3_periodic_fetch_stats()
10910 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL); in tg3_periodic_fetch_stats()
10911 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST); in tg3_periodic_fetch_stats()
10912 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST); in tg3_periodic_fetch_stats()
10913 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST); in tg3_periodic_fetch_stats()
10914 if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) && in tg3_periodic_fetch_stats()
10915 (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low + in tg3_periodic_fetch_stats()
10916 sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) { in tg3_periodic_fetch_stats()
10920 val &= ~tg3_lso_rd_dma_workaround_bit(tp); in tg3_periodic_fetch_stats()
10922 tg3_flag_clear(tp, 5719_5720_RDMA_BUG); in tg3_periodic_fetch_stats()
10925 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS); in tg3_periodic_fetch_stats()
10926 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS); in tg3_periodic_fetch_stats()
10927 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST); in tg3_periodic_fetch_stats()
10928 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST); in tg3_periodic_fetch_stats()
10929 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST); in tg3_periodic_fetch_stats()
10930 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS); in tg3_periodic_fetch_stats()
10931 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS); in tg3_periodic_fetch_stats()
10932 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD); in tg3_periodic_fetch_stats()
10933 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD); in tg3_periodic_fetch_stats()
10934 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD); in tg3_periodic_fetch_stats()
10935 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED); in tg3_periodic_fetch_stats()
10936 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG); in tg3_periodic_fetch_stats()
10937 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS); in tg3_periodic_fetch_stats()
10938 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE); in tg3_periodic_fetch_stats()
10940 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT); in tg3_periodic_fetch_stats()
10941 if (tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_periodic_fetch_stats()
10942 tg3_asic_rev(tp) != ASIC_REV_5762 && in tg3_periodic_fetch_stats()
10943 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0 && in tg3_periodic_fetch_stats()
10944 tg3_chip_rev_id(tp) != CHIPREV_ID_5720_A0) { in tg3_periodic_fetch_stats()
10945 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT); in tg3_periodic_fetch_stats()
10951 sp->rx_discards.low += val; in tg3_periodic_fetch_stats()
10952 if (sp->rx_discards.low < val) in tg3_periodic_fetch_stats()
10953 sp->rx_discards.high += 1; in tg3_periodic_fetch_stats()
10955 sp->mbuf_lwm_thresh_hit = sp->rx_discards; in tg3_periodic_fetch_stats()
10957 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT); in tg3_periodic_fetch_stats()
10960 static void tg3_chk_missed_msi(struct tg3 *tp) in tg3_chk_missed_msi() argument
10964 for (i = 0; i < tp->irq_cnt; i++) { in tg3_chk_missed_msi()
10965 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_chk_missed_msi()
10968 if (tnapi->last_rx_cons == tnapi->rx_rcb_ptr && in tg3_chk_missed_msi()
10969 tnapi->last_tx_cons == tnapi->tx_cons) { in tg3_chk_missed_msi()
10970 if (tnapi->chk_msi_cnt < 1) { in tg3_chk_missed_msi()
10971 tnapi->chk_msi_cnt++; in tg3_chk_missed_msi()
10977 tnapi->chk_msi_cnt = 0; in tg3_chk_missed_msi()
10978 tnapi->last_rx_cons = tnapi->rx_rcb_ptr; in tg3_chk_missed_msi()
10979 tnapi->last_tx_cons = tnapi->tx_cons; in tg3_chk_missed_msi()
10985 struct tg3 *tp = from_timer(tp, t, timer); in tg3_timer() local
10987 spin_lock(&tp->lock); in tg3_timer()
10989 if (tp->irq_sync || tg3_flag(tp, RESET_TASK_PENDING)) { in tg3_timer()
10990 spin_unlock(&tp->lock); in tg3_timer()
10994 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_timer()
10995 tg3_flag(tp, 57765_CLASS)) in tg3_timer()
10996 tg3_chk_missed_msi(tp); in tg3_timer()
10998 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { in tg3_timer()
11003 if (!tg3_flag(tp, TAGGED_STATUS)) { in tg3_timer()
11004 /* All of this garbage is because when using non-tagged in tg3_timer()
11008 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) { in tg3_timer()
11010 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT); in tg3_timer()
11012 tw32(HOSTCC_MODE, tp->coalesce_mode | in tg3_timer()
11017 spin_unlock(&tp->lock); in tg3_timer()
11018 tg3_reset_task_schedule(tp); in tg3_timer()
11024 if (!--tp->timer_counter) { in tg3_timer()
11025 if (tg3_flag(tp, 5705_PLUS)) in tg3_timer()
11026 tg3_periodic_fetch_stats(tp); in tg3_timer()
11028 if (tp->setlpicnt && !--tp->setlpicnt) in tg3_timer()
11029 tg3_phy_eee_enable(tp); in tg3_timer()
11031 if (tg3_flag(tp, USE_LINKCHG_REG)) { in tg3_timer()
11038 if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) { in tg3_timer()
11045 tg3_setup_phy(tp, false); in tg3_timer()
11046 } else if (tg3_flag(tp, POLL_SERDES)) { in tg3_timer()
11050 if (tp->link_up && in tg3_timer()
11054 if (!tp->link_up && in tg3_timer()
11060 if (!tp->serdes_counter) { in tg3_timer()
11062 (tp->mac_mode & in tg3_timer()
11065 tw32_f(MAC_MODE, tp->mac_mode); in tg3_timer()
11068 tg3_setup_phy(tp, false); in tg3_timer()
11070 } else if ((tp->phy_flags & TG3_PHYFLG_MII_SERDES) && in tg3_timer()
11071 tg3_flag(tp, 5780_CLASS)) { in tg3_timer()
11072 tg3_serdes_parallel_detect(tp); in tg3_timer()
11073 } else if (tg3_flag(tp, POLL_CPMU_LINK)) { in tg3_timer()
11078 if (link_up != tp->link_up) in tg3_timer()
11079 tg3_setup_phy(tp, false); in tg3_timer()
11082 tp->timer_counter = tp->timer_multiplier; in tg3_timer()
11102 if (!--tp->asf_counter) { in tg3_timer()
11103 if (tg3_flag(tp, ENABLE_ASF) && !tg3_flag(tp, ENABLE_APE)) { in tg3_timer()
11104 tg3_wait_for_event_ack(tp); in tg3_timer()
11106 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, in tg3_timer()
11108 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4); in tg3_timer()
11109 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, in tg3_timer()
11112 tg3_generate_fw_event(tp); in tg3_timer()
11114 tp->asf_counter = tp->asf_multiplier; in tg3_timer()
11118 tg3_send_ape_heartbeat(tp, TG3_APE_HB_INTERVAL); in tg3_timer()
11120 spin_unlock(&tp->lock); in tg3_timer()
11123 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer()
11124 add_timer(&tp->timer); in tg3_timer()
11127 static void tg3_timer_init(struct tg3 *tp) in tg3_timer_init() argument
11129 if (tg3_flag(tp, TAGGED_STATUS) && in tg3_timer_init()
11130 tg3_asic_rev(tp) != ASIC_REV_5717 && in tg3_timer_init()
11131 !tg3_flag(tp, 57765_CLASS)) in tg3_timer_init()
11132 tp->timer_offset = HZ; in tg3_timer_init()
11134 tp->timer_offset = HZ / 10; in tg3_timer_init()
11136 BUG_ON(tp->timer_offset > HZ); in tg3_timer_init()
11138 tp->timer_multiplier = (HZ / tp->timer_offset); in tg3_timer_init()
11139 tp->asf_multiplier = (HZ / tp->timer_offset) * in tg3_timer_init()
11142 timer_setup(&tp->timer, tg3_timer, 0); in tg3_timer_init()
11145 static void tg3_timer_start(struct tg3 *tp) in tg3_timer_start() argument
11147 tp->asf_counter = tp->asf_multiplier; in tg3_timer_start()
11148 tp->timer_counter = tp->timer_multiplier; in tg3_timer_start()
11150 tp->timer.expires = jiffies + tp->timer_offset; in tg3_timer_start()
11151 add_timer(&tp->timer); in tg3_timer_start()
11154 static void tg3_timer_stop(struct tg3 *tp) in tg3_timer_stop() argument
11156 del_timer_sync(&tp->timer); in tg3_timer_stop()
11159 /* Restart hardware after configuration changes, self-test, etc.
11160 * Invoked with tp->lock held.
11162 static int tg3_restart_hw(struct tg3 *tp, bool reset_phy) in tg3_restart_hw() argument
11163 __releases(tp->lock) in tg3_restart_hw()
11164 __acquires(tp->lock) in tg3_restart_hw()
11168 err = tg3_init_hw(tp, reset_phy); in tg3_restart_hw()
11170 netdev_err(tp->dev, in tg3_restart_hw()
11171 "Failed to re-initialize device, aborting\n"); in tg3_restart_hw()
11172 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_restart_hw()
11173 tg3_full_unlock(tp); in tg3_restart_hw()
11174 tg3_timer_stop(tp); in tg3_restart_hw()
11175 tp->irq_sync = 0; in tg3_restart_hw()
11176 tg3_napi_enable(tp); in tg3_restart_hw()
11177 dev_close(tp->dev); in tg3_restart_hw()
11178 tg3_full_lock(tp, 0); in tg3_restart_hw()
11185 struct tg3 *tp = container_of(work, struct tg3, reset_task); in tg3_reset_task() local
11189 tg3_full_lock(tp, 0); in tg3_reset_task()
11191 if (tp->pcierr_recovery || !netif_running(tp->dev) || in tg3_reset_task()
11192 tp->pdev->error_state != pci_channel_io_normal) { in tg3_reset_task()
11193 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11194 tg3_full_unlock(tp); in tg3_reset_task()
11199 tg3_full_unlock(tp); in tg3_reset_task()
11201 tg3_phy_stop(tp); in tg3_reset_task()
11203 tg3_netif_stop(tp); in tg3_reset_task()
11205 tg3_full_lock(tp, 1); in tg3_reset_task()
11207 if (tg3_flag(tp, TX_RECOVERY_PENDING)) { in tg3_reset_task()
11208 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_reset_task()
11209 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_reset_task()
11210 tg3_flag_set(tp, MBOX_WRITE_REORDER); in tg3_reset_task()
11211 tg3_flag_clear(tp, TX_RECOVERY_PENDING); in tg3_reset_task()
11214 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_reset_task()
11215 err = tg3_init_hw(tp, true); in tg3_reset_task()
11217 tg3_full_unlock(tp); in tg3_reset_task()
11218 tp->irq_sync = 0; in tg3_reset_task()
11219 tg3_napi_enable(tp); in tg3_reset_task()
11223 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11224 dev_close(tp->dev); in tg3_reset_task()
11228 tg3_netif_start(tp); in tg3_reset_task()
11229 tg3_full_unlock(tp); in tg3_reset_task()
11230 tg3_phy_start(tp); in tg3_reset_task()
11231 tg3_flag_clear(tp, RESET_TASK_PENDING); in tg3_reset_task()
11236 static int tg3_request_irq(struct tg3 *tp, int irq_num) in tg3_request_irq() argument
11241 struct tg3_napi *tnapi = &tp->napi[irq_num]; in tg3_request_irq()
11243 if (tp->irq_cnt == 1) in tg3_request_irq()
11244 name = tp->dev->name; in tg3_request_irq()
11246 name = &tnapi->irq_lbl[0]; in tg3_request_irq()
11247 if (tnapi->tx_buffers && tnapi->rx_rcb) in tg3_request_irq()
11249 "%s-txrx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11250 else if (tnapi->tx_buffers) in tg3_request_irq()
11252 "%s-tx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11253 else if (tnapi->rx_rcb) in tg3_request_irq()
11255 "%s-rx-%d", tp->dev->name, irq_num); in tg3_request_irq()
11258 "%s-%d", tp->dev->name, irq_num); in tg3_request_irq()
11259 name[IFNAMSIZ-1] = 0; in tg3_request_irq()
11262 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_request_irq()
11264 if (tg3_flag(tp, 1SHOT_MSI)) in tg3_request_irq()
11269 if (tg3_flag(tp, TAGGED_STATUS)) in tg3_request_irq()
11274 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi); in tg3_request_irq()
11277 static int tg3_test_interrupt(struct tg3 *tp) in tg3_test_interrupt() argument
11279 struct tg3_napi *tnapi = &tp->napi[0]; in tg3_test_interrupt()
11280 struct net_device *dev = tp->dev; in tg3_test_interrupt()
11285 return -ENODEV; in tg3_test_interrupt()
11287 tg3_disable_ints(tp); in tg3_test_interrupt()
11289 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11295 if (tg3_flag(tp, 57765_PLUS)) { in tg3_test_interrupt()
11300 err = request_irq(tnapi->irq_vec, tg3_test_isr, in tg3_test_interrupt()
11301 IRQF_SHARED, dev->name, tnapi); in tg3_test_interrupt()
11305 tnapi->hw_status->status &= ~SD_STATUS_UPDATED; in tg3_test_interrupt()
11306 tg3_enable_ints(tp); in tg3_test_interrupt()
11308 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_test_interrupt()
11309 tnapi->coal_now); in tg3_test_interrupt()
11314 int_mbox = tr32_mailbox(tnapi->int_mbox); in tg3_test_interrupt()
11323 if (tg3_flag(tp, 57765_PLUS) && in tg3_test_interrupt()
11324 tnapi->hw_status->status_tag != tnapi->last_tag) in tg3_test_interrupt()
11325 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24); in tg3_test_interrupt()
11330 tg3_disable_ints(tp); in tg3_test_interrupt()
11332 free_irq(tnapi->irq_vec, tnapi); in tg3_test_interrupt()
11334 err = tg3_request_irq(tp, 0); in tg3_test_interrupt()
11341 if (tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, 1SHOT_MSI)) { in tg3_test_interrupt()
11348 return -EIO; in tg3_test_interrupt()
11354 static int tg3_test_msi(struct tg3 *tp) in tg3_test_msi() argument
11359 if (!tg3_flag(tp, USING_MSI)) in tg3_test_msi()
11365 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_test_msi()
11366 pci_write_config_word(tp->pdev, PCI_COMMAND, in tg3_test_msi()
11369 err = tg3_test_interrupt(tp); in tg3_test_msi()
11371 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_test_msi()
11377 if (err != -EIO) in tg3_test_msi()
11381 netdev_warn(tp->dev, "No interrupt was generated using MSI. Switching " in tg3_test_msi()
11385 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11387 pci_disable_msi(tp->pdev); in tg3_test_msi()
11389 tg3_flag_clear(tp, USING_MSI); in tg3_test_msi()
11390 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_test_msi()
11392 err = tg3_request_irq(tp, 0); in tg3_test_msi()
11399 tg3_full_lock(tp, 1); in tg3_test_msi()
11401 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_test_msi()
11402 err = tg3_init_hw(tp, true); in tg3_test_msi()
11404 tg3_full_unlock(tp); in tg3_test_msi()
11407 free_irq(tp->napi[0].irq_vec, &tp->napi[0]); in tg3_test_msi()
11412 static int tg3_request_firmware(struct tg3 *tp) in tg3_request_firmware() argument
11416 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) { in tg3_request_firmware()
11417 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n", in tg3_request_firmware()
11418 tp->fw_needed); in tg3_request_firmware()
11419 return -ENOENT; in tg3_request_firmware()
11422 fw_hdr = (struct tg3_firmware_hdr *)tp->fw->data; in tg3_request_firmware()
11429 tp->fw_len = be32_to_cpu(fw_hdr->len); /* includes bss */ in tg3_request_firmware()
11430 if (tp->fw_len < (tp->fw->size - TG3_FW_HDR_LEN)) { in tg3_request_firmware()
11431 netdev_err(tp->dev, "bogus length %d in \"%s\"\n", in tg3_request_firmware()
11432 tp->fw_len, tp->fw_needed); in tg3_request_firmware()
11433 release_firmware(tp->fw); in tg3_request_firmware()
11434 tp->fw = NULL; in tg3_request_firmware()
11435 return -EINVAL; in tg3_request_firmware()
11439 tp->fw_needed = NULL; in tg3_request_firmware()
11443 static u32 tg3_irq_count(struct tg3 *tp) in tg3_irq_count() argument
11445 u32 irq_cnt = max(tp->rxq_cnt, tp->txq_cnt); in tg3_irq_count()
11449 * In multiqueue MSI-X mode, the first MSI-X vector in tg3_irq_count()
11450 * only deals with link interrupts, etc, so we add in tg3_irq_count()
11453 irq_cnt = min_t(unsigned, irq_cnt + 1, tp->irq_max); in tg3_irq_count()
11459 static bool tg3_enable_msix(struct tg3 *tp) in tg3_enable_msix() argument
11464 tp->txq_cnt = tp->txq_req; in tg3_enable_msix()
11465 tp->rxq_cnt = tp->rxq_req; in tg3_enable_msix()
11466 if (!tp->rxq_cnt) in tg3_enable_msix()
11467 tp->rxq_cnt = netif_get_num_default_rss_queues(); in tg3_enable_msix()
11468 if (tp->rxq_cnt > tp->rxq_max) in tg3_enable_msix()
11469 tp->rxq_cnt = tp->rxq_max; in tg3_enable_msix()
11471 /* Disable multiple TX rings by default. Simple round-robin hardware in tg3_enable_msix()
11475 if (!tp->txq_req) in tg3_enable_msix()
11476 tp->txq_cnt = 1; in tg3_enable_msix()
11478 tp->irq_cnt = tg3_irq_count(tp); in tg3_enable_msix()
11480 for (i = 0; i < tp->irq_max; i++) { in tg3_enable_msix()
11485 rc = pci_enable_msix_range(tp->pdev, msix_ent, 1, tp->irq_cnt); in tg3_enable_msix()
11488 } else if (rc < tp->irq_cnt) { in tg3_enable_msix()
11489 netdev_notice(tp->dev, "Requested %d MSI-X vectors, received %d\n", in tg3_enable_msix()
11490 tp->irq_cnt, rc); in tg3_enable_msix()
11491 tp->irq_cnt = rc; in tg3_enable_msix()
11492 tp->rxq_cnt = max(rc - 1, 1); in tg3_enable_msix()
11493 if (tp->txq_cnt) in tg3_enable_msix()
11494 tp->txq_cnt = min(tp->rxq_cnt, tp->txq_max); in tg3_enable_msix()
11497 for (i = 0; i < tp->irq_max; i++) in tg3_enable_msix()
11498 tp->napi[i].irq_vec = msix_ent[i].vector; in tg3_enable_msix()
11500 if (netif_set_real_num_rx_queues(tp->dev, tp->rxq_cnt)) { in tg3_enable_msix()
11501 pci_disable_msix(tp->pdev); in tg3_enable_msix()
11505 if (tp->irq_cnt == 1) in tg3_enable_msix()
11508 tg3_flag_set(tp, ENABLE_RSS); in tg3_enable_msix()
11510 if (tp->txq_cnt > 1) in tg3_enable_msix()
11511 tg3_flag_set(tp, ENABLE_TSS); in tg3_enable_msix()
11513 netif_set_real_num_tx_queues(tp->dev, tp->txq_cnt); in tg3_enable_msix()
11518 static void tg3_ints_init(struct tg3 *tp) in tg3_ints_init() argument
11520 if ((tg3_flag(tp, SUPPORT_MSI) || tg3_flag(tp, SUPPORT_MSIX)) && in tg3_ints_init()
11521 !tg3_flag(tp, TAGGED_STATUS)) { in tg3_ints_init()
11525 netdev_warn(tp->dev, in tg3_ints_init()
11530 if (tg3_flag(tp, SUPPORT_MSIX) && tg3_enable_msix(tp)) in tg3_ints_init()
11531 tg3_flag_set(tp, USING_MSIX); in tg3_ints_init()
11532 else if (tg3_flag(tp, SUPPORT_MSI) && pci_enable_msi(tp->pdev) == 0) in tg3_ints_init()
11533 tg3_flag_set(tp, USING_MSI); in tg3_ints_init()
11535 if (tg3_flag(tp, USING_MSI) || tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
11537 if (tg3_flag(tp, USING_MSIX) && tp->irq_cnt > 1) in tg3_ints_init()
11539 if (!tg3_flag(tp, 1SHOT_MSI)) in tg3_ints_init()
11544 if (!tg3_flag(tp, USING_MSIX)) { in tg3_ints_init()
11545 tp->irq_cnt = 1; in tg3_ints_init()
11546 tp->napi[0].irq_vec = tp->pdev->irq; in tg3_ints_init()
11549 if (tp->irq_cnt == 1) { in tg3_ints_init()
11550 tp->txq_cnt = 1; in tg3_ints_init()
11551 tp->rxq_cnt = 1; in tg3_ints_init()
11552 netif_set_real_num_tx_queues(tp->dev, 1); in tg3_ints_init()
11553 netif_set_real_num_rx_queues(tp->dev, 1); in tg3_ints_init()
11557 static void tg3_ints_fini(struct tg3 *tp) in tg3_ints_fini() argument
11559 if (tg3_flag(tp, USING_MSIX)) in tg3_ints_fini()
11560 pci_disable_msix(tp->pdev); in tg3_ints_fini()
11561 else if (tg3_flag(tp, USING_MSI)) in tg3_ints_fini()
11562 pci_disable_msi(tp->pdev); in tg3_ints_fini()
11563 tg3_flag_clear(tp, USING_MSI); in tg3_ints_fini()
11564 tg3_flag_clear(tp, USING_MSIX); in tg3_ints_fini()
11565 tg3_flag_clear(tp, ENABLE_RSS); in tg3_ints_fini()
11566 tg3_flag_clear(tp, ENABLE_TSS); in tg3_ints_fini()
11569 static int tg3_start(struct tg3 *tp, bool reset_phy, bool test_irq, in tg3_start() argument
11572 struct net_device *dev = tp->dev; in tg3_start()
11579 tg3_ints_init(tp); in tg3_start()
11581 tg3_rss_check_indir_tbl(tp); in tg3_start()
11586 err = tg3_alloc_consistent(tp); in tg3_start()
11590 tg3_napi_init(tp); in tg3_start()
11592 tg3_napi_enable(tp); in tg3_start()
11594 for (i = 0; i < tp->irq_cnt; i++) { in tg3_start()
11595 err = tg3_request_irq(tp, i); in tg3_start()
11597 for (i--; i >= 0; i--) { in tg3_start()
11598 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11600 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11606 tg3_full_lock(tp, 0); in tg3_start()
11609 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_start()
11611 err = tg3_init_hw(tp, reset_phy); in tg3_start()
11613 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_start()
11614 tg3_free_rings(tp); in tg3_start()
11617 tg3_full_unlock(tp); in tg3_start()
11622 if (test_irq && tg3_flag(tp, USING_MSI)) { in tg3_start()
11623 err = tg3_test_msi(tp); in tg3_start()
11626 tg3_full_lock(tp, 0); in tg3_start()
11627 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_start()
11628 tg3_free_rings(tp); in tg3_start()
11629 tg3_full_unlock(tp); in tg3_start()
11634 if (!tg3_flag(tp, 57765_PLUS) && tg3_flag(tp, USING_MSI)) { in tg3_start()
11642 tg3_phy_start(tp); in tg3_start()
11644 tg3_hwmon_open(tp); in tg3_start()
11646 tg3_full_lock(tp, 0); in tg3_start()
11648 tg3_timer_start(tp); in tg3_start()
11649 tg3_flag_set(tp, INIT_COMPLETE); in tg3_start()
11650 tg3_enable_ints(tp); in tg3_start()
11652 tg3_ptp_resume(tp); in tg3_start()
11654 tg3_full_unlock(tp); in tg3_start()
11662 if (dev->features & NETIF_F_LOOPBACK) in tg3_start()
11663 tg3_set_loopback(dev, dev->features); in tg3_start()
11668 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_start()
11669 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_start()
11670 free_irq(tnapi->irq_vec, tnapi); in tg3_start()
11674 tg3_napi_disable(tp); in tg3_start()
11675 tg3_napi_fini(tp); in tg3_start()
11676 tg3_free_consistent(tp); in tg3_start()
11679 tg3_ints_fini(tp); in tg3_start()
11684 static void tg3_stop(struct tg3 *tp) in tg3_stop() argument
11688 tg3_reset_task_cancel(tp); in tg3_stop()
11689 tg3_netif_stop(tp); in tg3_stop()
11691 tg3_timer_stop(tp); in tg3_stop()
11693 tg3_hwmon_close(tp); in tg3_stop()
11695 tg3_phy_stop(tp); in tg3_stop()
11697 tg3_full_lock(tp, 1); in tg3_stop()
11699 tg3_disable_ints(tp); in tg3_stop()
11701 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_stop()
11702 tg3_free_rings(tp); in tg3_stop()
11703 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_stop()
11705 tg3_full_unlock(tp); in tg3_stop()
11707 for (i = tp->irq_cnt - 1; i >= 0; i--) { in tg3_stop()
11708 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_stop()
11709 free_irq(tnapi->irq_vec, tnapi); in tg3_stop()
11712 tg3_ints_fini(tp); in tg3_stop()
11714 tg3_napi_fini(tp); in tg3_stop()
11716 tg3_free_consistent(tp); in tg3_stop()
11721 struct tg3 *tp = netdev_priv(dev); in tg3_open() local
11724 if (tp->pcierr_recovery) { in tg3_open()
11727 return -EAGAIN; in tg3_open()
11730 if (tp->fw_needed) { in tg3_open()
11731 err = tg3_request_firmware(tp); in tg3_open()
11732 if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_open()
11734 netdev_warn(tp->dev, "EEE capability disabled\n"); in tg3_open()
11735 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_open()
11736 } else if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_open()
11737 netdev_warn(tp->dev, "EEE capability restored\n"); in tg3_open()
11738 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_open()
11740 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) { in tg3_open()
11744 netdev_warn(tp->dev, "TSO capability disabled\n"); in tg3_open()
11745 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_open()
11746 } else if (!tg3_flag(tp, TSO_CAPABLE)) { in tg3_open()
11747 netdev_notice(tp->dev, "TSO capability restored\n"); in tg3_open()
11748 tg3_flag_set(tp, TSO_CAPABLE); in tg3_open()
11752 tg3_carrier_off(tp); in tg3_open()
11754 err = tg3_power_up(tp); in tg3_open()
11758 tg3_full_lock(tp, 0); in tg3_open()
11760 tg3_disable_ints(tp); in tg3_open()
11761 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_open()
11763 tg3_full_unlock(tp); in tg3_open()
11765 err = tg3_start(tp, in tg3_open()
11766 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN), in tg3_open()
11769 tg3_frob_aux_power(tp, false); in tg3_open()
11770 pci_set_power_state(tp->pdev, PCI_D3hot); in tg3_open()
11778 struct tg3 *tp = netdev_priv(dev); in tg3_close() local
11780 if (tp->pcierr_recovery) { in tg3_close()
11783 return -EAGAIN; in tg3_close()
11786 tg3_stop(tp); in tg3_close()
11788 if (pci_device_is_present(tp->pdev)) { in tg3_close()
11789 tg3_power_down_prepare(tp); in tg3_close()
11791 tg3_carrier_off(tp); in tg3_close()
11798 return ((u64)val->high << 32) | ((u64)val->low); in get_stat64()
11801 static u64 tg3_calc_crc_errors(struct tg3 *tp) in tg3_calc_crc_errors() argument
11803 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_calc_crc_errors()
11805 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_calc_crc_errors()
11806 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_calc_crc_errors()
11807 tg3_asic_rev(tp) == ASIC_REV_5701)) { in tg3_calc_crc_errors()
11810 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) { in tg3_calc_crc_errors()
11811 tg3_writephy(tp, MII_TG3_TEST1, in tg3_calc_crc_errors()
11813 tg3_readphy(tp, MII_TG3_RXR_COUNTERS, &val); in tg3_calc_crc_errors()
11817 tp->phy_crc_errors += val; in tg3_calc_crc_errors()
11819 return tp->phy_crc_errors; in tg3_calc_crc_errors()
11822 return get_stat64(&hw_stats->rx_fcs_errors); in tg3_calc_crc_errors()
11826 estats->member = old_estats->member + \
11827 get_stat64(&hw_stats->member)
11829 static void tg3_get_estats(struct tg3 *tp, struct tg3_ethtool_stats *estats) in tg3_get_estats() argument
11831 struct tg3_ethtool_stats *old_estats = &tp->estats_prev; in tg3_get_estats()
11832 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_estats()
11913 static void tg3_get_nstats(struct tg3 *tp, struct rtnl_link_stats64 *stats) in tg3_get_nstats() argument
11915 struct rtnl_link_stats64 *old_stats = &tp->net_stats_prev; in tg3_get_nstats()
11916 struct tg3_hw_stats *hw_stats = tp->hw_stats; in tg3_get_nstats()
11921 stats->rx_packets = old_stats->rx_packets + in tg3_get_nstats()
11922 get_stat64(&hw_stats->rx_ucast_packets) + in tg3_get_nstats()
11923 get_stat64(&hw_stats->rx_mcast_packets) + in tg3_get_nstats()
11924 get_stat64(&hw_stats->rx_bcast_packets); in tg3_get_nstats()
11926 stats->tx_packets = old_stats->tx_packets + in tg3_get_nstats()
11927 get_stat64(&hw_stats->tx_ucast_packets) + in tg3_get_nstats()
11928 get_stat64(&hw_stats->tx_mcast_packets) + in tg3_get_nstats()
11929 get_stat64(&hw_stats->tx_bcast_packets); in tg3_get_nstats()
11931 stats->rx_bytes = old_stats->rx_bytes + in tg3_get_nstats()
11932 get_stat64(&hw_stats->rx_octets); in tg3_get_nstats()
11933 stats->tx_bytes = old_stats->tx_bytes + in tg3_get_nstats()
11934 get_stat64(&hw_stats->tx_octets); in tg3_get_nstats()
11936 stats->rx_errors = old_stats->rx_errors + in tg3_get_nstats()
11937 get_stat64(&hw_stats->rx_errors); in tg3_get_nstats()
11938 stats->tx_errors = old_stats->tx_errors + in tg3_get_nstats()
11939 get_stat64(&hw_stats->tx_errors) + in tg3_get_nstats()
11940 get_stat64(&hw_stats->tx_mac_errors) + in tg3_get_nstats()
11941 get_stat64(&hw_stats->tx_carrier_sense_errors) + in tg3_get_nstats()
11942 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
11944 stats->multicast = old_stats->multicast + in tg3_get_nstats()
11945 get_stat64(&hw_stats->rx_mcast_packets); in tg3_get_nstats()
11946 stats->collisions = old_stats->collisions + in tg3_get_nstats()
11947 get_stat64(&hw_stats->tx_collisions); in tg3_get_nstats()
11949 stats->rx_length_errors = old_stats->rx_length_errors + in tg3_get_nstats()
11950 get_stat64(&hw_stats->rx_frame_too_long_errors) + in tg3_get_nstats()
11951 get_stat64(&hw_stats->rx_undersize_packets); in tg3_get_nstats()
11953 stats->rx_frame_errors = old_stats->rx_frame_errors + in tg3_get_nstats()
11954 get_stat64(&hw_stats->rx_align_errors); in tg3_get_nstats()
11955 stats->tx_aborted_errors = old_stats->tx_aborted_errors + in tg3_get_nstats()
11956 get_stat64(&hw_stats->tx_discards); in tg3_get_nstats()
11957 stats->tx_carrier_errors = old_stats->tx_carrier_errors + in tg3_get_nstats()
11958 get_stat64(&hw_stats->tx_carrier_sense_errors); in tg3_get_nstats()
11960 stats->rx_crc_errors = old_stats->rx_crc_errors + in tg3_get_nstats()
11961 tg3_calc_crc_errors(tp); in tg3_get_nstats()
11963 stats->rx_missed_errors = old_stats->rx_missed_errors + in tg3_get_nstats()
11964 get_stat64(&hw_stats->rx_discards); in tg3_get_nstats()
11966 /* Aggregate per-queue counters. The per-queue counters are updated in tg3_get_nstats()
11967 * by a single writer, race-free. The result computed by this loop in tg3_get_nstats()
11974 rx_dropped = (unsigned long)(old_stats->rx_dropped); in tg3_get_nstats()
11975 tx_dropped = (unsigned long)(old_stats->tx_dropped); in tg3_get_nstats()
11977 for (i = 0; i < tp->irq_cnt; i++) { in tg3_get_nstats()
11978 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_get_nstats()
11980 rx_dropped += tnapi->rx_dropped; in tg3_get_nstats()
11981 tx_dropped += tnapi->tx_dropped; in tg3_get_nstats()
11984 stats->rx_dropped = rx_dropped; in tg3_get_nstats()
11985 stats->tx_dropped = tx_dropped; in tg3_get_nstats()
11996 struct tg3 *tp = netdev_priv(dev); in tg3_get_regs() local
11998 regs->version = 0; in tg3_get_regs()
12002 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_get_regs()
12005 tg3_full_lock(tp, 0); in tg3_get_regs()
12007 tg3_dump_legacy_regs(tp, (u32 *)_p); in tg3_get_regs()
12009 tg3_full_unlock(tp); in tg3_get_regs()
12014 struct tg3 *tp = netdev_priv(dev); in tg3_get_eeprom_len() local
12016 return tp->nvram_size; in tg3_get_eeprom_len()
12021 struct tg3 *tp = netdev_priv(dev); in tg3_get_eeprom() local
12027 if (tg3_flag(tp, NO_NVRAM)) in tg3_get_eeprom()
12028 return -EINVAL; in tg3_get_eeprom()
12030 offset = eeprom->offset; in tg3_get_eeprom()
12031 len = eeprom->len; in tg3_get_eeprom()
12032 eeprom->len = 0; in tg3_get_eeprom()
12034 eeprom->magic = TG3_EEPROM_MAGIC; in tg3_get_eeprom()
12036 /* Override clock, link aware and link idle modes */ in tg3_get_eeprom()
12037 if (tg3_flag(tp, CPMU_PRESENT)) { in tg3_get_eeprom()
12047 tg3_override_clk(tp); in tg3_get_eeprom()
12052 b_count = 4 - b_offset; in tg3_get_eeprom()
12057 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val); in tg3_get_eeprom()
12061 len -= b_count; in tg3_get_eeprom()
12063 eeprom->len += b_count; in tg3_get_eeprom()
12067 pd = &data[eeprom->len]; in tg3_get_eeprom()
12068 for (i = 0; i < (len - (len & 3)); i += 4) { in tg3_get_eeprom()
12069 ret = tg3_nvram_read_be32(tp, offset + i, &val); in tg3_get_eeprom()
12072 i -= 4; in tg3_get_eeprom()
12073 eeprom->len += i; in tg3_get_eeprom()
12079 eeprom->len += i; in tg3_get_eeprom()
12080 ret = -EINTR; in tg3_get_eeprom()
12086 eeprom->len += i; in tg3_get_eeprom()
12090 pd = &data[eeprom->len]; in tg3_get_eeprom()
12092 b_offset = offset + len - b_count; in tg3_get_eeprom()
12093 ret = tg3_nvram_read_be32(tp, b_offset, &val); in tg3_get_eeprom()
12097 eeprom->len += b_count; in tg3_get_eeprom()
12102 /* Restore clock, link aware and link idle modes */ in tg3_get_eeprom()
12103 tg3_restore_clk(tp); in tg3_get_eeprom()
12112 struct tg3 *tp = netdev_priv(dev); in tg3_set_eeprom() local
12118 if (tg3_flag(tp, NO_NVRAM) || in tg3_set_eeprom()
12119 eeprom->magic != TG3_EEPROM_MAGIC) in tg3_set_eeprom()
12120 return -EINVAL; in tg3_set_eeprom()
12122 offset = eeprom->offset; in tg3_set_eeprom()
12123 len = eeprom->len; in tg3_set_eeprom()
12127 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start); in tg3_set_eeprom()
12141 ret = tg3_nvram_read_be32(tp, offset+len-4, &end); in tg3_set_eeprom()
12150 return -ENOMEM; in tg3_set_eeprom()
12154 memcpy(buf+len-4, &end, 4); in tg3_set_eeprom()
12155 memcpy(buf + b_offset, data, eeprom->len); in tg3_set_eeprom()
12158 ret = tg3_nvram_write_block(tp, offset, len, buf); in tg3_set_eeprom()
12169 struct tg3 *tp = netdev_priv(dev); in tg3_get_link_ksettings() local
12172 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_get_link_ksettings()
12174 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_get_link_ksettings()
12175 return -EAGAIN; in tg3_get_link_ksettings()
12176 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_get_link_ksettings()
12184 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_get_link_ksettings()
12188 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12194 cmd->base.port = PORT_TP; in tg3_get_link_ksettings()
12197 cmd->base.port = PORT_FIBRE; in tg3_get_link_ksettings()
12199 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, in tg3_get_link_ksettings()
12202 advertising = tp->link_config.advertising; in tg3_get_link_ksettings()
12203 if (tg3_flag(tp, PAUSE_AUTONEG)) { in tg3_get_link_ksettings()
12204 if (tp->link_config.flowctrl & FLOW_CTRL_RX) { in tg3_get_link_ksettings()
12205 if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12211 } else if (tp->link_config.flowctrl & FLOW_CTRL_TX) { in tg3_get_link_ksettings()
12215 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, in tg3_get_link_ksettings()
12218 if (netif_running(dev) && tp->link_up) { in tg3_get_link_ksettings()
12219 cmd->base.speed = tp->link_config.active_speed; in tg3_get_link_ksettings()
12220 cmd->base.duplex = tp->link_config.active_duplex; in tg3_get_link_ksettings()
12222 cmd->link_modes.lp_advertising, in tg3_get_link_ksettings()
12223 tp->link_config.rmt_adv); in tg3_get_link_ksettings()
12225 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) { in tg3_get_link_ksettings()
12226 if (tp->phy_flags & TG3_PHYFLG_MDIX_STATE) in tg3_get_link_ksettings()
12227 cmd->base.eth_tp_mdix = ETH_TP_MDI_X; in tg3_get_link_ksettings()
12229 cmd->base.eth_tp_mdix = ETH_TP_MDI; in tg3_get_link_ksettings()
12232 cmd->base.speed = SPEED_UNKNOWN; in tg3_get_link_ksettings()
12233 cmd->base.duplex = DUPLEX_UNKNOWN; in tg3_get_link_ksettings()
12234 cmd->base.eth_tp_mdix = ETH_TP_MDI_INVALID; in tg3_get_link_ksettings()
12236 cmd->base.phy_address = tp->phy_addr; in tg3_get_link_ksettings()
12237 cmd->base.autoneg = tp->link_config.autoneg; in tg3_get_link_ksettings()
12244 struct tg3 *tp = netdev_priv(dev); in tg3_set_link_ksettings() local
12245 u32 speed = cmd->base.speed; in tg3_set_link_ksettings()
12248 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_link_ksettings()
12250 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_set_link_ksettings()
12251 return -EAGAIN; in tg3_set_link_ksettings()
12252 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_link_ksettings()
12256 if (cmd->base.autoneg != AUTONEG_ENABLE && in tg3_set_link_ksettings()
12257 cmd->base.autoneg != AUTONEG_DISABLE) in tg3_set_link_ksettings()
12258 return -EINVAL; in tg3_set_link_ksettings()
12260 if (cmd->base.autoneg == AUTONEG_DISABLE && in tg3_set_link_ksettings()
12261 cmd->base.duplex != DUPLEX_FULL && in tg3_set_link_ksettings()
12262 cmd->base.duplex != DUPLEX_HALF) in tg3_set_link_ksettings()
12263 return -EINVAL; in tg3_set_link_ksettings()
12266 cmd->link_modes.advertising); in tg3_set_link_ksettings()
12268 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12273 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_set_link_ksettings()
12277 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_set_link_ksettings()
12287 return -EINVAL; in tg3_set_link_ksettings()
12298 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) { in tg3_set_link_ksettings()
12300 return -EINVAL; in tg3_set_link_ksettings()
12302 if (cmd->base.duplex != DUPLEX_FULL) in tg3_set_link_ksettings()
12303 return -EINVAL; in tg3_set_link_ksettings()
12307 return -EINVAL; in tg3_set_link_ksettings()
12311 tg3_full_lock(tp, 0); in tg3_set_link_ksettings()
12313 tp->link_config.autoneg = cmd->base.autoneg; in tg3_set_link_ksettings()
12314 if (cmd->base.autoneg == AUTONEG_ENABLE) { in tg3_set_link_ksettings()
12315 tp->link_config.advertising = (advertising | in tg3_set_link_ksettings()
12317 tp->link_config.speed = SPEED_UNKNOWN; in tg3_set_link_ksettings()
12318 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_set_link_ksettings()
12320 tp->link_config.advertising = 0; in tg3_set_link_ksettings()
12321 tp->link_config.speed = speed; in tg3_set_link_ksettings()
12322 tp->link_config.duplex = cmd->base.duplex; in tg3_set_link_ksettings()
12325 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_link_ksettings()
12327 tg3_warn_mgmt_link_flap(tp); in tg3_set_link_ksettings()
12330 tg3_setup_phy(tp, true); in tg3_set_link_ksettings()
12332 tg3_full_unlock(tp); in tg3_set_link_ksettings()
12339 struct tg3 *tp = netdev_priv(dev); in tg3_get_drvinfo() local
12341 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); in tg3_get_drvinfo()
12342 strscpy(info->fw_version, tp->fw_ver, sizeof(info->fw_version)); in tg3_get_drvinfo()
12343 strscpy(info->bus_info, pci_name(tp->pdev), sizeof(info->bus_info)); in tg3_get_drvinfo()
12348 struct tg3 *tp = netdev_priv(dev); in tg3_get_wol() local
12350 if (tg3_flag(tp, WOL_CAP) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12351 wol->supported = WAKE_MAGIC; in tg3_get_wol()
12353 wol->supported = 0; in tg3_get_wol()
12354 wol->wolopts = 0; in tg3_get_wol()
12355 if (tg3_flag(tp, WOL_ENABLE) && device_can_wakeup(&tp->pdev->dev)) in tg3_get_wol()
12356 wol->wolopts = WAKE_MAGIC; in tg3_get_wol()
12357 memset(&wol->sopass, 0, sizeof(wol->sopass)); in tg3_get_wol()
12362 struct tg3 *tp = netdev_priv(dev); in tg3_set_wol() local
12363 struct device *dp = &tp->pdev->dev; in tg3_set_wol()
12365 if (wol->wolopts & ~WAKE_MAGIC) in tg3_set_wol()
12366 return -EINVAL; in tg3_set_wol()
12367 if ((wol->wolopts & WAKE_MAGIC) && in tg3_set_wol()
12368 !(tg3_flag(tp, WOL_CAP) && device_can_wakeup(dp))) in tg3_set_wol()
12369 return -EINVAL; in tg3_set_wol()
12371 device_set_wakeup_enable(dp, wol->wolopts & WAKE_MAGIC); in tg3_set_wol()
12374 tg3_flag_set(tp, WOL_ENABLE); in tg3_set_wol()
12376 tg3_flag_clear(tp, WOL_ENABLE); in tg3_set_wol()
12383 struct tg3 *tp = netdev_priv(dev); in tg3_get_msglevel() local
12384 return tp->msg_enable; in tg3_get_msglevel()
12389 struct tg3 *tp = netdev_priv(dev); in tg3_set_msglevel() local
12390 tp->msg_enable = value; in tg3_set_msglevel()
12395 struct tg3 *tp = netdev_priv(dev); in tg3_nway_reset() local
12399 return -EAGAIN; in tg3_nway_reset()
12401 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_nway_reset()
12402 return -EINVAL; in tg3_nway_reset()
12404 tg3_warn_mgmt_link_flap(tp); in tg3_nway_reset()
12406 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_nway_reset()
12407 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_nway_reset()
12408 return -EAGAIN; in tg3_nway_reset()
12409 r = phy_start_aneg(mdiobus_get_phy(tp->mdio_bus, tp->phy_addr)); in tg3_nway_reset()
12413 spin_lock_bh(&tp->lock); in tg3_nway_reset()
12414 r = -EINVAL; in tg3_nway_reset()
12415 tg3_readphy(tp, MII_BMCR, &bmcr); in tg3_nway_reset()
12416 if (!tg3_readphy(tp, MII_BMCR, &bmcr) && in tg3_nway_reset()
12418 (tp->phy_flags & TG3_PHYFLG_PARALLEL_DETECT))) { in tg3_nway_reset()
12419 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART | in tg3_nway_reset()
12423 spin_unlock_bh(&tp->lock); in tg3_nway_reset()
12434 struct tg3 *tp = netdev_priv(dev); in tg3_get_ringparam() local
12436 ering->rx_max_pending = tp->rx_std_ring_mask; in tg3_get_ringparam()
12437 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
12438 ering->rx_jumbo_max_pending = tp->rx_jmb_ring_mask; in tg3_get_ringparam()
12440 ering->rx_jumbo_max_pending = 0; in tg3_get_ringparam()
12442 ering->tx_max_pending = TG3_TX_RING_SIZE - 1; in tg3_get_ringparam()
12444 ering->rx_pending = tp->rx_pending; in tg3_get_ringparam()
12445 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_get_ringparam()
12446 ering->rx_jumbo_pending = tp->rx_jumbo_pending; in tg3_get_ringparam()
12448 ering->rx_jumbo_pending = 0; in tg3_get_ringparam()
12450 ering->tx_pending = tp->napi[0].tx_pending; in tg3_get_ringparam()
12458 struct tg3 *tp = netdev_priv(dev); in tg3_set_ringparam() local
12462 if ((ering->rx_pending > tp->rx_std_ring_mask) || in tg3_set_ringparam()
12463 (ering->rx_jumbo_pending > tp->rx_jmb_ring_mask) || in tg3_set_ringparam()
12464 (ering->tx_pending > TG3_TX_RING_SIZE - 1) || in tg3_set_ringparam()
12465 (ering->tx_pending <= MAX_SKB_FRAGS) || in tg3_set_ringparam()
12466 (tg3_flag(tp, TSO_BUG) && in tg3_set_ringparam()
12467 (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) in tg3_set_ringparam()
12468 return -EINVAL; in tg3_set_ringparam()
12471 tg3_phy_stop(tp); in tg3_set_ringparam()
12472 tg3_netif_stop(tp); in tg3_set_ringparam()
12476 tg3_full_lock(tp, irq_sync); in tg3_set_ringparam()
12478 tp->rx_pending = ering->rx_pending; in tg3_set_ringparam()
12480 if (tg3_flag(tp, MAX_RXPEND_64) && in tg3_set_ringparam()
12481 tp->rx_pending > 63) in tg3_set_ringparam()
12482 tp->rx_pending = 63; in tg3_set_ringparam()
12484 if (tg3_flag(tp, JUMBO_RING_ENABLE)) in tg3_set_ringparam()
12485 tp->rx_jumbo_pending = ering->rx_jumbo_pending; in tg3_set_ringparam()
12487 for (i = 0; i < tp->irq_max; i++) in tg3_set_ringparam()
12488 tp->napi[i].tx_pending = ering->tx_pending; in tg3_set_ringparam()
12491 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_set_ringparam()
12493 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_ringparam()
12494 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_set_ringparam()
12495 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_set_ringparam()
12498 err = tg3_restart_hw(tp, reset_phy); in tg3_set_ringparam()
12500 tg3_netif_start(tp); in tg3_set_ringparam()
12503 tg3_full_unlock(tp); in tg3_set_ringparam()
12506 tg3_phy_start(tp); in tg3_set_ringparam()
12513 struct tg3 *tp = netdev_priv(dev); in tg3_get_pauseparam() local
12515 epause->autoneg = !!tg3_flag(tp, PAUSE_AUTONEG); in tg3_get_pauseparam()
12517 if (tp->link_config.flowctrl & FLOW_CTRL_RX) in tg3_get_pauseparam()
12518 epause->rx_pause = 1; in tg3_get_pauseparam()
12520 epause->rx_pause = 0; in tg3_get_pauseparam()
12522 if (tp->link_config.flowctrl & FLOW_CTRL_TX) in tg3_get_pauseparam()
12523 epause->tx_pause = 1; in tg3_get_pauseparam()
12525 epause->tx_pause = 0; in tg3_get_pauseparam()
12530 struct tg3 *tp = netdev_priv(dev); in tg3_set_pauseparam() local
12534 if (tp->link_config.autoneg == AUTONEG_ENABLE) in tg3_set_pauseparam()
12535 tg3_warn_mgmt_link_flap(tp); in tg3_set_pauseparam()
12537 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_set_pauseparam()
12540 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_set_pauseparam()
12543 return -EINVAL; in tg3_set_pauseparam()
12545 tp->link_config.flowctrl = 0; in tg3_set_pauseparam()
12546 phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause); in tg3_set_pauseparam()
12547 if (epause->rx_pause) { in tg3_set_pauseparam()
12548 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12550 if (epause->tx_pause) { in tg3_set_pauseparam()
12551 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12553 } else if (epause->tx_pause) { in tg3_set_pauseparam()
12554 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12557 if (epause->autoneg) in tg3_set_pauseparam()
12558 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12560 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12562 if (tp->phy_flags & TG3_PHYFLG_IS_CONNECTED) { in tg3_set_pauseparam()
12563 if (phydev->autoneg) { in tg3_set_pauseparam()
12565 * renegotiate the link to inform our in tg3_set_pauseparam()
12566 * link partner of our flow control in tg3_set_pauseparam()
12574 if (!epause->autoneg) in tg3_set_pauseparam()
12575 tg3_setup_flow_control(tp, 0, 0); in tg3_set_pauseparam()
12581 tg3_netif_stop(tp); in tg3_set_pauseparam()
12585 tg3_full_lock(tp, irq_sync); in tg3_set_pauseparam()
12587 if (epause->autoneg) in tg3_set_pauseparam()
12588 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12590 tg3_flag_clear(tp, PAUSE_AUTONEG); in tg3_set_pauseparam()
12591 if (epause->rx_pause) in tg3_set_pauseparam()
12592 tp->link_config.flowctrl |= FLOW_CTRL_RX; in tg3_set_pauseparam()
12594 tp->link_config.flowctrl &= ~FLOW_CTRL_RX; in tg3_set_pauseparam()
12595 if (epause->tx_pause) in tg3_set_pauseparam()
12596 tp->link_config.flowctrl |= FLOW_CTRL_TX; in tg3_set_pauseparam()
12598 tp->link_config.flowctrl &= ~FLOW_CTRL_TX; in tg3_set_pauseparam()
12601 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_set_pauseparam()
12603 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_set_pauseparam()
12604 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_set_pauseparam()
12605 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_set_pauseparam()
12608 err = tg3_restart_hw(tp, reset_phy); in tg3_set_pauseparam()
12610 tg3_netif_start(tp); in tg3_set_pauseparam()
12613 tg3_full_unlock(tp); in tg3_set_pauseparam()
12616 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_pauseparam()
12629 return -EOPNOTSUPP; in tg3_get_sset_count()
12636 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxnfc() local
12638 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxnfc()
12639 return -EOPNOTSUPP; in tg3_get_rxnfc()
12641 switch (info->cmd) { in tg3_get_rxnfc()
12643 if (netif_running(tp->dev)) in tg3_get_rxnfc()
12644 info->data = tp->rxq_cnt; in tg3_get_rxnfc()
12646 info->data = num_online_cpus(); in tg3_get_rxnfc()
12647 if (info->data > TG3_RSS_MAX_NUM_QS) in tg3_get_rxnfc()
12648 info->data = TG3_RSS_MAX_NUM_QS; in tg3_get_rxnfc()
12654 return -EOPNOTSUPP; in tg3_get_rxnfc()
12661 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxfh_indir_size() local
12663 if (tg3_flag(tp, SUPPORT_MSIX)) in tg3_get_rxfh_indir_size()
12671 struct tg3 *tp = netdev_priv(dev); in tg3_get_rxfh() local
12680 indir[i] = tp->rss_ind_tbl[i]; in tg3_get_rxfh()
12688 struct tg3 *tp = netdev_priv(dev); in tg3_set_rxfh() local
12696 return -EOPNOTSUPP; in tg3_set_rxfh()
12702 tp->rss_ind_tbl[i] = indir[i]; in tg3_set_rxfh()
12704 if (!netif_running(dev) || !tg3_flag(tp, ENABLE_RSS)) in tg3_set_rxfh()
12710 tg3_full_lock(tp, 0); in tg3_set_rxfh()
12711 tg3_rss_write_indir_tbl(tp); in tg3_set_rxfh()
12712 tg3_full_unlock(tp); in tg3_set_rxfh()
12720 struct tg3 *tp = netdev_priv(dev); in tg3_get_channels() local
12723 channel->max_rx = tp->rxq_max; in tg3_get_channels()
12724 channel->max_tx = tp->txq_max; in tg3_get_channels()
12727 channel->rx_count = tp->rxq_cnt; in tg3_get_channels()
12728 channel->tx_count = tp->txq_cnt; in tg3_get_channels()
12730 if (tp->rxq_req) in tg3_get_channels()
12731 channel->rx_count = tp->rxq_req; in tg3_get_channels()
12733 channel->rx_count = min(deflt_qs, tp->rxq_max); in tg3_get_channels()
12735 if (tp->txq_req) in tg3_get_channels()
12736 channel->tx_count = tp->txq_req; in tg3_get_channels()
12738 channel->tx_count = min(deflt_qs, tp->txq_max); in tg3_get_channels()
12745 struct tg3 *tp = netdev_priv(dev); in tg3_set_channels() local
12747 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_set_channels()
12748 return -EOPNOTSUPP; in tg3_set_channels()
12750 if (channel->rx_count > tp->rxq_max || in tg3_set_channels()
12751 channel->tx_count > tp->txq_max) in tg3_set_channels()
12752 return -EINVAL; in tg3_set_channels()
12754 tp->rxq_req = channel->rx_count; in tg3_set_channels()
12755 tp->txq_req = channel->tx_count; in tg3_set_channels()
12760 tg3_stop(tp); in tg3_set_channels()
12762 tg3_carrier_off(tp); in tg3_set_channels()
12764 tg3_start(tp, true, false, false); in tg3_set_channels()
12787 struct tg3 *tp = netdev_priv(dev); in tg3_set_phys_id() local
12809 tw32(MAC_LED_CTRL, tp->led_ctrl); in tg3_set_phys_id()
12819 struct tg3 *tp = netdev_priv(dev); in tg3_get_ethtool_stats() local
12821 if (tp->hw_stats) in tg3_get_ethtool_stats()
12822 tg3_get_estats(tp, (struct tg3_ethtool_stats *)tmp_stats); in tg3_get_ethtool_stats()
12827 static __be32 *tg3_vpd_readblock(struct tg3 *tp, unsigned int *vpdlen) in tg3_vpd_readblock() argument
12834 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &magic)) in tg3_vpd_readblock()
12841 if (tg3_nvram_read(tp, offset, &val)) in tg3_vpd_readblock()
12851 if (tg3_nvram_read(tp, offset + 4, &offset)) in tg3_vpd_readblock()
12854 offset = tg3_nvram_logical_addr(tp, offset); in tg3_vpd_readblock()
12867 /* The data is in little-endian format in NVRAM. in tg3_vpd_readblock()
12868 * Use the big-endian read routines to preserve in tg3_vpd_readblock()
12871 if (tg3_nvram_read_be32(tp, offset + i, &buf[i/4])) in tg3_vpd_readblock()
12876 buf = pci_vpd_alloc(tp->pdev, vpdlen); in tg3_vpd_readblock()
12898 static int tg3_test_nvram(struct tg3 *tp) in tg3_test_nvram() argument
12905 if (tg3_flag(tp, NO_NVRAM)) in tg3_test_nvram()
12908 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_test_nvram()
12909 return -EIO; in tg3_test_nvram()
12936 return -EIO; in tg3_test_nvram()
12943 return -EIO; in tg3_test_nvram()
12947 return -ENOMEM; in tg3_test_nvram()
12949 err = -EIO; in tg3_test_nvram()
12951 err = tg3_nvram_read_be32(tp, i, &buf[j]); in tg3_test_nvram()
12981 err = -EIO; in tg3_test_nvram()
13015 err = -EIO; in tg3_test_nvram()
13028 err = -EIO; in tg3_test_nvram()
13042 buf = tg3_vpd_readblock(tp, &len); in tg3_test_nvram()
13044 return -ENOMEM; in tg3_test_nvram()
13058 static int tg3_test_link(struct tg3 *tp) in tg3_test_link() argument
13062 if (!netif_running(tp->dev)) in tg3_test_link()
13063 return -ENODEV; in tg3_test_link()
13065 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_test_link()
13071 if (tp->link_up) in tg3_test_link()
13078 return -EIO; in tg3_test_link()
13082 static int tg3_test_registers(struct tg3 *tp) in tg3_test_registers() argument
13232 if (tg3_flag(tp, 5705_PLUS)) { in tg3_test_registers()
13234 if (tg3_flag(tp, 5750_PLUS)) in tg3_test_registers()
13245 if (tg3_flag(tp, IS_5788) && in tg3_test_registers()
13259 /* Determine the read-only value. */ in tg3_test_registers()
13262 /* Write zero to the register, then make sure the read-only bits in tg3_test_registers()
13269 /* Test the read-only and read/write bits. */ in tg3_test_registers()
13274 * make sure the read-only bits are not changed and the in tg3_test_registers()
13281 /* Test the read-only bits. */ in tg3_test_registers()
13295 if (netif_msg_hw(tp)) in tg3_test_registers()
13296 netdev_err(tp->dev, in tg3_test_registers()
13299 return -EIO; in tg3_test_registers()
13302 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len) in tg3_do_mem_test() argument
13312 tg3_write_mem(tp, offset + j, test_pattern[i]); in tg3_do_mem_test()
13313 tg3_read_mem(tp, offset + j, &val); in tg3_do_mem_test()
13315 return -EIO; in tg3_do_mem_test()
13321 static int tg3_test_memory(struct tg3 *tp) in tg3_test_memory() argument
13368 if (tg3_flag(tp, 5717_PLUS)) in tg3_test_memory()
13370 else if (tg3_flag(tp, 57765_CLASS) || in tg3_test_memory()
13371 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_test_memory()
13373 else if (tg3_flag(tp, 5755_PLUS)) in tg3_test_memory()
13375 else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_test_memory()
13377 else if (tg3_flag(tp, 5705_PLUS)) in tg3_test_memory()
13383 err = tg3_do_mem_test(tp, mem_tbl[i].offset, mem_tbl[i].len); in tg3_test_memory()
13414 static int tg3_run_loopback(struct tg3 *tp, u32 pktsz, bool tso_loopback) in tg3_run_loopback() argument
13425 struct tg3_rx_prodring_set *tpr = &tp->napi[0].prodring; in tg3_run_loopback()
13427 tnapi = &tp->napi[0]; in tg3_run_loopback()
13428 rnapi = &tp->napi[0]; in tg3_run_loopback()
13429 if (tp->irq_cnt > 1) { in tg3_run_loopback()
13430 if (tg3_flag(tp, ENABLE_RSS)) in tg3_run_loopback()
13431 rnapi = &tp->napi[1]; in tg3_run_loopback()
13432 if (tg3_flag(tp, ENABLE_TSS)) in tg3_run_loopback()
13433 tnapi = &tp->napi[1]; in tg3_run_loopback()
13435 coal_now = tnapi->coal_now | rnapi->coal_now; in tg3_run_loopback()
13437 err = -EIO; in tg3_run_loopback()
13440 skb = netdev_alloc_skb(tp->dev, tx_len); in tg3_run_loopback()
13442 return -ENOMEM; in tg3_run_loopback()
13445 memcpy(tx_data, tp->dev->dev_addr, ETH_ALEN); in tg3_run_loopback()
13460 val = tx_len - ETH_ALEN * 2 - sizeof(tg3_tso_header); in tg3_run_loopback()
13464 iph->tot_len = htons((u16)(mss + hdr_len)); in tg3_run_loopback()
13469 if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
13470 tg3_flag(tp, HW_TSO_2) || in tg3_run_loopback()
13471 tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
13475 th->check = 0; in tg3_run_loopback()
13479 if (tg3_flag(tp, HW_TSO_3)) { in tg3_run_loopback()
13484 } else if (tg3_flag(tp, HW_TSO_2)) in tg3_run_loopback()
13486 else if (tg3_flag(tp, HW_TSO_1) || in tg3_run_loopback()
13487 tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_run_loopback()
13498 if (tg3_flag(tp, USE_JUMBO_BDFLAG) && in tg3_run_loopback()
13506 map = dma_map_single(&tp->pdev->dev, skb->data, tx_len, DMA_TO_DEVICE); in tg3_run_loopback()
13507 if (dma_mapping_error(&tp->pdev->dev, map)) { in tg3_run_loopback()
13509 return -EIO; in tg3_run_loopback()
13512 val = tnapi->tx_prod; in tg3_run_loopback()
13513 tnapi->tx_buffers[val].skb = skb; in tg3_run_loopback()
13514 dma_unmap_addr_set(&tnapi->tx_buffers[val], mapping, map); in tg3_run_loopback()
13516 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13517 rnapi->coal_now); in tg3_run_loopback()
13521 rx_start_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13526 tnapi->tx_buffers[val].skb = NULL; in tg3_run_loopback()
13528 return -EIO; in tg3_run_loopback()
13531 tnapi->tx_prod++; in tg3_run_loopback()
13536 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod); in tg3_run_loopback()
13537 tr32_mailbox(tnapi->prodmbox); in tg3_run_loopback()
13543 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE | in tg3_run_loopback()
13548 tx_idx = tnapi->hw_status->idx[0].tx_consumer; in tg3_run_loopback()
13549 rx_idx = rnapi->hw_status->idx[0].rx_producer; in tg3_run_loopback()
13550 if ((tx_idx == tnapi->tx_prod) && in tg3_run_loopback()
13555 tg3_tx_skb_unmap(tnapi, tnapi->tx_prod - 1, -1); in tg3_run_loopback()
13558 if (tx_idx != tnapi->tx_prod) in tg3_run_loopback()
13566 desc = &rnapi->rx_rcb[rx_start_idx++]; in tg3_run_loopback()
13567 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK; in tg3_run_loopback()
13568 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK; in tg3_run_loopback()
13570 if ((desc->err_vlan & RXD_ERR_MASK) != 0 && in tg3_run_loopback()
13571 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) in tg3_run_loopback()
13574 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) in tg3_run_loopback()
13575 - ETH_FCS_LEN; in tg3_run_loopback()
13581 if (pktsz <= TG3_RX_STD_DMA_SZ - ETH_FCS_LEN) { in tg3_run_loopback()
13588 } else if ((desc->type_flags & RXD_FLAG_TCPUDP_CSUM) && in tg3_run_loopback()
13589 (desc->ip_tcp_csum & RXD_TCPCSUM_MASK) in tg3_run_loopback()
13595 rx_data = tpr->rx_std_buffers[desc_idx].data; in tg3_run_loopback()
13596 map = dma_unmap_addr(&tpr->rx_std_buffers[desc_idx], in tg3_run_loopback()
13599 rx_data = tpr->rx_jmb_buffers[desc_idx].data; in tg3_run_loopback()
13600 map = dma_unmap_addr(&tpr->rx_jmb_buffers[desc_idx], in tg3_run_loopback()
13605 dma_sync_single_for_cpu(&tp->pdev->dev, map, rx_len, in tg3_run_loopback()
13608 rx_data += TG3_RX_OFFSET(tp); in tg3_run_loopback()
13630 static int tg3_test_loopback(struct tg3 *tp, u64 *data, bool do_extlpbk) in tg3_test_loopback() argument
13632 int err = -EIO; in tg3_test_loopback()
13636 if (tp->dma_limit) in tg3_test_loopback()
13637 jmb_pkt_sz = tp->dma_limit - ETH_HLEN; in tg3_test_loopback()
13639 eee_cap = tp->phy_flags & TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13640 tp->phy_flags &= ~TG3_PHYFLG_EEE_CAP; in tg3_test_loopback()
13642 if (!netif_running(tp->dev)) { in tg3_test_loopback()
13650 err = tg3_reset_hw(tp, true); in tg3_test_loopback()
13659 if (tg3_flag(tp, ENABLE_RSS)) { in tg3_test_loopback()
13668 /* HW errata - mac loopback fails in some cases on 5780. in tg3_test_loopback()
13673 if (tg3_asic_rev(tp) != ASIC_REV_5780 && in tg3_test_loopback()
13674 !tg3_flag(tp, CPMU_PRESENT)) { in tg3_test_loopback()
13675 tg3_mac_loopback(tp, true); in tg3_test_loopback()
13677 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13680 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13681 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13684 tg3_mac_loopback(tp, false); in tg3_test_loopback()
13687 if (!(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && in tg3_test_loopback()
13688 !tg3_flag(tp, USE_PHYLIB)) { in tg3_test_loopback()
13691 tg3_phy_lpbk_set(tp, 0, false); in tg3_test_loopback()
13693 /* Wait for link */ in tg3_test_loopback()
13700 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13702 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
13703 tg3_run_loopback(tp, ETH_FRAME_LEN, true)) in tg3_test_loopback()
13705 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13706 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13710 tg3_phy_lpbk_set(tp, 0, true); in tg3_test_loopback()
13712 /* All link indications report up, but the hardware in tg3_test_loopback()
13718 if (tg3_run_loopback(tp, ETH_FRAME_LEN, false)) in tg3_test_loopback()
13721 if (tg3_flag(tp, TSO_CAPABLE) && in tg3_test_loopback()
13722 tg3_run_loopback(tp, ETH_FRAME_LEN, true)) in tg3_test_loopback()
13725 if (tg3_flag(tp, JUMBO_RING_ENABLE) && in tg3_test_loopback()
13726 tg3_run_loopback(tp, jmb_pkt_sz + ETH_HLEN, false)) in tg3_test_loopback()
13731 /* Re-enable gphy autopowerdown. */ in tg3_test_loopback()
13732 if (tp->phy_flags & TG3_PHYFLG_ENABLE_APD) in tg3_test_loopback()
13733 tg3_phy_toggle_apd(tp, true); in tg3_test_loopback()
13737 data[TG3_EXT_LOOPB_TEST]) ? -EIO : 0; in tg3_test_loopback()
13740 tp->phy_flags |= eee_cap; in tg3_test_loopback()
13748 struct tg3 *tp = netdev_priv(dev); in tg3_self_test() local
13749 bool doextlpbk = etest->flags & ETH_TEST_FL_EXTERNAL_LB; in tg3_self_test()
13751 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) { in tg3_self_test()
13752 if (tg3_power_up(tp)) { in tg3_self_test()
13753 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13757 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_self_test()
13762 if (tg3_test_nvram(tp) != 0) { in tg3_self_test()
13763 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13766 if (!doextlpbk && tg3_test_link(tp)) { in tg3_self_test()
13767 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13770 if (etest->flags & ETH_TEST_FL_OFFLINE) { in tg3_self_test()
13774 tg3_phy_stop(tp); in tg3_self_test()
13775 tg3_netif_stop(tp); in tg3_self_test()
13779 tg3_full_lock(tp, irq_sync); in tg3_self_test()
13780 tg3_halt(tp, RESET_KIND_SUSPEND, 1); in tg3_self_test()
13781 err = tg3_nvram_lock(tp); in tg3_self_test()
13782 tg3_halt_cpu(tp, RX_CPU_BASE); in tg3_self_test()
13783 if (!tg3_flag(tp, 5705_PLUS)) in tg3_self_test()
13784 tg3_halt_cpu(tp, TX_CPU_BASE); in tg3_self_test()
13786 tg3_nvram_unlock(tp); in tg3_self_test()
13788 if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) in tg3_self_test()
13789 tg3_phy_reset(tp); in tg3_self_test()
13791 if (tg3_test_registers(tp) != 0) { in tg3_self_test()
13792 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13796 if (tg3_test_memory(tp) != 0) { in tg3_self_test()
13797 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13802 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE; in tg3_self_test()
13804 if (tg3_test_loopback(tp, data, doextlpbk)) in tg3_self_test()
13805 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13807 tg3_full_unlock(tp); in tg3_self_test()
13809 if (tg3_test_interrupt(tp) != 0) { in tg3_self_test()
13810 etest->flags |= ETH_TEST_FL_FAILED; in tg3_self_test()
13814 tg3_full_lock(tp, 0); in tg3_self_test()
13816 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_self_test()
13818 tg3_flag_set(tp, INIT_COMPLETE); in tg3_self_test()
13819 err2 = tg3_restart_hw(tp, true); in tg3_self_test()
13821 tg3_netif_start(tp); in tg3_self_test()
13824 tg3_full_unlock(tp); in tg3_self_test()
13827 tg3_phy_start(tp); in tg3_self_test()
13829 if (tp->phy_flags & TG3_PHYFLG_IS_LOW_POWER) in tg3_self_test()
13830 tg3_power_down_prepare(tp); in tg3_self_test()
13836 struct tg3 *tp = netdev_priv(dev); in tg3_hwtstamp_set() local
13839 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_hwtstamp_set()
13840 return -EOPNOTSUPP; in tg3_hwtstamp_set()
13842 if (copy_from_user(&stmpconf, ifr->ifr_data, sizeof(stmpconf))) in tg3_hwtstamp_set()
13843 return -EFAULT; in tg3_hwtstamp_set()
13847 return -ERANGE; in tg3_hwtstamp_set()
13851 tp->rxptpctl = 0; in tg3_hwtstamp_set()
13854 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13858 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13862 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V1_EN | in tg3_hwtstamp_set()
13866 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13870 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13874 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13878 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13882 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13886 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13890 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_EN | in tg3_hwtstamp_set()
13894 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN | in tg3_hwtstamp_set()
13898 tp->rxptpctl = TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN | in tg3_hwtstamp_set()
13902 return -ERANGE; in tg3_hwtstamp_set()
13905 if (netif_running(dev) && tp->rxptpctl) in tg3_hwtstamp_set()
13907 tp->rxptpctl | TG3_RX_PTP_CTL_HWTS_INTERLOCK); in tg3_hwtstamp_set()
13910 tg3_flag_set(tp, TX_TSTAMP_EN); in tg3_hwtstamp_set()
13912 tg3_flag_clear(tp, TX_TSTAMP_EN); in tg3_hwtstamp_set()
13914 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_set()
13915 -EFAULT : 0; in tg3_hwtstamp_set()
13920 struct tg3 *tp = netdev_priv(dev); in tg3_hwtstamp_get() local
13923 if (!tg3_flag(tp, PTP_CAPABLE)) in tg3_hwtstamp_get()
13924 return -EOPNOTSUPP; in tg3_hwtstamp_get()
13927 stmpconf.tx_type = (tg3_flag(tp, TX_TSTAMP_EN) ? in tg3_hwtstamp_get()
13930 switch (tp->rxptpctl) { in tg3_hwtstamp_get()
13972 return -ERANGE; in tg3_hwtstamp_get()
13975 return copy_to_user(ifr->ifr_data, &stmpconf, sizeof(stmpconf)) ? in tg3_hwtstamp_get()
13976 -EFAULT : 0; in tg3_hwtstamp_get()
13982 struct tg3 *tp = netdev_priv(dev); in tg3_ioctl() local
13985 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_ioctl()
13987 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) in tg3_ioctl()
13988 return -EAGAIN; in tg3_ioctl()
13989 phydev = mdiobus_get_phy(tp->mdio_bus, tp->phy_addr); in tg3_ioctl()
13995 data->phy_id = tp->phy_addr; in tg3_ioctl()
14001 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14005 return -EAGAIN; in tg3_ioctl()
14007 spin_lock_bh(&tp->lock); in tg3_ioctl()
14008 err = __tg3_readphy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14009 data->reg_num & 0x1f, &mii_regval); in tg3_ioctl()
14010 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14012 data->val_out = mii_regval; in tg3_ioctl()
14018 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_ioctl()
14022 return -EAGAIN; in tg3_ioctl()
14024 spin_lock_bh(&tp->lock); in tg3_ioctl()
14025 err = __tg3_writephy(tp, data->phy_id & 0x1f, in tg3_ioctl()
14026 data->reg_num & 0x1f, data->val_in); in tg3_ioctl()
14027 spin_unlock_bh(&tp->lock); in tg3_ioctl()
14041 return -EOPNOTSUPP; in tg3_ioctl()
14049 struct tg3 *tp = netdev_priv(dev); in tg3_get_coalesce() local
14051 memcpy(ec, &tp->coal, sizeof(*ec)); in tg3_get_coalesce()
14060 struct tg3 *tp = netdev_priv(dev); in tg3_set_coalesce() local
14064 if (!tg3_flag(tp, 5705_PLUS)) { in tg3_set_coalesce()
14071 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) || in tg3_set_coalesce()
14072 (!ec->rx_coalesce_usecs) || in tg3_set_coalesce()
14073 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) || in tg3_set_coalesce()
14074 (!ec->tx_coalesce_usecs) || in tg3_set_coalesce()
14075 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) || in tg3_set_coalesce()
14076 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) || in tg3_set_coalesce()
14077 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) || in tg3_set_coalesce()
14078 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) || in tg3_set_coalesce()
14079 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) || in tg3_set_coalesce()
14080 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) || in tg3_set_coalesce()
14081 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) || in tg3_set_coalesce()
14082 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks)) in tg3_set_coalesce()
14083 return -EINVAL; in tg3_set_coalesce()
14086 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs; in tg3_set_coalesce()
14087 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs; in tg3_set_coalesce()
14088 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames; in tg3_set_coalesce()
14089 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames; in tg3_set_coalesce()
14090 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq; in tg3_set_coalesce()
14091 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq; in tg3_set_coalesce()
14092 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq; in tg3_set_coalesce()
14093 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq; in tg3_set_coalesce()
14094 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs; in tg3_set_coalesce()
14097 tg3_full_lock(tp, 0); in tg3_set_coalesce()
14098 __tg3_set_coalesce(tp, &tp->coal); in tg3_set_coalesce()
14099 tg3_full_unlock(tp); in tg3_set_coalesce()
14106 struct tg3 *tp = netdev_priv(dev); in tg3_set_eee() local
14108 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_set_eee()
14109 netdev_warn(tp->dev, "Board does not support EEE!\n"); in tg3_set_eee()
14110 return -EOPNOTSUPP; in tg3_set_eee()
14113 if (edata->advertised != tp->eee.advertised) { in tg3_set_eee()
14114 netdev_warn(tp->dev, in tg3_set_eee()
14116 return -EINVAL; in tg3_set_eee()
14119 if (edata->tx_lpi_timer > TG3_CPMU_DBTMR1_LNKIDLE_MAX) { in tg3_set_eee()
14120 netdev_warn(tp->dev, in tg3_set_eee()
14123 return -EINVAL; in tg3_set_eee()
14126 tp->eee = *edata; in tg3_set_eee()
14128 tp->phy_flags |= TG3_PHYFLG_USER_CONFIGURED; in tg3_set_eee()
14129 tg3_warn_mgmt_link_flap(tp); in tg3_set_eee()
14131 if (netif_running(tp->dev)) { in tg3_set_eee()
14132 tg3_full_lock(tp, 0); in tg3_set_eee()
14133 tg3_setup_eee(tp); in tg3_set_eee()
14134 tg3_phy_reset(tp); in tg3_set_eee()
14135 tg3_full_unlock(tp); in tg3_set_eee()
14143 struct tg3 *tp = netdev_priv(dev); in tg3_get_eee() local
14145 if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP)) { in tg3_get_eee()
14146 netdev_warn(tp->dev, in tg3_get_eee()
14148 return -EOPNOTSUPP; in tg3_get_eee()
14151 *edata = tp->eee; in tg3_get_eee()
14200 struct tg3 *tp = netdev_priv(dev); in tg3_get_stats64() local
14202 spin_lock_bh(&tp->lock); in tg3_get_stats64()
14203 if (!tp->hw_stats || !tg3_flag(tp, INIT_COMPLETE)) { in tg3_get_stats64()
14204 *stats = tp->net_stats_prev; in tg3_get_stats64()
14205 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14209 tg3_get_nstats(tp, stats); in tg3_get_stats64()
14210 spin_unlock_bh(&tp->lock); in tg3_get_stats64()
14215 struct tg3 *tp = netdev_priv(dev); in tg3_set_rx_mode() local
14220 tg3_full_lock(tp, 0); in tg3_set_rx_mode()
14222 tg3_full_unlock(tp); in tg3_set_rx_mode()
14225 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp, in tg3_set_mtu() argument
14228 dev->mtu = new_mtu; in tg3_set_mtu()
14231 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
14233 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_set_mtu()
14235 tg3_flag_set(tp, JUMBO_RING_ENABLE); in tg3_set_mtu()
14238 if (tg3_flag(tp, 5780_CLASS)) { in tg3_set_mtu()
14239 tg3_flag_set(tp, TSO_CAPABLE); in tg3_set_mtu()
14242 tg3_flag_clear(tp, JUMBO_RING_ENABLE); in tg3_set_mtu()
14248 struct tg3 *tp = netdev_priv(dev); in tg3_change_mtu() local
14256 tg3_set_mtu(dev, tp, new_mtu); in tg3_change_mtu()
14260 tg3_phy_stop(tp); in tg3_change_mtu()
14262 tg3_netif_stop(tp); in tg3_change_mtu()
14264 tg3_set_mtu(dev, tp, new_mtu); in tg3_change_mtu()
14266 tg3_full_lock(tp, 1); in tg3_change_mtu()
14268 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_change_mtu()
14273 if (tg3_asic_rev(tp) == ASIC_REV_57766 || in tg3_change_mtu()
14274 tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_change_mtu()
14275 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_change_mtu()
14276 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_change_mtu()
14279 err = tg3_restart_hw(tp, reset_phy); in tg3_change_mtu()
14282 tg3_netif_start(tp); in tg3_change_mtu()
14284 tg3_full_unlock(tp); in tg3_change_mtu()
14287 tg3_phy_start(tp); in tg3_change_mtu()
14310 static void tg3_get_eeprom_size(struct tg3 *tp) in tg3_get_eeprom_size() argument
14314 tp->nvram_size = EEPROM_CHIP_SIZE; in tg3_get_eeprom_size()
14316 if (tg3_nvram_read(tp, 0, &magic) != 0) in tg3_get_eeprom_size()
14331 while (cursize < tp->nvram_size) { in tg3_get_eeprom_size()
14332 if (tg3_nvram_read(tp, cursize, &val) != 0) in tg3_get_eeprom_size()
14341 tp->nvram_size = cursize; in tg3_get_eeprom_size()
14344 static void tg3_get_nvram_size(struct tg3 *tp) in tg3_get_nvram_size() argument
14348 if (tg3_flag(tp, NO_NVRAM) || tg3_nvram_read(tp, 0, &val) != 0) in tg3_get_nvram_size()
14353 tg3_get_eeprom_size(tp); in tg3_get_nvram_size()
14357 if (tg3_nvram_read(tp, 0xf0, &val) == 0) { in tg3_get_nvram_size()
14360 * 16-bit value at offset 0xf2. The tg3_nvram_read() in tg3_get_nvram_size()
14364 * want will always reside in the lower 16-bits. in tg3_get_nvram_size()
14367 * opposite the endianness of the CPU. The 16-bit in tg3_get_nvram_size()
14370 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024; in tg3_get_nvram_size()
14374 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_nvram_size()
14377 static void tg3_get_nvram_info(struct tg3 *tp) in tg3_get_nvram_info() argument
14383 tg3_flag_set(tp, FLASH); in tg3_get_nvram_info()
14389 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_get_nvram_info()
14390 tg3_flag(tp, 5780_CLASS)) { in tg3_get_nvram_info()
14393 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14394 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14395 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14398 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14399 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE; in tg3_get_nvram_info()
14402 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14403 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_nvram_info()
14404 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14407 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_nvram_info()
14408 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE; in tg3_get_nvram_info()
14409 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14412 tp->nvram_jedecnum = JEDEC_SAIFUN; in tg3_get_nvram_info()
14413 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE; in tg3_get_nvram_info()
14417 tp->nvram_jedecnum = JEDEC_SST; in tg3_get_nvram_info()
14418 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE; in tg3_get_nvram_info()
14422 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_nvram_info()
14423 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE; in tg3_get_nvram_info()
14424 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_nvram_info()
14428 static void tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1) in tg3_nvram_get_pagesize() argument
14432 tp->nvram_pagesize = 256; in tg3_nvram_get_pagesize()
14435 tp->nvram_pagesize = 512; in tg3_nvram_get_pagesize()
14438 tp->nvram_pagesize = 1024; in tg3_nvram_get_pagesize()
14441 tp->nvram_pagesize = 2048; in tg3_nvram_get_pagesize()
14444 tp->nvram_pagesize = 4096; in tg3_nvram_get_pagesize()
14447 tp->nvram_pagesize = 264; in tg3_nvram_get_pagesize()
14450 tp->nvram_pagesize = 528; in tg3_nvram_get_pagesize()
14455 static void tg3_get_5752_nvram_info(struct tg3 *tp) in tg3_get_5752_nvram_info() argument
14463 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5752_nvram_info()
14468 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14469 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14472 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5752_nvram_info()
14473 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14474 tg3_flag_set(tp, FLASH); in tg3_get_5752_nvram_info()
14479 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5752_nvram_info()
14480 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5752_nvram_info()
14481 tg3_flag_set(tp, FLASH); in tg3_get_5752_nvram_info()
14485 if (tg3_flag(tp, FLASH)) { in tg3_get_5752_nvram_info()
14486 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5752_nvram_info()
14489 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5752_nvram_info()
14496 static void tg3_get_5755_nvram_info(struct tg3 *tp) in tg3_get_5755_nvram_info() argument
14504 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5755_nvram_info()
14514 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5755_nvram_info()
14515 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5755_nvram_info()
14516 tg3_flag_set(tp, FLASH); in tg3_get_5755_nvram_info()
14517 tp->nvram_pagesize = 264; in tg3_get_5755_nvram_info()
14520 tp->nvram_size = (protect ? 0x3e200 : in tg3_get_5755_nvram_info()
14523 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14526 tp->nvram_size = (protect ? 0x1f200 : in tg3_get_5755_nvram_info()
14532 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5755_nvram_info()
14533 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5755_nvram_info()
14534 tg3_flag_set(tp, FLASH); in tg3_get_5755_nvram_info()
14535 tp->nvram_pagesize = 256; in tg3_get_5755_nvram_info()
14537 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14541 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14545 tp->nvram_size = (protect ? in tg3_get_5755_nvram_info()
14552 static void tg3_get_5787_nvram_info(struct tg3 *tp) in tg3_get_5787_nvram_info() argument
14563 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14564 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14565 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5787_nvram_info()
14574 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5787_nvram_info()
14575 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14576 tg3_flag_set(tp, FLASH); in tg3_get_5787_nvram_info()
14577 tp->nvram_pagesize = 264; in tg3_get_5787_nvram_info()
14582 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5787_nvram_info()
14583 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5787_nvram_info()
14584 tg3_flag_set(tp, FLASH); in tg3_get_5787_nvram_info()
14585 tp->nvram_pagesize = 256; in tg3_get_5787_nvram_info()
14590 static void tg3_get_5761_nvram_info(struct tg3 *tp) in tg3_get_5761_nvram_info() argument
14598 tg3_flag_set(tp, PROTECTED_NVRAM); in tg3_get_5761_nvram_info()
14612 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5761_nvram_info()
14613 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5761_nvram_info()
14614 tg3_flag_set(tp, FLASH); in tg3_get_5761_nvram_info()
14615 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5761_nvram_info()
14616 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14626 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5761_nvram_info()
14627 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5761_nvram_info()
14628 tg3_flag_set(tp, FLASH); in tg3_get_5761_nvram_info()
14629 tp->nvram_pagesize = 256; in tg3_get_5761_nvram_info()
14634 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT); in tg3_get_5761_nvram_info()
14641 tp->nvram_size = TG3_NVRAM_SIZE_2MB; in tg3_get_5761_nvram_info()
14647 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5761_nvram_info()
14653 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5761_nvram_info()
14659 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5761_nvram_info()
14665 static void tg3_get_5906_nvram_info(struct tg3 *tp) in tg3_get_5906_nvram_info() argument
14667 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5906_nvram_info()
14668 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5906_nvram_info()
14669 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5906_nvram_info()
14672 static void tg3_get_57780_nvram_info(struct tg3 *tp) in tg3_get_57780_nvram_info() argument
14681 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14682 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14683 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_57780_nvram_info()
14695 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_57780_nvram_info()
14696 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14697 tg3_flag_set(tp, FLASH); in tg3_get_57780_nvram_info()
14703 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14707 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14711 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14718 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_57780_nvram_info()
14719 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_57780_nvram_info()
14720 tg3_flag_set(tp, FLASH); in tg3_get_57780_nvram_info()
14724 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_57780_nvram_info()
14727 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_57780_nvram_info()
14730 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_57780_nvram_info()
14735 tg3_flag_set(tp, NO_NVRAM); in tg3_get_57780_nvram_info()
14739 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_57780_nvram_info()
14740 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_57780_nvram_info()
14741 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_57780_nvram_info()
14745 static void tg3_get_5717_nvram_info(struct tg3 *tp) in tg3_get_5717_nvram_info() argument
14754 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14755 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14756 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5717_nvram_info()
14768 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5717_nvram_info()
14769 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14770 tg3_flag_set(tp, FLASH); in tg3_get_5717_nvram_info()
14778 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14781 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14795 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5717_nvram_info()
14796 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5717_nvram_info()
14797 tg3_flag_set(tp, FLASH); in tg3_get_5717_nvram_info()
14806 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5717_nvram_info()
14809 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5717_nvram_info()
14814 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5717_nvram_info()
14818 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5717_nvram_info()
14819 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5717_nvram_info()
14820 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5717_nvram_info()
14823 static void tg3_get_5720_nvram_info(struct tg3 *tp) in tg3_get_5720_nvram_info() argument
14830 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_get_5720_nvram_info()
14832 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14842 tp->nvram_pagesize = 4096; in tg3_get_5720_nvram_info()
14843 tp->nvram_jedecnum = JEDEC_MACRONIX; in tg3_get_5720_nvram_info()
14844 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14845 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5720_nvram_info()
14846 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14848 tp->nvram_size = in tg3_get_5720_nvram_info()
14872 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14873 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14878 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE; in tg3_get_5720_nvram_info()
14880 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE; in tg3_get_5720_nvram_info()
14894 tp->nvram_jedecnum = JEDEC_ATMEL; in tg3_get_5720_nvram_info()
14895 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14896 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14902 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14907 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14911 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14914 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_get_5720_nvram_info()
14915 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14937 tp->nvram_jedecnum = JEDEC_ST; in tg3_get_5720_nvram_info()
14938 tg3_flag_set(tp, NVRAM_BUFFERED); in tg3_get_5720_nvram_info()
14939 tg3_flag_set(tp, FLASH); in tg3_get_5720_nvram_info()
14946 tp->nvram_size = TG3_NVRAM_SIZE_256KB; in tg3_get_5720_nvram_info()
14952 tp->nvram_size = TG3_NVRAM_SIZE_512KB; in tg3_get_5720_nvram_info()
14958 tp->nvram_size = TG3_NVRAM_SIZE_1MB; in tg3_get_5720_nvram_info()
14961 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_get_5720_nvram_info()
14962 tp->nvram_size = TG3_NVRAM_SIZE_128KB; in tg3_get_5720_nvram_info()
14967 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14971 tg3_nvram_get_pagesize(tp, nvcfg1); in tg3_get_5720_nvram_info()
14972 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528) in tg3_get_5720_nvram_info()
14973 tg3_flag_set(tp, NO_NVRAM_ADDR_TRANS); in tg3_get_5720_nvram_info()
14975 if (tg3_asic_rev(tp) == ASIC_REV_5762) { in tg3_get_5720_nvram_info()
14978 if (tg3_nvram_read(tp, 0, &val)) in tg3_get_5720_nvram_info()
14983 tg3_flag_set(tp, NO_NVRAM); in tg3_get_5720_nvram_info()
14988 static void tg3_nvram_init(struct tg3 *tp) in tg3_nvram_init() argument
14990 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_nvram_init()
14992 tg3_flag_clear(tp, NVRAM); in tg3_nvram_init()
14993 tg3_flag_clear(tp, NVRAM_BUFFERED); in tg3_nvram_init()
14994 tg3_flag_set(tp, NO_NVRAM); in tg3_nvram_init()
15010 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_nvram_init()
15011 tg3_asic_rev(tp) != ASIC_REV_5701) { in tg3_nvram_init()
15012 tg3_flag_set(tp, NVRAM); in tg3_nvram_init()
15014 if (tg3_nvram_lock(tp)) { in tg3_nvram_init()
15015 netdev_warn(tp->dev, in tg3_nvram_init()
15020 tg3_enable_nvram_access(tp); in tg3_nvram_init()
15022 tp->nvram_size = 0; in tg3_nvram_init()
15024 if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_nvram_init()
15025 tg3_get_5752_nvram_info(tp); in tg3_nvram_init()
15026 else if (tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_nvram_init()
15027 tg3_get_5755_nvram_info(tp); in tg3_nvram_init()
15028 else if (tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_nvram_init()
15029 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_nvram_init()
15030 tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_nvram_init()
15031 tg3_get_5787_nvram_info(tp); in tg3_nvram_init()
15032 else if (tg3_asic_rev(tp) == ASIC_REV_5761) in tg3_nvram_init()
15033 tg3_get_5761_nvram_info(tp); in tg3_nvram_init()
15034 else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_nvram_init()
15035 tg3_get_5906_nvram_info(tp); in tg3_nvram_init()
15036 else if (tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_nvram_init()
15037 tg3_flag(tp, 57765_CLASS)) in tg3_nvram_init()
15038 tg3_get_57780_nvram_info(tp); in tg3_nvram_init()
15039 else if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_nvram_init()
15040 tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_nvram_init()
15041 tg3_get_5717_nvram_info(tp); in tg3_nvram_init()
15042 else if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_nvram_init()
15043 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_nvram_init()
15044 tg3_get_5720_nvram_info(tp); in tg3_nvram_init()
15046 tg3_get_nvram_info(tp); in tg3_nvram_init()
15048 if (tp->nvram_size == 0) in tg3_nvram_init()
15049 tg3_get_nvram_size(tp); in tg3_nvram_init()
15051 tg3_disable_nvram_access(tp); in tg3_nvram_init()
15052 tg3_nvram_unlock(tp); in tg3_nvram_init()
15055 tg3_flag_clear(tp, NVRAM); in tg3_nvram_init()
15056 tg3_flag_clear(tp, NVRAM_BUFFERED); in tg3_nvram_init()
15058 tg3_get_eeprom_size(tp); in tg3_nvram_init()
15131 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp) in tg3_lookup_by_subsys() argument
15137 tp->pdev->subsystem_vendor) && in tg3_lookup_by_subsys()
15139 tp->pdev->subsystem_device)) in tg3_lookup_by_subsys()
15145 static void tg3_get_eeprom_hw_cfg(struct tg3 *tp) in tg3_get_eeprom_hw_cfg() argument
15149 tp->phy_id = TG3_PHY_ID_INVALID; in tg3_get_eeprom_hw_cfg()
15150 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15153 tg3_flag_set(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15154 tg3_flag_set(tp, WOL_CAP); in tg3_get_eeprom_hw_cfg()
15156 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_eeprom_hw_cfg()
15158 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15159 tg3_flag_set(tp, IS_NIC); in tg3_get_eeprom_hw_cfg()
15163 tg3_flag_set(tp, ASPM_WORKAROUND); in tg3_get_eeprom_hw_cfg()
15166 tg3_flag_set(tp, WOL_ENABLE); in tg3_get_eeprom_hw_cfg()
15167 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15172 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val); in tg3_get_eeprom_hw_cfg()
15179 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); in tg3_get_eeprom_hw_cfg()
15180 tp->nic_sram_data_cfg = nic_cfg; in tg3_get_eeprom_hw_cfg()
15182 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver); in tg3_get_eeprom_hw_cfg()
15184 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_get_eeprom_hw_cfg()
15185 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_get_eeprom_hw_cfg()
15186 tg3_asic_rev(tp) != ASIC_REV_5703 && in tg3_get_eeprom_hw_cfg()
15188 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2); in tg3_get_eeprom_hw_cfg()
15190 if (tg3_asic_rev(tp) == ASIC_REV_5785) in tg3_get_eeprom_hw_cfg()
15191 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4); in tg3_get_eeprom_hw_cfg()
15193 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_eeprom_hw_cfg()
15194 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_eeprom_hw_cfg()
15195 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_get_eeprom_hw_cfg()
15196 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_5, &cfg5); in tg3_get_eeprom_hw_cfg()
15202 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id); in tg3_get_eeprom_hw_cfg()
15213 tp->phy_id = eeprom_phy_id; in tg3_get_eeprom_hw_cfg()
15215 if (!tg3_flag(tp, 5705_PLUS)) in tg3_get_eeprom_hw_cfg()
15216 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_get_eeprom_hw_cfg()
15218 tp->phy_flags |= TG3_PHYFLG_MII_SERDES; in tg3_get_eeprom_hw_cfg()
15221 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15230 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15234 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15238 tp->led_ctrl = LED_CTRL_MODE_MAC; in tg3_get_eeprom_hw_cfg()
15243 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
15244 tg3_asic_rev(tp) == ASIC_REV_5701) in tg3_get_eeprom_hw_cfg()
15245 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15250 tp->led_ctrl = LED_CTRL_MODE_SHARED; in tg3_get_eeprom_hw_cfg()
15251 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0 && in tg3_get_eeprom_hw_cfg()
15252 tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A1) in tg3_get_eeprom_hw_cfg()
15253 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15256 if (tg3_flag(tp, 5717_PLUS) || in tg3_get_eeprom_hw_cfg()
15257 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_eeprom_hw_cfg()
15258 tp->led_ctrl |= LED_CTRL_BLINK_RATE_OVERRIDE | in tg3_get_eeprom_hw_cfg()
15264 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC; in tg3_get_eeprom_hw_cfg()
15268 tp->led_ctrl = LED_CTRL_MODE_COMBO; in tg3_get_eeprom_hw_cfg()
15269 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5750_A0) in tg3_get_eeprom_hw_cfg()
15270 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 | in tg3_get_eeprom_hw_cfg()
15276 if ((tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_eeprom_hw_cfg()
15277 tg3_asic_rev(tp) == ASIC_REV_5701) && in tg3_get_eeprom_hw_cfg()
15278 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL) in tg3_get_eeprom_hw_cfg()
15279 tp->led_ctrl = LED_CTRL_MODE_PHY_2; in tg3_get_eeprom_hw_cfg()
15281 if (tg3_chip_rev(tp) == CHIPREV_5784_AX) in tg3_get_eeprom_hw_cfg()
15282 tp->led_ctrl = LED_CTRL_MODE_PHY_1; in tg3_get_eeprom_hw_cfg()
15285 tg3_flag_set(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15286 if ((tp->pdev->subsystem_vendor == in tg3_get_eeprom_hw_cfg()
15288 (tp->pdev->subsystem_device == 0x205a || in tg3_get_eeprom_hw_cfg()
15289 tp->pdev->subsystem_device == 0x2063)) in tg3_get_eeprom_hw_cfg()
15290 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15292 tg3_flag_clear(tp, EEPROM_WRITE_PROT); in tg3_get_eeprom_hw_cfg()
15293 tg3_flag_set(tp, IS_NIC); in tg3_get_eeprom_hw_cfg()
15297 tg3_flag_set(tp, ENABLE_ASF); in tg3_get_eeprom_hw_cfg()
15298 if (tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15299 tg3_flag_set(tp, ASF_NEW_HANDSHAKE); in tg3_get_eeprom_hw_cfg()
15303 tg3_flag(tp, 5750_PLUS)) in tg3_get_eeprom_hw_cfg()
15304 tg3_flag_set(tp, ENABLE_APE); in tg3_get_eeprom_hw_cfg()
15306 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES && in tg3_get_eeprom_hw_cfg()
15308 tg3_flag_clear(tp, WOL_CAP); in tg3_get_eeprom_hw_cfg()
15310 if (tg3_flag(tp, WOL_CAP) && in tg3_get_eeprom_hw_cfg()
15312 tg3_flag_set(tp, WOL_ENABLE); in tg3_get_eeprom_hw_cfg()
15313 device_set_wakeup_enable(&tp->pdev->dev, true); in tg3_get_eeprom_hw_cfg()
15317 tp->phy_flags |= TG3_PHYFLG_CAPACITIVE_COUPLING; in tg3_get_eeprom_hw_cfg()
15319 /* serdes signal pre-emphasis in register 0x590 set by */ in tg3_get_eeprom_hw_cfg()
15322 tp->phy_flags |= TG3_PHYFLG_SERDES_PREEMPHASIS; in tg3_get_eeprom_hw_cfg()
15324 if ((tg3_flag(tp, 57765_PLUS) || in tg3_get_eeprom_hw_cfg()
15325 (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_get_eeprom_hw_cfg()
15326 tg3_chip_rev(tp) != CHIPREV_5784_AX)) && in tg3_get_eeprom_hw_cfg()
15328 tp->phy_flags |= TG3_PHYFLG_ENABLE_APD; in tg3_get_eeprom_hw_cfg()
15330 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_get_eeprom_hw_cfg()
15333 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3); in tg3_get_eeprom_hw_cfg()
15334 if (tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_get_eeprom_hw_cfg()
15335 !tg3_flag(tp, 57765_PLUS) && in tg3_get_eeprom_hw_cfg()
15337 tg3_flag_set(tp, ASPM_WORKAROUND); in tg3_get_eeprom_hw_cfg()
15339 tp->phy_flags |= TG3_PHYFLG_KEEP_LINK_ON_PWRDN; in tg3_get_eeprom_hw_cfg()
15341 tp->phy_flags |= TG3_PHYFLG_1G_ON_VAUX_OK; in tg3_get_eeprom_hw_cfg()
15345 tg3_flag_set(tp, RGMII_INBAND_DISABLE); in tg3_get_eeprom_hw_cfg()
15347 tg3_flag_set(tp, RGMII_EXT_IBND_RX_EN); in tg3_get_eeprom_hw_cfg()
15349 tg3_flag_set(tp, RGMII_EXT_IBND_TX_EN); in tg3_get_eeprom_hw_cfg()
15352 tp->phy_flags |= TG3_PHYFLG_DISABLE_1G_HD_ADV; in tg3_get_eeprom_hw_cfg()
15355 if (tg3_flag(tp, WOL_CAP)) in tg3_get_eeprom_hw_cfg()
15356 device_set_wakeup_enable(&tp->pdev->dev, in tg3_get_eeprom_hw_cfg()
15357 tg3_flag(tp, WOL_ENABLE)); in tg3_get_eeprom_hw_cfg()
15359 device_set_wakeup_capable(&tp->pdev->dev, false); in tg3_get_eeprom_hw_cfg()
15362 static int tg3_ape_otp_read(struct tg3 *tp, u32 offset, u32 *val) in tg3_ape_otp_read() argument
15367 err = tg3_nvram_lock(tp); in tg3_ape_otp_read()
15371 tg3_ape_write32(tp, TG3_APE_OTP_ADDR, off | APE_OTP_ADDR_CPU_ENABLE); in tg3_ape_otp_read()
15372 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, APE_OTP_CTRL_PROG_EN | in tg3_ape_otp_read()
15374 tg3_ape_read32(tp, TG3_APE_OTP_CTRL); in tg3_ape_otp_read()
15378 val2 = tg3_ape_read32(tp, TG3_APE_OTP_STATUS); in tg3_ape_otp_read()
15380 *val = tg3_ape_read32(tp, TG3_APE_OTP_RD_DATA); in tg3_ape_otp_read()
15386 tg3_ape_write32(tp, TG3_APE_OTP_CTRL, 0); in tg3_ape_otp_read()
15388 tg3_nvram_unlock(tp); in tg3_ape_otp_read()
15392 return -EBUSY; in tg3_ape_otp_read()
15395 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd) in tg3_issue_otp_command() argument
15411 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY; in tg3_issue_otp_command()
15415 * configuration is a 32-bit value that straddles the alignment boundary.
15416 * We do two 32-bit reads and then shift and merge the results.
15418 static u32 tg3_read_otp_phycfg(struct tg3 *tp) in tg3_read_otp_phycfg() argument
15424 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT)) in tg3_read_otp_phycfg()
15429 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
15436 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ)) in tg3_read_otp_phycfg()
15444 static void tg3_phy_init_link_config(struct tg3 *tp) in tg3_phy_init_link_config() argument
15448 if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) { in tg3_phy_init_link_config()
15449 if (!(tp->phy_flags & TG3_PHYFLG_DISABLE_1G_HD_ADV)) in tg3_phy_init_link_config()
15454 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_phy_init_link_config()
15463 tp->link_config.advertising = adv; in tg3_phy_init_link_config()
15464 tp->link_config.speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15465 tp->link_config.duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15466 tp->link_config.autoneg = AUTONEG_ENABLE; in tg3_phy_init_link_config()
15467 tp->link_config.active_speed = SPEED_UNKNOWN; in tg3_phy_init_link_config()
15468 tp->link_config.active_duplex = DUPLEX_UNKNOWN; in tg3_phy_init_link_config()
15470 tp->old_link = -1; in tg3_phy_init_link_config()
15473 static int tg3_phy_probe(struct tg3 *tp) in tg3_phy_probe() argument
15480 tg3_flag_set(tp, PAUSE_AUTONEG); in tg3_phy_probe()
15481 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX; in tg3_phy_probe()
15483 if (tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
15484 switch (tp->pci_fn) { in tg3_phy_probe()
15486 tp->phy_ape_lock = TG3_APE_LOCK_PHY0; in tg3_phy_probe()
15489 tp->phy_ape_lock = TG3_APE_LOCK_PHY1; in tg3_phy_probe()
15492 tp->phy_ape_lock = TG3_APE_LOCK_PHY2; in tg3_phy_probe()
15495 tp->phy_ape_lock = TG3_APE_LOCK_PHY3; in tg3_phy_probe()
15500 if (!tg3_flag(tp, ENABLE_ASF) && in tg3_phy_probe()
15501 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15502 !(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) in tg3_phy_probe()
15503 tp->phy_flags &= ~(TG3_PHYFLG_1G_ON_VAUX_OK | in tg3_phy_probe()
15506 if (tg3_flag(tp, USE_PHYLIB)) in tg3_phy_probe()
15507 return tg3_phy_init(tp); in tg3_phy_probe()
15513 if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) { in tg3_phy_probe()
15518 * to either the hard-coded table based PHY_ID and failing in tg3_phy_probe()
15521 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1); in tg3_phy_probe()
15522 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2); in tg3_phy_probe()
15532 tp->phy_id = hw_phy_id; in tg3_phy_probe()
15534 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15536 tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15538 if (tp->phy_id != TG3_PHY_ID_INVALID) { in tg3_phy_probe()
15548 p = tg3_lookup_by_subsys(tp); in tg3_phy_probe()
15550 tp->phy_id = p->phy_id; in tg3_phy_probe()
15551 } else if (!tg3_flag(tp, IS_SSB_CORE)) { in tg3_phy_probe()
15559 return -ENODEV; in tg3_phy_probe()
15562 if (!tp->phy_id || in tg3_phy_probe()
15563 tp->phy_id == TG3_PHY_ID_BCM8002) in tg3_phy_probe()
15564 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES; in tg3_phy_probe()
15568 if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15569 (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_phy_probe()
15570 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_phy_probe()
15571 tg3_asic_rev(tp) == ASIC_REV_57766 || in tg3_phy_probe()
15572 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_phy_probe()
15573 (tg3_asic_rev(tp) == ASIC_REV_5717 && in tg3_phy_probe()
15574 tg3_chip_rev_id(tp) != CHIPREV_ID_5717_A0) || in tg3_phy_probe()
15575 (tg3_asic_rev(tp) == ASIC_REV_57765 && in tg3_phy_probe()
15576 tg3_chip_rev_id(tp) != CHIPREV_ID_57765_A0))) { in tg3_phy_probe()
15577 tp->phy_flags |= TG3_PHYFLG_EEE_CAP; in tg3_phy_probe()
15579 tp->eee.supported = SUPPORTED_100baseT_Full | in tg3_phy_probe()
15581 tp->eee.advertised = ADVERTISED_100baseT_Full | in tg3_phy_probe()
15583 tp->eee.eee_enabled = 1; in tg3_phy_probe()
15584 tp->eee.tx_lpi_enabled = 1; in tg3_phy_probe()
15585 tp->eee.tx_lpi_timer = TG3_CPMU_DBTMR1_LNKIDLE_2047US; in tg3_phy_probe()
15588 tg3_phy_init_link_config(tp); in tg3_phy_probe()
15590 if (!(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN) && in tg3_phy_probe()
15591 !(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) && in tg3_phy_probe()
15592 !tg3_flag(tp, ENABLE_APE) && in tg3_phy_probe()
15593 !tg3_flag(tp, ENABLE_ASF)) { in tg3_phy_probe()
15596 tg3_readphy(tp, MII_BMSR, &bmsr); in tg3_phy_probe()
15597 if (!tg3_readphy(tp, MII_BMSR, &bmsr) && in tg3_phy_probe()
15601 err = tg3_phy_reset(tp); in tg3_phy_probe()
15605 tg3_phy_set_wirespeed(tp); in tg3_phy_probe()
15607 if (!tg3_phy_copper_an_config_ok(tp, &dummy)) { in tg3_phy_probe()
15608 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising, in tg3_phy_probe()
15609 tp->link_config.flowctrl); in tg3_phy_probe()
15611 tg3_writephy(tp, MII_BMCR, in tg3_phy_probe()
15617 if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) { in tg3_phy_probe()
15618 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
15622 err = tg3_init_5401phy_dsp(tp); in tg3_phy_probe()
15628 static void tg3_read_vpd(struct tg3 *tp) in tg3_read_vpd() argument
15634 vpd_data = (u8 *)tg3_vpd_readblock(tp, &vpdlen); in tg3_read_vpd()
15651 memset(tp->fw_ver, 0, sizeof(tp->fw_ver)); in tg3_read_vpd()
15652 snprintf(tp->fw_ver, sizeof(tp->fw_ver), "%.*s bc ", len, vpd_data + i); in tg3_read_vpd()
15663 memcpy(tp->board_part_number, &vpd_data[i], len); in tg3_read_vpd()
15667 if (tp->board_part_number[0]) in tg3_read_vpd()
15671 if (tg3_asic_rev(tp) == ASIC_REV_5717) { in tg3_read_vpd()
15672 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_read_vpd()
15673 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C) in tg3_read_vpd()
15674 strcpy(tp->board_part_number, "BCM5717"); in tg3_read_vpd()
15675 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718) in tg3_read_vpd()
15676 strcpy(tp->board_part_number, "BCM5718"); in tg3_read_vpd()
15679 } else if (tg3_asic_rev(tp) == ASIC_REV_57780) { in tg3_read_vpd()
15680 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780) in tg3_read_vpd()
15681 strcpy(tp->board_part_number, "BCM57780"); in tg3_read_vpd()
15682 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760) in tg3_read_vpd()
15683 strcpy(tp->board_part_number, "BCM57760"); in tg3_read_vpd()
15684 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790) in tg3_read_vpd()
15685 strcpy(tp->board_part_number, "BCM57790"); in tg3_read_vpd()
15686 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788) in tg3_read_vpd()
15687 strcpy(tp->board_part_number, "BCM57788"); in tg3_read_vpd()
15690 } else if (tg3_asic_rev(tp) == ASIC_REV_57765) { in tg3_read_vpd()
15691 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761) in tg3_read_vpd()
15692 strcpy(tp->board_part_number, "BCM57761"); in tg3_read_vpd()
15693 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765) in tg3_read_vpd()
15694 strcpy(tp->board_part_number, "BCM57765"); in tg3_read_vpd()
15695 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781) in tg3_read_vpd()
15696 strcpy(tp->board_part_number, "BCM57781"); in tg3_read_vpd()
15697 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785) in tg3_read_vpd()
15698 strcpy(tp->board_part_number, "BCM57785"); in tg3_read_vpd()
15699 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791) in tg3_read_vpd()
15700 strcpy(tp->board_part_number, "BCM57791"); in tg3_read_vpd()
15701 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795) in tg3_read_vpd()
15702 strcpy(tp->board_part_number, "BCM57795"); in tg3_read_vpd()
15705 } else if (tg3_asic_rev(tp) == ASIC_REV_57766) { in tg3_read_vpd()
15706 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762) in tg3_read_vpd()
15707 strcpy(tp->board_part_number, "BCM57762"); in tg3_read_vpd()
15708 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766) in tg3_read_vpd()
15709 strcpy(tp->board_part_number, "BCM57766"); in tg3_read_vpd()
15710 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782) in tg3_read_vpd()
15711 strcpy(tp->board_part_number, "BCM57782"); in tg3_read_vpd()
15712 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_read_vpd()
15713 strcpy(tp->board_part_number, "BCM57786"); in tg3_read_vpd()
15716 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_read_vpd()
15717 strcpy(tp->board_part_number, "BCM95906"); in tg3_read_vpd()
15720 strcpy(tp->board_part_number, "none"); in tg3_read_vpd()
15724 static int tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) in tg3_fw_img_is_valid() argument
15728 if (tg3_nvram_read(tp, offset, &val) || in tg3_fw_img_is_valid()
15730 tg3_nvram_read(tp, offset + 4, &val) || in tg3_fw_img_is_valid()
15737 static void tg3_read_bc_ver(struct tg3 *tp) in tg3_read_bc_ver() argument
15743 if (tg3_nvram_read(tp, 0xc, &offset) || in tg3_read_bc_ver()
15744 tg3_nvram_read(tp, 0x4, &start)) in tg3_read_bc_ver()
15747 offset = tg3_nvram_logical_addr(tp, offset); in tg3_read_bc_ver()
15749 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_bc_ver()
15753 if (tg3_nvram_read(tp, offset + 4, &val)) in tg3_read_bc_ver()
15760 dst_off = strlen(tp->fw_ver); in tg3_read_bc_ver()
15763 if (TG3_VER_SIZE - dst_off < 16 || in tg3_read_bc_ver()
15764 tg3_nvram_read(tp, offset + 8, &ver_offset)) in tg3_read_bc_ver()
15767 offset = offset + ver_offset - start; in tg3_read_bc_ver()
15770 if (tg3_nvram_read_be32(tp, offset + i, &v)) in tg3_read_bc_ver()
15773 memcpy(tp->fw_ver + dst_off + i, &v, sizeof(v)); in tg3_read_bc_ver()
15778 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset)) in tg3_read_bc_ver()
15784 snprintf(&tp->fw_ver[dst_off], TG3_VER_SIZE - dst_off, in tg3_read_bc_ver()
15789 static void tg3_read_hwsb_ver(struct tg3 *tp) in tg3_read_hwsb_ver() argument
15794 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val)) in tg3_read_hwsb_ver()
15802 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor); in tg3_read_hwsb_ver()
15805 static void tg3_read_sb_ver(struct tg3 *tp, u32 val) in tg3_read_sb_ver() argument
15809 strncat(tp->fw_ver, "sb", TG3_VER_SIZE - strlen(tp->fw_ver) - 1); in tg3_read_sb_ver()
15837 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_sb_ver()
15849 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15850 snprintf(&tp->fw_ver[offset], TG3_VER_SIZE - offset, in tg3_read_sb_ver()
15854 offset = strlen(tp->fw_ver); in tg3_read_sb_ver()
15855 if (offset < TG3_VER_SIZE - 1) in tg3_read_sb_ver()
15856 tp->fw_ver[offset] = 'a' + build - 1; in tg3_read_sb_ver()
15860 static void tg3_read_mgmtfw_ver(struct tg3 *tp) in tg3_read_mgmtfw_ver() argument
15868 if (tg3_nvram_read(tp, offset, &val)) in tg3_read_mgmtfw_ver()
15878 if (!tg3_flag(tp, 5705_PLUS)) in tg3_read_mgmtfw_ver()
15880 else if (tg3_nvram_read(tp, offset - 4, &start)) in tg3_read_mgmtfw_ver()
15883 if (tg3_nvram_read(tp, offset + 4, &offset) || in tg3_read_mgmtfw_ver()
15884 !tg3_fw_img_is_valid(tp, offset) || in tg3_read_mgmtfw_ver()
15885 tg3_nvram_read(tp, offset + 8, &val)) in tg3_read_mgmtfw_ver()
15888 offset += val - start; in tg3_read_mgmtfw_ver()
15890 vlen = strlen(tp->fw_ver); in tg3_read_mgmtfw_ver()
15892 tp->fw_ver[vlen++] = ','; in tg3_read_mgmtfw_ver()
15893 tp->fw_ver[vlen++] = ' '; in tg3_read_mgmtfw_ver()
15897 if (tg3_nvram_read_be32(tp, offset, &v)) in tg3_read_mgmtfw_ver()
15902 if (vlen > TG3_VER_SIZE - sizeof(v)) { in tg3_read_mgmtfw_ver()
15903 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); in tg3_read_mgmtfw_ver()
15907 memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); in tg3_read_mgmtfw_ver()
15912 static void tg3_probe_ncsi(struct tg3 *tp) in tg3_probe_ncsi() argument
15916 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG); in tg3_probe_ncsi()
15920 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS); in tg3_probe_ncsi()
15924 if (tg3_ape_read32(tp, TG3_APE_FW_FEATURES) & TG3_APE_FW_FEATURE_NCSI) in tg3_probe_ncsi()
15925 tg3_flag_set(tp, APE_HAS_NCSI); in tg3_probe_ncsi()
15928 static void tg3_read_dash_ver(struct tg3 *tp) in tg3_read_dash_ver() argument
15934 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION); in tg3_read_dash_ver()
15936 if (tg3_flag(tp, APE_HAS_NCSI)) in tg3_read_dash_ver()
15938 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725) in tg3_read_dash_ver()
15943 vlen = strlen(tp->fw_ver); in tg3_read_dash_ver()
15945 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " %s v%d.%d.%d.%d", in tg3_read_dash_ver()
15953 static void tg3_read_otp_ver(struct tg3 *tp) in tg3_read_otp_ver() argument
15957 if (tg3_asic_rev(tp) != ASIC_REV_5762) in tg3_read_otp_ver()
15960 if (!tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0, &val) && in tg3_read_otp_ver()
15961 !tg3_ape_otp_read(tp, OTP_ADDRESS_MAGIC0 + 4, &val2) && in tg3_read_otp_ver()
15973 vlen = strlen(tp->fw_ver); in tg3_read_otp_ver()
15974 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " .%02d", ver); in tg3_read_otp_ver()
15978 static void tg3_read_fw_ver(struct tg3 *tp) in tg3_read_fw_ver() argument
15983 if (tp->fw_ver[0] != 0) in tg3_read_fw_ver()
15986 if (tg3_flag(tp, NO_NVRAM)) { in tg3_read_fw_ver()
15987 strcat(tp->fw_ver, "sb"); in tg3_read_fw_ver()
15988 tg3_read_otp_ver(tp); in tg3_read_fw_ver()
15992 if (tg3_nvram_read(tp, 0, &val)) in tg3_read_fw_ver()
15996 tg3_read_bc_ver(tp); in tg3_read_fw_ver()
15998 tg3_read_sb_ver(tp, val); in tg3_read_fw_ver()
16000 tg3_read_hwsb_ver(tp); in tg3_read_fw_ver()
16002 if (tg3_flag(tp, ENABLE_ASF)) { in tg3_read_fw_ver()
16003 if (tg3_flag(tp, ENABLE_APE)) { in tg3_read_fw_ver()
16004 tg3_probe_ncsi(tp); in tg3_read_fw_ver()
16006 tg3_read_dash_ver(tp); in tg3_read_fw_ver()
16008 tg3_read_mgmtfw_ver(tp); in tg3_read_fw_ver()
16012 tp->fw_ver[TG3_VER_SIZE - 1] = 0; in tg3_read_fw_ver()
16015 static inline u32 tg3_rx_ret_ring_size(struct tg3 *tp) in tg3_rx_ret_ring_size() argument
16017 if (tg3_flag(tp, LRG_PROD_RING_CAP)) in tg3_rx_ret_ring_size()
16019 else if (tg3_flag(tp, JUMBO_CAPABLE) && !tg3_flag(tp, 5780_CLASS)) in tg3_rx_ret_ring_size()
16032 static struct pci_dev *tg3_find_peer(struct tg3 *tp) in tg3_find_peer() argument
16035 unsigned int func, devnr = tp->pdev->devfn & ~7; in tg3_find_peer()
16038 peer = pci_get_slot(tp->pdev->bus, devnr | func); in tg3_find_peer()
16039 if (peer && peer != tp->pdev) in tg3_find_peer()
16043 /* 5704 can be configured in single-port mode, set peer to in tg3_find_peer()
16044 * tp->pdev in that case. in tg3_find_peer()
16047 peer = tp->pdev; in tg3_find_peer()
16060 static void tg3_detect_asic_rev(struct tg3 *tp, u32 misc_ctrl_reg) in tg3_detect_asic_rev() argument
16062 tp->pci_chip_rev_id = misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT; in tg3_detect_asic_rev()
16063 if (tg3_asic_rev(tp) == ASIC_REV_USE_PROD_ID_REG) { in tg3_detect_asic_rev()
16069 tg3_flag_set(tp, CPMU_PRESENT); in tg3_detect_asic_rev()
16071 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_detect_asic_rev()
16072 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_detect_asic_rev()
16073 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_detect_asic_rev()
16074 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_detect_asic_rev()
16075 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_detect_asic_rev()
16076 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_detect_asic_rev()
16077 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_detect_asic_rev()
16078 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_detect_asic_rev()
16079 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_detect_asic_rev()
16080 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_detect_asic_rev()
16081 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) in tg3_detect_asic_rev()
16083 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 || in tg3_detect_asic_rev()
16084 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 || in tg3_detect_asic_rev()
16085 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 || in tg3_detect_asic_rev()
16086 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 || in tg3_detect_asic_rev()
16087 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 || in tg3_detect_asic_rev()
16088 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795 || in tg3_detect_asic_rev()
16089 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57762 || in tg3_detect_asic_rev()
16090 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57766 || in tg3_detect_asic_rev()
16091 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57782 || in tg3_detect_asic_rev()
16092 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57786) in tg3_detect_asic_rev()
16097 pci_read_config_dword(tp->pdev, reg, &tp->pci_chip_rev_id); in tg3_detect_asic_rev()
16103 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5752_A0_HW) in tg3_detect_asic_rev()
16104 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; in tg3_detect_asic_rev()
16106 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_C0) in tg3_detect_asic_rev()
16107 tp->pci_chip_rev_id = CHIPREV_ID_5720_A0; in tg3_detect_asic_rev()
16109 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_detect_asic_rev()
16110 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_detect_asic_rev()
16111 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_detect_asic_rev()
16112 tg3_flag_set(tp, 5717_PLUS); in tg3_detect_asic_rev()
16114 if (tg3_asic_rev(tp) == ASIC_REV_57765 || in tg3_detect_asic_rev()
16115 tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_detect_asic_rev()
16116 tg3_flag_set(tp, 57765_CLASS); in tg3_detect_asic_rev()
16118 if (tg3_flag(tp, 57765_CLASS) || tg3_flag(tp, 5717_PLUS) || in tg3_detect_asic_rev()
16119 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_detect_asic_rev()
16120 tg3_flag_set(tp, 57765_PLUS); in tg3_detect_asic_rev()
16123 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_detect_asic_rev()
16124 tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_detect_asic_rev()
16125 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_detect_asic_rev()
16126 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_detect_asic_rev()
16127 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_detect_asic_rev()
16128 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_detect_asic_rev()
16129 tg3_flag(tp, 57765_PLUS)) in tg3_detect_asic_rev()
16130 tg3_flag_set(tp, 5755_PLUS); in tg3_detect_asic_rev()
16132 if (tg3_asic_rev(tp) == ASIC_REV_5780 || in tg3_detect_asic_rev()
16133 tg3_asic_rev(tp) == ASIC_REV_5714) in tg3_detect_asic_rev()
16134 tg3_flag_set(tp, 5780_CLASS); in tg3_detect_asic_rev()
16136 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_detect_asic_rev()
16137 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_detect_asic_rev()
16138 tg3_asic_rev(tp) == ASIC_REV_5906 || in tg3_detect_asic_rev()
16139 tg3_flag(tp, 5755_PLUS) || in tg3_detect_asic_rev()
16140 tg3_flag(tp, 5780_CLASS)) in tg3_detect_asic_rev()
16141 tg3_flag_set(tp, 5750_PLUS); in tg3_detect_asic_rev()
16143 if (tg3_asic_rev(tp) == ASIC_REV_5705 || in tg3_detect_asic_rev()
16144 tg3_flag(tp, 5750_PLUS)) in tg3_detect_asic_rev()
16145 tg3_flag_set(tp, 5705_PLUS); in tg3_detect_asic_rev()
16148 static bool tg3_10_100_only_device(struct tg3 *tp, in tg3_10_100_only_device() argument
16153 if ((tg3_asic_rev(tp) == ASIC_REV_5703 && in tg3_10_100_only_device()
16155 (tp->phy_flags & TG3_PHYFLG_IS_FET)) in tg3_10_100_only_device()
16158 if (ent->driver_data & TG3_DRV_DATA_FLAG_10_100_ONLY) { in tg3_10_100_only_device()
16159 if (tg3_asic_rev(tp) == ASIC_REV_5705) { in tg3_10_100_only_device()
16160 if (ent->driver_data & TG3_DRV_DATA_FLAG_5705_10_100) in tg3_10_100_only_device()
16170 static int tg3_get_invariants(struct tg3 *tp, const struct pci_device_id *ent) in tg3_get_invariants() argument
16185 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16187 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16189 /* Important! -- Make sure register accesses are byteswapped in tg3_get_invariants()
16194 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16196 tp->misc_host_ctrl |= (misc_ctrl_reg & in tg3_get_invariants()
16198 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16199 tp->misc_host_ctrl); in tg3_get_invariants()
16201 tg3_detect_asic_rev(tp, misc_ctrl_reg); in tg3_get_invariants()
16209 * will drive special cycles with non-zero data during the in tg3_get_invariants()
16212 * non-zero address during special cycles. However, only in tg3_get_invariants()
16213 * these ICH bridges are known to drive non-zero addresses in tg3_get_invariants()
16220 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A1) || in tg3_get_invariants()
16221 (tg3_chip_rev_id(tp) == CHIPREV_ID_5703_A2)) { in tg3_get_invariants()
16240 while (pci_id->vendor != 0) { in tg3_get_invariants()
16241 bridge = pci_get_device(pci_id->vendor, pci_id->device, in tg3_get_invariants()
16247 if (pci_id->rev != PCI_ANY_ID) { in tg3_get_invariants()
16248 if (bridge->revision > pci_id->rev) in tg3_get_invariants()
16251 if (bridge->subordinate && in tg3_get_invariants()
16252 (bridge->subordinate->number == in tg3_get_invariants()
16253 tp->pdev->bus->number)) { in tg3_get_invariants()
16254 tg3_flag_set(tp, ICH_WORKAROUND); in tg3_get_invariants()
16261 if (tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_get_invariants()
16273 while (pci_id->vendor != 0) { in tg3_get_invariants()
16274 bridge = pci_get_device(pci_id->vendor, in tg3_get_invariants()
16275 pci_id->device, in tg3_get_invariants()
16281 if (bridge->subordinate && in tg3_get_invariants()
16282 (bridge->subordinate->number <= in tg3_get_invariants()
16283 tp->pdev->bus->number) && in tg3_get_invariants()
16284 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16285 tp->pdev->bus->number)) { in tg3_get_invariants()
16286 tg3_flag_set(tp, 5701_DMA_BUG); in tg3_get_invariants()
16294 * DMA addresses > 40-bit. This bridge may have other additional in tg3_get_invariants()
16295 * 57xx devices behind it in some 4-port NIC designs for example. in tg3_get_invariants()
16296 * Any tg3 device found behind the bridge will also need the 40-bit in tg3_get_invariants()
16299 if (tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16300 tg3_flag_set(tp, 40BIT_DMA_BUG); in tg3_get_invariants()
16301 tp->msi_cap = tp->pdev->msi_cap; in tg3_get_invariants()
16309 if (bridge && bridge->subordinate && in tg3_get_invariants()
16310 (bridge->subordinate->number <= in tg3_get_invariants()
16311 tp->pdev->bus->number) && in tg3_get_invariants()
16312 (bridge->subordinate->busn_res.end >= in tg3_get_invariants()
16313 tp->pdev->bus->number)) { in tg3_get_invariants()
16314 tg3_flag_set(tp, 40BIT_DMA_BUG); in tg3_get_invariants()
16321 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_invariants()
16322 tg3_asic_rev(tp) == ASIC_REV_5714) in tg3_get_invariants()
16323 tp->pdev_peer = tg3_find_peer(tp); in tg3_get_invariants()
16326 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0) in tg3_get_invariants()
16328 else if (tg3_flag(tp, 57765_PLUS)) in tg3_get_invariants()
16329 tg3_flag_set(tp, HW_TSO_3); in tg3_get_invariants()
16330 else if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16331 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16332 tg3_flag_set(tp, HW_TSO_2); in tg3_get_invariants()
16333 else if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
16334 tg3_flag_set(tp, HW_TSO_1); in tg3_get_invariants()
16335 tg3_flag_set(tp, TSO_BUG); in tg3_get_invariants()
16336 if (tg3_asic_rev(tp) == ASIC_REV_5750 && in tg3_get_invariants()
16337 tg3_chip_rev_id(tp) >= CHIPREV_ID_5750_C2) in tg3_get_invariants()
16338 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16339 } else if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_get_invariants()
16340 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_get_invariants()
16341 tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) { in tg3_get_invariants()
16342 tg3_flag_set(tp, FW_TSO); in tg3_get_invariants()
16343 tg3_flag_set(tp, TSO_BUG); in tg3_get_invariants()
16344 if (tg3_asic_rev(tp) == ASIC_REV_5705) in tg3_get_invariants()
16345 tp->fw_needed = FIRMWARE_TG3TSO5; in tg3_get_invariants()
16347 tp->fw_needed = FIRMWARE_TG3TSO; in tg3_get_invariants()
16351 if (tg3_flag(tp, HW_TSO_1) || in tg3_get_invariants()
16352 tg3_flag(tp, HW_TSO_2) || in tg3_get_invariants()
16353 tg3_flag(tp, HW_TSO_3) || in tg3_get_invariants()
16354 tg3_flag(tp, FW_TSO)) { in tg3_get_invariants()
16359 tg3_flag_set(tp, TSO_CAPABLE); in tg3_get_invariants()
16361 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16362 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16363 tp->fw_needed = NULL; in tg3_get_invariants()
16366 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0) in tg3_get_invariants()
16367 tp->fw_needed = FIRMWARE_TG3; in tg3_get_invariants()
16369 if (tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_get_invariants()
16370 tp->fw_needed = FIRMWARE_TG357766; in tg3_get_invariants()
16372 tp->irq_max = 1; in tg3_get_invariants()
16374 if (tg3_flag(tp, 5750_PLUS)) { in tg3_get_invariants()
16375 tg3_flag_set(tp, SUPPORT_MSI); in tg3_get_invariants()
16376 if (tg3_chip_rev(tp) == CHIPREV_5750_AX || in tg3_get_invariants()
16377 tg3_chip_rev(tp) == CHIPREV_5750_BX || in tg3_get_invariants()
16378 (tg3_asic_rev(tp) == ASIC_REV_5714 && in tg3_get_invariants()
16379 tg3_chip_rev_id(tp) <= CHIPREV_ID_5714_A2 && in tg3_get_invariants()
16380 tp->pdev_peer == tp->pdev)) in tg3_get_invariants()
16381 tg3_flag_clear(tp, SUPPORT_MSI); in tg3_get_invariants()
16383 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16384 tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16385 tg3_flag_set(tp, 1SHOT_MSI); in tg3_get_invariants()
16388 if (tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
16389 tg3_flag_set(tp, SUPPORT_MSIX); in tg3_get_invariants()
16390 tp->irq_max = TG3_IRQ_MAX_VECS; in tg3_get_invariants()
16394 tp->txq_max = 1; in tg3_get_invariants()
16395 tp->rxq_max = 1; in tg3_get_invariants()
16396 if (tp->irq_max > 1) { in tg3_get_invariants()
16397 tp->rxq_max = TG3_RSS_MAX_NUM_QS; in tg3_get_invariants()
16398 tg3_rss_init_dflt_indir_tbl(tp, TG3_RSS_MAX_NUM_QS); in tg3_get_invariants()
16400 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16401 tg3_asic_rev(tp) == ASIC_REV_5720) in tg3_get_invariants()
16402 tp->txq_max = tp->irq_max - 1; in tg3_get_invariants()
16405 if (tg3_flag(tp, 5755_PLUS) || in tg3_get_invariants()
16406 tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16407 tg3_flag_set(tp, SHORT_DMA_BUG); in tg3_get_invariants()
16409 if (tg3_asic_rev(tp) == ASIC_REV_5719) in tg3_get_invariants()
16410 tp->dma_limit = TG3_TX_BD_DMA_MAX_4K; in tg3_get_invariants()
16412 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16413 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16414 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_get_invariants()
16415 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16416 tg3_flag_set(tp, LRG_PROD_RING_CAP); in tg3_get_invariants()
16418 if (tg3_flag(tp, 57765_PLUS) && in tg3_get_invariants()
16419 tg3_chip_rev_id(tp) != CHIPREV_ID_5719_A0) in tg3_get_invariants()
16420 tg3_flag_set(tp, USE_JUMBO_BDFLAG); in tg3_get_invariants()
16422 if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
16423 tg3_flag(tp, 5780_CLASS) || in tg3_get_invariants()
16424 tg3_flag(tp, USE_JUMBO_BDFLAG)) in tg3_get_invariants()
16425 tg3_flag_set(tp, JUMBO_CAPABLE); in tg3_get_invariants()
16427 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16430 if (pci_is_pcie(tp->pdev)) { in tg3_get_invariants()
16433 tg3_flag_set(tp, PCI_EXPRESS); in tg3_get_invariants()
16435 pcie_capability_read_word(tp->pdev, PCI_EXP_LNKCTL, &lnkctl); in tg3_get_invariants()
16437 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16438 tg3_flag_clear(tp, HW_TSO_2); in tg3_get_invariants()
16439 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16441 if (tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_get_invariants()
16442 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_get_invariants()
16443 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A0 || in tg3_get_invariants()
16444 tg3_chip_rev_id(tp) == CHIPREV_ID_57780_A1) in tg3_get_invariants()
16445 tg3_flag_set(tp, CLKREQ_BUG); in tg3_get_invariants()
16446 } else if (tg3_chip_rev_id(tp) == CHIPREV_ID_5717_A0) { in tg3_get_invariants()
16447 tg3_flag_set(tp, L1PLLPD_EN); in tg3_get_invariants()
16449 } else if (tg3_asic_rev(tp) == ASIC_REV_5785) { in tg3_get_invariants()
16454 tg3_flag_set(tp, PCI_EXPRESS); in tg3_get_invariants()
16455 } else if (!tg3_flag(tp, 5705_PLUS) || in tg3_get_invariants()
16456 tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16457 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX); in tg3_get_invariants()
16458 if (!tp->pcix_cap) { in tg3_get_invariants()
16459 dev_err(&tp->pdev->dev, in tg3_get_invariants()
16460 "Cannot find PCI-X capability, aborting\n"); in tg3_get_invariants()
16461 return -EIO; in tg3_get_invariants()
16465 tg3_flag_set(tp, PCIX_MODE); in tg3_get_invariants()
16475 !tg3_flag(tp, PCI_EXPRESS)) in tg3_get_invariants()
16476 tg3_flag_set(tp, MBOX_WRITE_REORDER); in tg3_get_invariants()
16478 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, in tg3_get_invariants()
16479 &tp->pci_cacheline_sz); in tg3_get_invariants()
16480 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16481 &tp->pci_lat_timer); in tg3_get_invariants()
16482 if (tg3_asic_rev(tp) == ASIC_REV_5703 && in tg3_get_invariants()
16483 tp->pci_lat_timer < 64) { in tg3_get_invariants()
16484 tp->pci_lat_timer = 64; in tg3_get_invariants()
16485 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, in tg3_get_invariants()
16486 tp->pci_lat_timer); in tg3_get_invariants()
16489 /* Important! -- It is critical that the PCI-X hw workaround in tg3_get_invariants()
16492 if (tg3_chip_rev(tp) == CHIPREV_5700_BX) { in tg3_get_invariants()
16496 tg3_flag_set(tp, TXD_MBOX_HWBUG); in tg3_get_invariants()
16498 /* If we are in PCI-X mode, enable register write workaround. in tg3_get_invariants()
16503 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16506 tg3_flag_set(tp, PCIX_TARGET_HWBUG); in tg3_get_invariants()
16512 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16513 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16517 pci_write_config_dword(tp->pdev, in tg3_get_invariants()
16518 tp->pdev->pm_cap + PCI_PM_CTRL, in tg3_get_invariants()
16522 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16524 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16529 tg3_flag_set(tp, PCI_HIGH_SPEED); in tg3_get_invariants()
16531 tg3_flag_set(tp, PCI_32BIT); in tg3_get_invariants()
16533 /* Chip-specific fixup from Broadcom driver */ in tg3_get_invariants()
16534 if ((tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) && in tg3_get_invariants()
16537 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg); in tg3_get_invariants()
16541 tp->read32 = tg3_read32; in tg3_get_invariants()
16542 tp->write32 = tg3_write32; in tg3_get_invariants()
16543 tp->read32_mbox = tg3_read32; in tg3_get_invariants()
16544 tp->write32_mbox = tg3_write32; in tg3_get_invariants()
16545 tp->write32_tx_mbox = tg3_write32; in tg3_get_invariants()
16546 tp->write32_rx_mbox = tg3_write32; in tg3_get_invariants()
16549 if (tg3_flag(tp, PCIX_TARGET_HWBUG)) in tg3_get_invariants()
16550 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16551 else if (tg3_asic_rev(tp) == ASIC_REV_5701 || in tg3_get_invariants()
16552 (tg3_flag(tp, PCI_EXPRESS) && in tg3_get_invariants()
16553 tg3_chip_rev_id(tp) == CHIPREV_ID_5750_A0)) { in tg3_get_invariants()
16561 tp->write32 = tg3_write_flush_reg32; in tg3_get_invariants()
16564 if (tg3_flag(tp, TXD_MBOX_HWBUG) || tg3_flag(tp, MBOX_WRITE_REORDER)) { in tg3_get_invariants()
16565 tp->write32_tx_mbox = tg3_write32_tx_mbox; in tg3_get_invariants()
16566 if (tg3_flag(tp, MBOX_WRITE_REORDER)) in tg3_get_invariants()
16567 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16570 if (tg3_flag(tp, ICH_WORKAROUND)) { in tg3_get_invariants()
16571 tp->read32 = tg3_read_indirect_reg32; in tg3_get_invariants()
16572 tp->write32 = tg3_write_indirect_reg32; in tg3_get_invariants()
16573 tp->read32_mbox = tg3_read_indirect_mbox; in tg3_get_invariants()
16574 tp->write32_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16575 tp->write32_tx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16576 tp->write32_rx_mbox = tg3_write_indirect_mbox; in tg3_get_invariants()
16578 iounmap(tp->regs); in tg3_get_invariants()
16579 tp->regs = NULL; in tg3_get_invariants()
16581 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd); in tg3_get_invariants()
16583 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd); in tg3_get_invariants()
16585 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_get_invariants()
16586 tp->read32_mbox = tg3_read32_mbox_5906; in tg3_get_invariants()
16587 tp->write32_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16588 tp->write32_tx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16589 tp->write32_rx_mbox = tg3_write32_mbox_5906; in tg3_get_invariants()
16592 if (tp->write32 == tg3_write_indirect_reg32 || in tg3_get_invariants()
16593 (tg3_flag(tp, PCIX_MODE) && in tg3_get_invariants()
16594 (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16595 tg3_asic_rev(tp) == ASIC_REV_5701))) in tg3_get_invariants()
16596 tg3_flag_set(tp, SRAM_USE_CONFIG); in tg3_get_invariants()
16606 tp->pci_fn = PCI_FUNC(tp->pdev->devfn) & 3; in tg3_get_invariants()
16607 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_invariants()
16608 tg3_flag(tp, 5780_CLASS)) { in tg3_get_invariants()
16609 if (tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16610 pci_read_config_dword(tp->pdev, in tg3_get_invariants()
16611 tp->pcix_cap + PCI_X_STATUS, in tg3_get_invariants()
16613 tp->pci_fn = val & 0x7; in tg3_get_invariants()
16615 } else if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16616 tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_get_invariants()
16617 tg3_asic_rev(tp) == ASIC_REV_5720) { in tg3_get_invariants()
16618 tg3_read_mem(tp, NIC_SRAM_CPMU_STATUS, &val); in tg3_get_invariants()
16622 if (tg3_asic_rev(tp) == ASIC_REV_5717) in tg3_get_invariants()
16623 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5717) ? 1 : 0; in tg3_get_invariants()
16625 tp->pci_fn = (val & TG3_CPMU_STATUS_FMSK_5719) >> in tg3_get_invariants()
16629 if (tg3_flag(tp, FLUSH_POSTED_WRITES)) { in tg3_get_invariants()
16630 tp->write32_tx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16631 tp->write32_rx_mbox = tg3_write_flush_reg32; in tg3_get_invariants()
16642 tg3_get_eeprom_hw_cfg(tp); in tg3_get_invariants()
16644 if (tg3_flag(tp, FW_TSO) && tg3_flag(tp, ENABLE_ASF)) { in tg3_get_invariants()
16645 tg3_flag_clear(tp, TSO_CAPABLE); in tg3_get_invariants()
16646 tg3_flag_clear(tp, TSO_BUG); in tg3_get_invariants()
16647 tp->fw_needed = NULL; in tg3_get_invariants()
16650 if (tg3_flag(tp, ENABLE_APE)) { in tg3_get_invariants()
16657 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16660 tg3_ape_lock_init(tp); in tg3_get_invariants()
16661 tp->ape_hb_interval = in tg3_get_invariants()
16665 /* Set up tp->grc_local_ctrl before calling in tg3_get_invariants()
16670 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM; in tg3_get_invariants()
16671 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16672 tg3_flag(tp, EEPROM_WRITE_PROT)) in tg3_get_invariants()
16673 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 | in tg3_get_invariants()
16676 * are no pull-up resistors on unused GPIO pins. in tg3_get_invariants()
16678 else if (tg3_asic_rev(tp) == ASIC_REV_5752) in tg3_get_invariants()
16679 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3; in tg3_get_invariants()
16681 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_get_invariants()
16682 tg3_asic_rev(tp) == ASIC_REV_57780 || in tg3_get_invariants()
16683 tg3_flag(tp, 57765_CLASS)) in tg3_get_invariants()
16684 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16686 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_get_invariants()
16687 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) { in tg3_get_invariants()
16689 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; in tg3_get_invariants()
16690 if (tg3_flag(tp, IS_NIC)) in tg3_get_invariants()
16692 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 | in tg3_get_invariants()
16696 if (tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16697 tp->grc_local_ctrl |= in tg3_get_invariants()
16701 tg3_pwrsrc_switch_to_vmain(tp); in tg3_get_invariants()
16706 if (tp->dev->mtu > ETH_DATA_LEN && !tg3_flag(tp, 5780_CLASS)) in tg3_get_invariants()
16707 tg3_flag_set(tp, JUMBO_RING_ENABLE); in tg3_get_invariants()
16710 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16711 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
16712 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || in tg3_get_invariants()
16713 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2) { in tg3_get_invariants()
16714 tg3_flag_clear(tp, WOL_SPEED_100MB); in tg3_get_invariants()
16716 tg3_flag_set(tp, WOL_SPEED_100MB); in tg3_get_invariants()
16719 if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_invariants()
16720 tp->phy_flags |= TG3_PHYFLG_IS_FET; in tg3_get_invariants()
16723 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_get_invariants()
16724 (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_get_invariants()
16725 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A0) && in tg3_get_invariants()
16726 (tg3_chip_rev_id(tp) != CHIPREV_ID_5705_A1)) || in tg3_get_invariants()
16727 (tp->phy_flags & TG3_PHYFLG_IS_FET) || in tg3_get_invariants()
16728 (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)) in tg3_get_invariants()
16729 tp->phy_flags |= TG3_PHYFLG_NO_ETH_WIRE_SPEED; in tg3_get_invariants()
16731 if (tg3_chip_rev(tp) == CHIPREV_5703_AX || in tg3_get_invariants()
16732 tg3_chip_rev(tp) == CHIPREV_5704_AX) in tg3_get_invariants()
16733 tp->phy_flags |= TG3_PHYFLG_ADC_BUG; in tg3_get_invariants()
16734 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5704_A0) in tg3_get_invariants()
16735 tp->phy_flags |= TG3_PHYFLG_5704_A0_BUG; in tg3_get_invariants()
16737 if (tg3_flag(tp, 5705_PLUS) && in tg3_get_invariants()
16738 !(tp->phy_flags & TG3_PHYFLG_IS_FET) && in tg3_get_invariants()
16739 tg3_asic_rev(tp) != ASIC_REV_5785 && in tg3_get_invariants()
16740 tg3_asic_rev(tp) != ASIC_REV_57780 && in tg3_get_invariants()
16741 !tg3_flag(tp, 57765_PLUS)) { in tg3_get_invariants()
16742 if (tg3_asic_rev(tp) == ASIC_REV_5755 || in tg3_get_invariants()
16743 tg3_asic_rev(tp) == ASIC_REV_5787 || in tg3_get_invariants()
16744 tg3_asic_rev(tp) == ASIC_REV_5784 || in tg3_get_invariants()
16745 tg3_asic_rev(tp) == ASIC_REV_5761) { in tg3_get_invariants()
16746 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 && in tg3_get_invariants()
16747 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722) in tg3_get_invariants()
16748 tp->phy_flags |= TG3_PHYFLG_JITTER_BUG; in tg3_get_invariants()
16749 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M) in tg3_get_invariants()
16750 tp->phy_flags |= TG3_PHYFLG_ADJUST_TRIM; in tg3_get_invariants()
16752 tp->phy_flags |= TG3_PHYFLG_BER_BUG; in tg3_get_invariants()
16755 if (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_get_invariants()
16756 tg3_chip_rev(tp) != CHIPREV_5784_AX) { in tg3_get_invariants()
16757 tp->phy_otp = tg3_read_otp_phycfg(tp); in tg3_get_invariants()
16758 if (tp->phy_otp == 0) in tg3_get_invariants()
16759 tp->phy_otp = TG3_OTP_DEFAULT; in tg3_get_invariants()
16762 if (tg3_flag(tp, CPMU_PRESENT)) in tg3_get_invariants()
16763 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; in tg3_get_invariants()
16765 tp->mi_mode = MAC_MI_MODE_BASE; in tg3_get_invariants()
16767 tp->coalesce_mode = 0; in tg3_get_invariants()
16768 if (tg3_chip_rev(tp) != CHIPREV_5700_AX && in tg3_get_invariants()
16769 tg3_chip_rev(tp) != CHIPREV_5700_BX) in tg3_get_invariants()
16770 tp->coalesce_mode |= HOSTCC_MODE_32BYTE; in tg3_get_invariants()
16773 if (tg3_asic_rev(tp) == ASIC_REV_5717 || in tg3_get_invariants()
16774 tg3_asic_rev(tp) == ASIC_REV_5762 || in tg3_get_invariants()
16775 tg3_chip_rev_id(tp) == CHIPREV_ID_5719_A0 || in tg3_get_invariants()
16776 tg3_chip_rev_id(tp) == CHIPREV_ID_5720_A0) { in tg3_get_invariants()
16777 tp->coalesce_mode |= HOSTCC_MODE_ATTN; in tg3_get_invariants()
16778 tp->grc_mode |= GRC_MODE_IRQ_ON_FLOW_ATTN; in tg3_get_invariants()
16781 if (tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_get_invariants()
16782 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_get_invariants()
16783 tg3_flag_set(tp, USE_PHYLIB); in tg3_get_invariants()
16785 err = tg3_mdio_init(tp); in tg3_get_invariants()
16791 if (tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_get_invariants()
16792 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_get_invariants()
16801 tw32(GRC_MODE, val | tp->grc_mode); in tg3_get_invariants()
16803 tg3_switch_clocks(tp); in tg3_get_invariants()
16811 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, in tg3_get_invariants()
16814 !tg3_flag(tp, PCIX_TARGET_HWBUG)) { in tg3_get_invariants()
16815 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5701_A0 || in tg3_get_invariants()
16816 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B0 || in tg3_get_invariants()
16817 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B2 || in tg3_get_invariants()
16818 tg3_chip_rev_id(tp) == CHIPREV_ID_5701_B5) { in tg3_get_invariants()
16825 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK; in tg3_get_invariants()
16831 tg3_flag_set(tp, PCIX_TARGET_HWBUG); in tg3_get_invariants()
16836 tg3_nvram_init(tp); in tg3_get_invariants()
16839 if (tg3_asic_rev(tp) == ASIC_REV_57766 && in tg3_get_invariants()
16840 !tg3_flag(tp, NO_NVRAM)) in tg3_get_invariants()
16841 tp->fw_needed = NULL; in tg3_get_invariants()
16846 if (tg3_asic_rev(tp) == ASIC_REV_5705 && in tg3_get_invariants()
16849 tg3_flag_set(tp, IS_5788); in tg3_get_invariants()
16851 if (!tg3_flag(tp, IS_5788) && in tg3_get_invariants()
16852 tg3_asic_rev(tp) != ASIC_REV_5700) in tg3_get_invariants()
16853 tg3_flag_set(tp, TAGGED_STATUS); in tg3_get_invariants()
16854 if (tg3_flag(tp, TAGGED_STATUS)) { in tg3_get_invariants()
16855 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD | in tg3_get_invariants()
16858 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS; in tg3_get_invariants()
16859 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, in tg3_get_invariants()
16860 tp->misc_host_ctrl); in tg3_get_invariants()
16864 if (tg3_flag(tp, ENABLE_APE)) in tg3_get_invariants()
16865 tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; in tg3_get_invariants()
16867 tp->mac_mode = 0; in tg3_get_invariants()
16869 if (tg3_10_100_only_device(tp, ent)) in tg3_get_invariants()
16870 tp->phy_flags |= TG3_PHYFLG_10_100_ONLY; in tg3_get_invariants()
16872 err = tg3_phy_probe(tp); in tg3_get_invariants()
16874 dev_err(&tp->pdev->dev, "phy probe failed, err %d\n", err); in tg3_get_invariants()
16876 tg3_mdio_fini(tp); in tg3_get_invariants()
16879 tg3_read_vpd(tp); in tg3_get_invariants()
16880 tg3_read_fw_ver(tp); in tg3_get_invariants()
16882 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { in tg3_get_invariants()
16883 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16885 if (tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_get_invariants()
16886 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16888 tp->phy_flags &= ~TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16891 /* 5700 {AX,BX} chips have a broken status block link in tg3_get_invariants()
16895 if (tg3_asic_rev(tp) == ASIC_REV_5700) in tg3_get_invariants()
16896 tg3_flag_set(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16898 tg3_flag_clear(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16901 * have to force the link status polling mechanism based in tg3_get_invariants()
16904 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL && in tg3_get_invariants()
16905 tg3_asic_rev(tp) == ASIC_REV_5701 && in tg3_get_invariants()
16906 !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES)) { in tg3_get_invariants()
16907 tp->phy_flags |= TG3_PHYFLG_USE_MI_INTERRUPT; in tg3_get_invariants()
16908 tg3_flag_set(tp, USE_LINKCHG_REG); in tg3_get_invariants()
16912 if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) in tg3_get_invariants()
16913 tg3_flag_set(tp, POLL_SERDES); in tg3_get_invariants()
16915 tg3_flag_clear(tp, POLL_SERDES); in tg3_get_invariants()
16917 if (tg3_flag(tp, ENABLE_APE) && tg3_flag(tp, ENABLE_ASF)) in tg3_get_invariants()
16918 tg3_flag_set(tp, POLL_CPMU_LINK); in tg3_get_invariants()
16920 tp->rx_offset = NET_SKB_PAD + NET_IP_ALIGN; in tg3_get_invariants()
16921 tp->rx_copy_thresh = TG3_RX_COPY_THRESHOLD; in tg3_get_invariants()
16922 if (tg3_asic_rev(tp) == ASIC_REV_5701 && in tg3_get_invariants()
16923 tg3_flag(tp, PCIX_MODE)) { in tg3_get_invariants()
16924 tp->rx_offset = NET_SKB_PAD; in tg3_get_invariants()
16926 tp->rx_copy_thresh = ~(u16)0; in tg3_get_invariants()
16930 tp->rx_std_ring_mask = TG3_RX_STD_RING_SIZE(tp) - 1; in tg3_get_invariants()
16931 tp->rx_jmb_ring_mask = TG3_RX_JMB_RING_SIZE(tp) - 1; in tg3_get_invariants()
16932 tp->rx_ret_ring_mask = tg3_rx_ret_ring_size(tp) - 1; in tg3_get_invariants()
16934 tp->rx_std_max_post = tp->rx_std_ring_mask + 1; in tg3_get_invariants()
16939 if (tg3_asic_rev(tp) == ASIC_REV_5750 || in tg3_get_invariants()
16940 tg3_asic_rev(tp) == ASIC_REV_5752 || in tg3_get_invariants()
16941 tg3_asic_rev(tp) == ASIC_REV_5755) in tg3_get_invariants()
16942 tp->rx_std_max_post = 8; in tg3_get_invariants()
16944 if (tg3_flag(tp, ASPM_WORKAROUND)) in tg3_get_invariants()
16945 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) & in tg3_get_invariants()
16951 static int tg3_get_device_address(struct tg3 *tp, u8 *addr) in tg3_get_device_address() argument
16957 if (!eth_platform_get_mac_address(&tp->pdev->dev, addr)) in tg3_get_device_address()
16960 if (tg3_flag(tp, IS_SSB_CORE)) { in tg3_get_device_address()
16961 err = ssb_gige_get_macaddr(tp->pdev, addr); in tg3_get_device_address()
16967 if (tg3_asic_rev(tp) == ASIC_REV_5704 || in tg3_get_device_address()
16968 tg3_flag(tp, 5780_CLASS)) { in tg3_get_device_address()
16971 if (tg3_nvram_lock(tp)) in tg3_get_device_address()
16974 tg3_nvram_unlock(tp); in tg3_get_device_address()
16975 } else if (tg3_flag(tp, 5717_PLUS)) { in tg3_get_device_address()
16976 if (tp->pci_fn & 1) in tg3_get_device_address()
16978 if (tp->pci_fn > 1) in tg3_get_device_address()
16980 } else if (tg3_asic_rev(tp) == ASIC_REV_5906) in tg3_get_device_address()
16984 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi); in tg3_get_device_address()
16989 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo); in tg3_get_device_address()
17000 if (!tg3_flag(tp, NO_NVRAM) && in tg3_get_device_address()
17001 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) && in tg3_get_device_address()
17002 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) { in tg3_get_device_address()
17021 return -EINVAL; in tg3_get_device_address()
17028 static u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val) in tg3_calc_dma_bndry() argument
17034 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte); in tg3_calc_dma_bndry()
17043 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_calc_dma_bndry()
17044 tg3_asic_rev(tp) != ASIC_REV_5701 && in tg3_calc_dma_bndry()
17045 !tg3_flag(tp, PCI_EXPRESS)) in tg3_calc_dma_bndry()
17058 if (tg3_flag(tp, 57765_PLUS)) { in tg3_calc_dma_bndry()
17067 * when a device tries to burst across a cache-line boundary. in tg3_calc_dma_bndry()
17070 * Unfortunately, for PCI-E there are only limited in tg3_calc_dma_bndry()
17071 * write-side controls for this, and thus for reads in tg3_calc_dma_bndry()
17077 if (tg3_flag(tp, PCIX_MODE) && !tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
17102 } else if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_calc_dma_bndry()
17169 static int tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, in tg3_do_test_dma() argument
17201 * Broadcom noted the GRC reset will also reset all sub-components. in tg3_do_test_dma()
17220 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, in tg3_do_test_dma()
17222 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val); in tg3_do_test_dma()
17224 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0); in tg3_do_test_dma()
17231 ret = -ENODEV; in tg3_do_test_dma()
17257 static int tg3_test_dma(struct tg3 *tp) in tg3_test_dma() argument
17263 buf = dma_alloc_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, in tg3_test_dma()
17266 ret = -ENOMEM; in tg3_test_dma()
17270 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) | in tg3_test_dma()
17273 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); in tg3_test_dma()
17275 if (tg3_flag(tp, 57765_PLUS)) in tg3_test_dma()
17278 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_test_dma()
17280 tp->dma_rwctrl |= 0x00180000; in tg3_test_dma()
17281 } else if (!tg3_flag(tp, PCIX_MODE)) { in tg3_test_dma()
17282 if (tg3_asic_rev(tp) == ASIC_REV_5705 || in tg3_test_dma()
17283 tg3_asic_rev(tp) == ASIC_REV_5750) in tg3_test_dma()
17284 tp->dma_rwctrl |= 0x003f0000; in tg3_test_dma()
17286 tp->dma_rwctrl |= 0x003f000f; in tg3_test_dma()
17288 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_test_dma()
17289 tg3_asic_rev(tp) == ASIC_REV_5704) { in tg3_test_dma()
17297 if (tg3_flag(tp, 40BIT_DMA_BUG) && in tg3_test_dma()
17298 tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_test_dma()
17299 tp->dma_rwctrl |= 0x8000; in tg3_test_dma()
17301 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17303 if (tg3_asic_rev(tp) == ASIC_REV_5703) in tg3_test_dma()
17306 tp->dma_rwctrl |= in tg3_test_dma()
17310 } else if (tg3_asic_rev(tp) == ASIC_REV_5780) { in tg3_test_dma()
17312 tp->dma_rwctrl |= 0x00144000; in tg3_test_dma()
17313 } else if (tg3_asic_rev(tp) == ASIC_REV_5714) { in tg3_test_dma()
17315 tp->dma_rwctrl |= 0x00148000; in tg3_test_dma()
17317 tp->dma_rwctrl |= 0x001b000f; in tg3_test_dma()
17320 if (tg3_flag(tp, ONE_DMA_AT_ONCE)) in tg3_test_dma()
17321 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA; in tg3_test_dma()
17323 if (tg3_asic_rev(tp) == ASIC_REV_5703 || in tg3_test_dma()
17324 tg3_asic_rev(tp) == ASIC_REV_5704) in tg3_test_dma()
17325 tp->dma_rwctrl &= 0xfffffff0; in tg3_test_dma()
17327 if (tg3_asic_rev(tp) == ASIC_REV_5700 || in tg3_test_dma()
17328 tg3_asic_rev(tp) == ASIC_REV_5701) { in tg3_test_dma()
17330 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT; in tg3_test_dma()
17340 * on those chips to enable a PCI-X workaround. in tg3_test_dma()
17342 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE; in tg3_test_dma()
17345 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17348 if (tg3_asic_rev(tp) != ASIC_REV_5700 && in tg3_test_dma()
17349 tg3_asic_rev(tp) != ASIC_REV_5701) in tg3_test_dma()
17355 saved_dma_rwctrl = tp->dma_rwctrl; in tg3_test_dma()
17356 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17357 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17366 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, true); in tg3_test_dma()
17368 dev_err(&tp->pdev->dev, in tg3_test_dma()
17375 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, false); in tg3_test_dma()
17377 dev_err(&tp->pdev->dev, "%s: Buffer read failed. " in tg3_test_dma()
17387 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17389 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17390 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17391 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17394 dev_err(&tp->pdev->dev, in tg3_test_dma()
17397 ret = -ENODEV; in tg3_test_dma()
17408 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) != in tg3_test_dma()
17415 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK; in tg3_test_dma()
17416 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16; in tg3_test_dma()
17419 tp->dma_rwctrl = saved_dma_rwctrl; in tg3_test_dma()
17422 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl); in tg3_test_dma()
17426 dma_free_coherent(&tp->pdev->dev, TEST_BUFFER_SIZE, buf, buf_dma); in tg3_test_dma()
17431 static void tg3_init_bufmgr_config(struct tg3 *tp) in tg3_init_bufmgr_config() argument
17433 if (tg3_flag(tp, 57765_PLUS)) { in tg3_init_bufmgr_config()
17434 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17436 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17438 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17441 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17443 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17445 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17447 } else if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_bufmgr_config()
17448 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17450 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17452 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17454 if (tg3_asic_rev(tp) == ASIC_REV_5906) { in tg3_init_bufmgr_config()
17455 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17457 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17461 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17463 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17465 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17468 tp->bufmgr_config.mbuf_read_dma_low_water = in tg3_init_bufmgr_config()
17470 tp->bufmgr_config.mbuf_mac_rx_low_water = in tg3_init_bufmgr_config()
17472 tp->bufmgr_config.mbuf_high_water = in tg3_init_bufmgr_config()
17475 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = in tg3_init_bufmgr_config()
17477 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = in tg3_init_bufmgr_config()
17479 tp->bufmgr_config.mbuf_high_water_jumbo = in tg3_init_bufmgr_config()
17483 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; in tg3_init_bufmgr_config()
17484 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; in tg3_init_bufmgr_config()
17487 static char *tg3_phy_string(struct tg3 *tp) in tg3_phy_string() argument
17489 switch (tp->phy_id & TG3_PHY_ID_MASK) { in tg3_phy_string()
17519 static char *tg3_bus_string(struct tg3 *tp, char *str) in tg3_bus_string() argument
17521 if (tg3_flag(tp, PCI_EXPRESS)) { in tg3_bus_string()
17524 } else if (tg3_flag(tp, PCIX_MODE)) { in tg3_bus_string()
17543 if (tg3_flag(tp, PCI_HIGH_SPEED)) in tg3_bus_string()
17548 if (tg3_flag(tp, PCI_32BIT)) in tg3_bus_string()
17549 strcat(str, ":32-bit"); in tg3_bus_string()
17551 strcat(str, ":64-bit"); in tg3_bus_string()
17555 static void tg3_init_coal(struct tg3 *tp) in tg3_init_coal() argument
17557 struct ethtool_coalesce *ec = &tp->coal; in tg3_init_coal()
17560 ec->cmd = ETHTOOL_GCOALESCE; in tg3_init_coal()
17561 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS; in tg3_init_coal()
17562 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS; in tg3_init_coal()
17563 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES; in tg3_init_coal()
17564 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES; in tg3_init_coal()
17565 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT; in tg3_init_coal()
17566 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT; in tg3_init_coal()
17567 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT; in tg3_init_coal()
17568 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT; in tg3_init_coal()
17569 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS; in tg3_init_coal()
17571 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD | in tg3_init_coal()
17573 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17574 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17575 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS; in tg3_init_coal()
17576 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS; in tg3_init_coal()
17579 if (tg3_flag(tp, 5705_PLUS)) { in tg3_init_coal()
17580 ec->rx_coalesce_usecs_irq = 0; in tg3_init_coal()
17581 ec->tx_coalesce_usecs_irq = 0; in tg3_init_coal()
17582 ec->stats_block_coalesce_usecs = 0; in tg3_init_coal()
17590 struct tg3 *tp; in tg3_init_one() local
17600 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); in tg3_init_one()
17606 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); in tg3_init_one()
17612 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS); in tg3_init_one()
17614 err = -ENOMEM; in tg3_init_one()
17618 SET_NETDEV_DEV(dev, &pdev->dev); in tg3_init_one()
17620 tp = netdev_priv(dev); in tg3_init_one()
17621 tp->pdev = pdev; in tg3_init_one()
17622 tp->dev = dev; in tg3_init_one()
17623 tp->rx_mode = TG3_DEF_RX_MODE; in tg3_init_one()
17624 tp->tx_mode = TG3_DEF_TX_MODE; in tg3_init_one()
17625 tp->irq_sync = 1; in tg3_init_one()
17626 tp->pcierr_recovery = false; in tg3_init_one()
17629 tp->msg_enable = tg3_debug; in tg3_init_one()
17631 tp->msg_enable = TG3_DEF_MSG_ENABLE; in tg3_init_one()
17634 tg3_flag_set(tp, IS_SSB_CORE); in tg3_init_one()
17636 tg3_flag_set(tp, FLUSH_POSTED_WRITES); in tg3_init_one()
17638 tg3_flag_set(tp, ONE_DMA_AT_ONCE); in tg3_init_one()
17640 tg3_flag_set(tp, USE_PHYLIB); in tg3_init_one()
17641 tg3_flag_set(tp, ROBOSWITCH); in tg3_init_one()
17644 tg3_flag_set(tp, RGMII_MODE); in tg3_init_one()
17651 tp->misc_host_ctrl = in tg3_init_one()
17657 /* The NONFRM (non-frame) byte/word swap controls take effect in tg3_init_one()
17661 * are running in big-endian mode. in tg3_init_one()
17663 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA | in tg3_init_one()
17666 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA; in tg3_init_one()
17668 spin_lock_init(&tp->lock); in tg3_init_one()
17669 spin_lock_init(&tp->indirect_lock); in tg3_init_one()
17670 INIT_WORK(&tp->reset_task, tg3_reset_task); in tg3_init_one()
17672 tp->regs = pci_ioremap_bar(pdev, BAR_0); in tg3_init_one()
17673 if (!tp->regs) { in tg3_init_one()
17674 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); in tg3_init_one()
17675 err = -ENOMEM; in tg3_init_one()
17679 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 || in tg3_init_one()
17680 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761E || in tg3_init_one()
17681 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S || in tg3_init_one()
17682 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761SE || in tg3_init_one()
17683 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 || in tg3_init_one()
17684 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717_C || in tg3_init_one()
17685 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 || in tg3_init_one()
17686 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5719 || in tg3_init_one()
17687 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5720 || in tg3_init_one()
17688 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57767 || in tg3_init_one()
17689 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57764 || in tg3_init_one()
17690 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5762 || in tg3_init_one()
17691 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5725 || in tg3_init_one()
17692 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5727 || in tg3_init_one()
17693 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57787) { in tg3_init_one()
17694 tg3_flag_set(tp, ENABLE_APE); in tg3_init_one()
17695 tp->aperegs = pci_ioremap_bar(pdev, BAR_2); in tg3_init_one()
17696 if (!tp->aperegs) { in tg3_init_one()
17697 dev_err(&pdev->dev, in tg3_init_one()
17699 err = -ENOMEM; in tg3_init_one()
17704 tp->rx_pending = TG3_DEF_RX_RING_PENDING; in tg3_init_one()
17705 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; in tg3_init_one()
17707 dev->ethtool_ops = &tg3_ethtool_ops; in tg3_init_one()
17708 dev->watchdog_timeo = TG3_TX_TIMEOUT; in tg3_init_one()
17709 dev->netdev_ops = &tg3_netdev_ops; in tg3_init_one()
17710 dev->irq = pdev->irq; in tg3_init_one()
17712 err = tg3_get_invariants(tp, ent); in tg3_init_one()
17714 dev_err(&pdev->dev, in tg3_init_one()
17720 * device behind the EPB cannot support DMA addresses > 40-bit. in tg3_init_one()
17721 * On 64-bit systems with IOMMU, use 40-bit dma_mask. in tg3_init_one()
17722 * On 64-bit systems without IOMMU, use 64-bit dma_mask and in tg3_init_one()
17725 if (tg3_flag(tp, IS_5788)) in tg3_init_one()
17727 else if (tg3_flag(tp, 40BIT_DMA_BUG)) { in tg3_init_one()
17735 if (tg3_asic_rev(tp) == ASIC_REV_57766) in tg3_init_one()
17740 err = dma_set_mask(&pdev->dev, dma_mask); in tg3_init_one()
17743 err = dma_set_coherent_mask(&pdev->dev, in tg3_init_one()
17746 dev_err(&pdev->dev, "Unable to obtain 64 bit " in tg3_init_one()
17753 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); in tg3_init_one()
17755 dev_err(&pdev->dev, in tg3_init_one()
17761 tg3_init_bufmgr_config(tp); in tg3_init_one()
17766 if (tg3_chip_rev_id(tp) != CHIPREV_ID_5700_B0) { in tg3_init_one()
17769 if (tg3_flag(tp, 5755_PLUS)) in tg3_init_one()
17777 if ((tg3_flag(tp, HW_TSO_1) || in tg3_init_one()
17778 tg3_flag(tp, HW_TSO_2) || in tg3_init_one()
17779 tg3_flag(tp, HW_TSO_3)) && in tg3_init_one()
17782 if (tg3_flag(tp, HW_TSO_2) || tg3_flag(tp, HW_TSO_3)) { in tg3_init_one()
17785 if (tg3_flag(tp, HW_TSO_3) || in tg3_init_one()
17786 tg3_asic_rev(tp) == ASIC_REV_5761 || in tg3_init_one()
17787 (tg3_asic_rev(tp) == ASIC_REV_5784 && in tg3_init_one()
17788 tg3_chip_rev(tp) != CHIPREV_5784_AX) || in tg3_init_one()
17789 tg3_asic_rev(tp) == ASIC_REV_5785 || in tg3_init_one()
17790 tg3_asic_rev(tp) == ASIC_REV_57780) in tg3_init_one()
17794 dev->features |= features | NETIF_F_HW_VLAN_CTAG_TX | in tg3_init_one()
17796 dev->vlan_features |= features; in tg3_init_one()
17800 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY in tg3_init_one()
17803 if (tg3_asic_rev(tp) != ASIC_REV_5780 && in tg3_init_one()
17804 !tg3_flag(tp, CPMU_PRESENT)) in tg3_init_one()
17808 dev->hw_features |= features; in tg3_init_one()
17809 dev->priv_flags |= IFF_UNICAST_FLT; in tg3_init_one()
17811 /* MTU range: 60 - 9000 or 1500, depending on hardware */ in tg3_init_one()
17812 dev->min_mtu = TG3_MIN_MTU; in tg3_init_one()
17813 dev->max_mtu = TG3_MAX_MTU(tp); in tg3_init_one()
17815 if (tg3_chip_rev_id(tp) == CHIPREV_ID_5705_A1 && in tg3_init_one()
17816 !tg3_flag(tp, TSO_CAPABLE) && in tg3_init_one()
17818 tg3_flag_set(tp, MAX_RXPEND_64); in tg3_init_one()
17819 tp->rx_pending = 63; in tg3_init_one()
17822 err = tg3_get_device_address(tp, addr); in tg3_init_one()
17824 dev_err(&pdev->dev, in tg3_init_one()
17833 for (i = 0; i < tp->irq_max; i++) { in tg3_init_one()
17834 struct tg3_napi *tnapi = &tp->napi[i]; in tg3_init_one()
17836 tnapi->tp = tp; in tg3_init_one()
17837 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING; in tg3_init_one()
17839 tnapi->int_mbox = intmbx; in tg3_init_one()
17842 tnapi->consmbox = rcvmbx; in tg3_init_one()
17843 tnapi->prodmbox = sndmbx; in tg3_init_one()
17846 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1); in tg3_init_one()
17848 tnapi->coal_now = HOSTCC_MODE_NOW; in tg3_init_one()
17850 if (!tg3_flag(tp, SUPPORT_MSIX)) in tg3_init_one()
17855 * RSS, the first vector only handles link interrupts and the in tg3_init_one()
17866 sndmbx -= 0x4; in tg3_init_one()
17878 tg3_full_lock(tp, 0); in tg3_init_one()
17880 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_init_one()
17881 tg3_full_unlock(tp); in tg3_init_one()
17884 err = tg3_test_dma(tp); in tg3_init_one()
17886 dev_err(&pdev->dev, "DMA engine test failed, aborting\n"); in tg3_init_one()
17890 tg3_init_coal(tp); in tg3_init_one()
17894 if (tg3_asic_rev(tp) == ASIC_REV_5719 || in tg3_init_one()
17895 tg3_asic_rev(tp) == ASIC_REV_5720 || in tg3_init_one()
17896 tg3_asic_rev(tp) == ASIC_REV_5762) in tg3_init_one()
17897 tg3_flag_set(tp, PTP_CAPABLE); in tg3_init_one()
17899 tg3_timer_init(tp); in tg3_init_one()
17901 tg3_carrier_off(tp); in tg3_init_one()
17905 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); in tg3_init_one()
17909 if (tg3_flag(tp, PTP_CAPABLE)) { in tg3_init_one()
17910 tg3_ptp_init(tp); in tg3_init_one()
17911 tp->ptp_clock = ptp_clock_register(&tp->ptp_info, in tg3_init_one()
17912 &tp->pdev->dev); in tg3_init_one()
17913 if (IS_ERR(tp->ptp_clock)) in tg3_init_one()
17914 tp->ptp_clock = NULL; in tg3_init_one()
17918 tp->board_part_number, in tg3_init_one()
17919 tg3_chip_rev_id(tp), in tg3_init_one()
17920 tg3_bus_string(tp, str), in tg3_init_one()
17921 dev->dev_addr); in tg3_init_one()
17923 if (!(tp->phy_flags & TG3_PHYFLG_IS_CONNECTED)) { in tg3_init_one()
17926 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY) in tg3_init_one()
17927 ethtype = "10/100Base-TX"; in tg3_init_one()
17928 else if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES) in tg3_init_one()
17929 ethtype = "1000Base-SX"; in tg3_init_one()
17931 ethtype = "10/100/1000Base-T"; in tg3_init_one()
17935 tg3_phy_string(tp), ethtype, in tg3_init_one()
17936 (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED) == 0, in tg3_init_one()
17937 (tp->phy_flags & TG3_PHYFLG_EEE_CAP) != 0); in tg3_init_one()
17941 (dev->features & NETIF_F_RXCSUM) != 0, in tg3_init_one()
17942 tg3_flag(tp, USE_LINKCHG_REG) != 0, in tg3_init_one()
17943 (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT) != 0, in tg3_init_one()
17944 tg3_flag(tp, ENABLE_ASF) != 0, in tg3_init_one()
17945 tg3_flag(tp, TSO_CAPABLE) != 0); in tg3_init_one()
17946 netdev_info(dev, "dma_rwctrl[%08x] dma_mask[%d-bit]\n", in tg3_init_one()
17947 tp->dma_rwctrl, in tg3_init_one()
17948 pdev->dma_mask == DMA_BIT_MASK(32) ? 32 : in tg3_init_one()
17949 ((u64)pdev->dma_mask) == DMA_BIT_MASK(40) ? 40 : 64); in tg3_init_one()
17956 if (tp->aperegs) { in tg3_init_one()
17957 iounmap(tp->aperegs); in tg3_init_one()
17958 tp->aperegs = NULL; in tg3_init_one()
17962 if (tp->regs) { in tg3_init_one()
17963 iounmap(tp->regs); in tg3_init_one()
17964 tp->regs = NULL; in tg3_init_one()
17984 struct tg3 *tp = netdev_priv(dev); in tg3_remove_one() local
17986 tg3_ptp_fini(tp); in tg3_remove_one()
17988 release_firmware(tp->fw); in tg3_remove_one()
17990 tg3_reset_task_cancel(tp); in tg3_remove_one()
17992 if (tg3_flag(tp, USE_PHYLIB)) { in tg3_remove_one()
17993 tg3_phy_fini(tp); in tg3_remove_one()
17994 tg3_mdio_fini(tp); in tg3_remove_one()
17998 if (tp->aperegs) { in tg3_remove_one()
17999 iounmap(tp->aperegs); in tg3_remove_one()
18000 tp->aperegs = NULL; in tg3_remove_one()
18002 if (tp->regs) { in tg3_remove_one()
18003 iounmap(tp->regs); in tg3_remove_one()
18004 tp->regs = NULL; in tg3_remove_one()
18016 struct tg3 *tp = netdev_priv(dev); in tg3_suspend() local
18024 tg3_reset_task_cancel(tp); in tg3_suspend()
18025 tg3_phy_stop(tp); in tg3_suspend()
18026 tg3_netif_stop(tp); in tg3_suspend()
18028 tg3_timer_stop(tp); in tg3_suspend()
18030 tg3_full_lock(tp, 1); in tg3_suspend()
18031 tg3_disable_ints(tp); in tg3_suspend()
18032 tg3_full_unlock(tp); in tg3_suspend()
18036 tg3_full_lock(tp, 0); in tg3_suspend()
18037 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1); in tg3_suspend()
18038 tg3_flag_clear(tp, INIT_COMPLETE); in tg3_suspend()
18039 tg3_full_unlock(tp); in tg3_suspend()
18041 err = tg3_power_down_prepare(tp); in tg3_suspend()
18045 tg3_full_lock(tp, 0); in tg3_suspend()
18047 tg3_flag_set(tp, INIT_COMPLETE); in tg3_suspend()
18048 err2 = tg3_restart_hw(tp, true); in tg3_suspend()
18052 tg3_timer_start(tp); in tg3_suspend()
18055 tg3_netif_start(tp); in tg3_suspend()
18058 tg3_full_unlock(tp); in tg3_suspend()
18061 tg3_phy_start(tp); in tg3_suspend()
18072 struct tg3 *tp = netdev_priv(dev); in tg3_resume() local
18082 tg3_full_lock(tp, 0); in tg3_resume()
18084 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_resume()
18086 tg3_flag_set(tp, INIT_COMPLETE); in tg3_resume()
18087 err = tg3_restart_hw(tp, in tg3_resume()
18088 !(tp->phy_flags & TG3_PHYFLG_KEEP_LINK_ON_PWRDN)); in tg3_resume()
18092 tg3_timer_start(tp); in tg3_resume()
18094 tg3_netif_start(tp); in tg3_resume()
18097 tg3_full_unlock(tp); in tg3_resume()
18100 tg3_phy_start(tp); in tg3_resume()
18157 struct tg3 *tp = netdev_priv(dev); in tg3_shutdown() local
18159 tg3_reset_task_cancel(tp); in tg3_shutdown()
18169 tg3_power_down(tp); in tg3_shutdown()
18172 pdev->current_state != PCI_D3cold && in tg3_shutdown()
18173 pdev->current_state != PCI_UNKNOWN) { in tg3_shutdown()
18190 * tg3_io_error_detected - called when PCI error is detected
18201 struct tg3 *tp = netdev_priv(netdev); in tg3_io_error_detected() local
18207 tg3_reset_task_cancel(tp); in tg3_io_error_detected()
18212 if (!netdev || tp->pcierr_recovery || !netif_running(netdev)) in tg3_io_error_detected()
18217 tp->pcierr_recovery = true; in tg3_io_error_detected()
18219 tg3_phy_stop(tp); in tg3_io_error_detected()
18221 tg3_netif_stop(tp); in tg3_io_error_detected()
18223 tg3_timer_stop(tp); in tg3_io_error_detected()
18228 tg3_full_lock(tp, 0); in tg3_io_error_detected()
18229 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0); in tg3_io_error_detected()
18230 tg3_full_unlock(tp); in tg3_io_error_detected()
18235 tg3_napi_enable(tp); in tg3_io_error_detected()
18249 * tg3_io_slot_reset - called after the pci bus has been reset.
18252 * Restart the card from scratch, as if from a cold-boot.
18260 struct tg3 *tp = netdev_priv(netdev); in tg3_io_slot_reset() local
18267 dev_err(&pdev->dev, in tg3_io_slot_reset()
18268 "Cannot re-enable PCI device after reset.\n"); in tg3_io_slot_reset()
18281 err = tg3_power_up(tp); in tg3_io_slot_reset()
18289 tg3_napi_enable(tp); in tg3_io_slot_reset()
18298 * tg3_io_resume - called when traffic can start flowing again.
18307 struct tg3 *tp = netdev_priv(netdev); in tg3_io_resume() local
18315 tg3_full_lock(tp, 0); in tg3_io_resume()
18316 tg3_ape_driver_state_change(tp, RESET_KIND_INIT); in tg3_io_resume()
18317 tg3_flag_set(tp, INIT_COMPLETE); in tg3_io_resume()
18318 err = tg3_restart_hw(tp, true); in tg3_io_resume()
18320 tg3_full_unlock(tp); in tg3_io_resume()
18327 tg3_timer_start(tp); in tg3_io_resume()
18329 tg3_netif_start(tp); in tg3_io_resume()
18331 tg3_full_unlock(tp); in tg3_io_resume()
18333 tg3_phy_start(tp); in tg3_io_resume()
18336 tp->pcierr_recovery = false; in tg3_io_resume()