Lines Matching +full:dp +full:- +full:phy1
3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
67 * is de-asserted */
75 * is de-asserted */
82 * port is de-asserted */
85 interface #n is de-asserted. */
98 interface #n is de-asserted. */
151 * is de-asserted */
159 * is de-asserted */
162 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
167 /* [RW 1] Indicates if to use per-class guaranty mode (new mode) or per-MAC
168 * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC
169 * mode). 1=per-class guaranty mode (new mode). */
177 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
179 if 1 - normal activity. */
181 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
183 if 1 - normal activity. */
198 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
199 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
200 Is used to determine the number of the AG context REG-pairs written back;
203 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
205 if 1 - normal activity. */
207 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
209 if 1 - normal activity. */
211 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
213 usual; if 1 - normal activity. */
215 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
216 are disregarded; all other signals are treated as usual; if 1 - normal
219 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
221 usual; if 1 - normal activity. */
223 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
224 input is disregarded; all other signals are treated as usual; if 1 -
227 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
229 counter. Must be initialized to 1 at start-up. */
239 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
241 if 1 - normal activity. */
243 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
245 counter. Must be initialized to 32 at start-up. */
255 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
257 if 1 - normal activity. */
271 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
273 credit counter. Must be initialized to 64 at start-up. */
275 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
277 credit counter. Must be initialized to 64 at start-up. */
279 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
280 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
287 the complement to 4 of the rest priorities - Aggregation channel; Load
292 the complement to 4 of the rest priorities - Aggregation channel; Load
297 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
299 REG-pairs are used in order to align to STORM context row size of 128
307 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
309 if 1 - normal activity. */
332 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
334 treated as usual; if 1 - normal activity. */
344 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
346 treated as usual; if 1 - normal activity. */
355 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
357 treated as usual; if 1 - normal activity. */
366 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
368 treated as usual; if 1 - normal activity. */
378 mechanism. The fields are: [5:0] - message length; [12:6] - message
379 pointer; 18:13] - next pointer. */
386 messages. Max credit available - 127. Write writes the initial credit
388 initialized to maximum XX protected message size - 2 at start-up. */
398 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
449 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
466 field allows changing the priorities of the weighted-round-robin arbiter
500 or auto-mask-mode (1) */
586 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
587 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
590 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
591 sleeping thread with priority 1; 4- sleeping thread with priority 2.
595 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
596 sleeping thread with priority 1; 4- sleeping thread with priority 2.
601 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
602 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
608 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
609 sleeping thread with priority 1; 4- sleeping thread with priority 2.
669 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
715 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
716 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
725 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
732 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
735 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
736 CRC-16 T10 initial value is all ones. */
778 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
780 as usual; if 1 - normal activity. */
782 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
784 all other signals are treated as usual; if 1 - normal activity. */
786 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
823 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
928 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
929 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
937 * command. Data valid only in addresses 0-4. all the rest are zero. */
953 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
954 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
955 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
965 * done was not received. Data valid only in addresses 0-4. all the rest are
969 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
970 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default
971 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod;
972 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode
973 * - In backward compatible mode; for non default SB; each even line in the
975 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
977 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
978 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; */
983 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
984 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3
985 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; */
998 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
999 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per
1000 * PF; 68-71 number of ATTN messages per PF */
1009 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
1146 * CNIG attention (reserved); [7] CNIG parity (reserved); [31-8] Reserved; */
1417 * parity; [31-10] Reserved; */
1423 * parity; [31-10] Reserved; */
1495 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1501 starts at 0x0 for the A0 tape-out and increments by one for each
1502 all-layer tape-out. */
1504 /* [R 14] otp_misc_do[100:0] spare bits collection: 13:11-
1505 * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72];
1506 * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */
1517 /* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that
1519 * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that
1521 * that the FW command that all Queues are empty is enabled. [2] - FW Early
1525 * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication
1527 * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF
1529 * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1
1533 * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that
1535 * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the
1537 * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM
1539 * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When
1541 * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1
1545 * bit masks the falling edge detect of the L1 status (L1 is on - off). [11]
1546 * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE
1548 * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1
1550 * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE
1553 * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
1555 * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1
1557 * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates
1559 * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status
1560 * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This
1561 * bit is applicable only in the EXIT Events Masks registers. [17] - L1
1563 * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off).
1565 * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in
1568 /* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates
1570 * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates
1572 * indicates that the FW command that all Queues are empty is enabled. [2] -
1576 * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request
1578 * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other
1580 * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status
1584 * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1
1586 * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1
1588 * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1
1591 * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for
1593 * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1
1597 * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When
1599 * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1
1602 * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE
1604 * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates
1606 * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1
1608 * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask.
1610 * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that
1612 * LPI is on - off). This bit is applicable only in the EXIT Events Masks
1613 * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the
1615 * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge
1616 * Detect indication from the PCIE CORE is enabled (L1 is on - off). This
1651 /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1653 is 1 - the path_swap output is equal to bit[1] of this register; [1] -
1659 /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1661 is 1 - the port_swap output is equal to bit[1] of this register; [1] -
1675 set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON.
1676 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1680 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1685 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1688 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1692 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1702 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a
1705 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1708 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1714 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1721 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1722 [27:24] the master that caused the attention - according to the following
1727 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1728 [27:24] the master that caused the attention - according to the following
1740 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1773 /* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR
1812 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1813 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 -
1814 * the port4mode_en output is equal to bit[1] of this register; [1] -
1819 write/read zero = the specific block is in reset; addr 0-wr- the write
1820 value will be written to the register; addr 1-set - one will be written
1822 have the value of zero will not be change) ; addr 2-clear - zero will be
1824 (bits that have the value of zero will not be change); addr 3-ignore;
1834 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1837 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1841 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1844 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1848 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1855 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1858 field is not applicable for this pin; only the VALUE fields is relevant -
1867 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1870 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1872 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1877 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1887 /* [RW 32] the value of the counter for sw timers1-8. there are 8 addresses
1888 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
1893 /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1895 - the path_swap output is equal to bit[1] of this register; [1] -
1900 loaded; 0-prepare; -unprepare */
1916 This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 -
1917 Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap
1922 Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode;
1923 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the
1964 72:73]-vnic_num; 81:74]-sideband_info */
1968 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1975 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
2007 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
2035 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
2058 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
2059 9-11PHY7; 12 MAC4; 13-15 PHY10; */
2061 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1-
2062 tsdm enable; b2- usdm enable */
2070 /* [RW 16] classes are high-priority for port0 */
2073 /* [RW 16] classes are low-priority for port0 */
2107 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
2142 /* [RW 16] Outer VLAN type identifier for multi-function mode. In non
2143 * multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
2182 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2191 /* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
2197 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2201 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2207 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2208 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2209 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2210 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2211 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2216 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2217 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2218 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2219 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2220 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2221 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2222 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
2224 * Note that rules 4-7 are for IPv6 packets only and require that the packet
2236 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2238 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2239 * priority field is extracted from the outer-most VLAN in receive packet.
2253 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2258 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2263 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2268 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A
2273 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A
2278 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A
2286 * clients that are not subject to WFQ credit blocking - their
2290 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2292 * subject to WFQ credit blocking - their specifications here are not used.
2295 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2296 * use credit registers 0-5 respectively (0x543210876). Note that credit
2300 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2302 * subject to WFQ credit blocking - their specifications here are not used.
2305 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2306 * use credit registers 0-5 respectively (0x543210876). Note that credit
2312 * strict priorities for clients 0-2 -- management and debug traffic. */
2342 * two round-robin arbitration slots to avoid starvation. A value of 0 means
2343 * no strict priority cycles - the strict priority with anti-starvation
2344 * arbiter becomes a round-robin arbiter. */
2349 * clients are assigned the following IDs: 0-management; 1-debug traffic
2350 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2355 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2360 /* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
2366 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2370 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2376 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2377 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2378 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2379 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2380 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2385 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2386 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2387 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2388 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2389 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2390 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2391 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
2393 * Note that rules 4-7 are for IPv6 packets only and require that the packet
2400 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2402 * client; bits [35-32] are for priority 8 client. The clients are assigned
2403 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2404 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2405 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2410 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2412 * client; bits [35-32] are for priority 8 client. The clients are assigned
2413 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2414 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2415 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2419 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
2421 * packets from MCP are forwarded to the network when this bit is cleared -
2423 * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter
2434 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2436 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2437 * priority field is extracted from the outer-most VLAN in receive packet.
2451 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2456 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A
2461 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A
2470 /* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
2478 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2482 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2488 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2489 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2490 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2491 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2492 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2497 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2498 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2499 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2500 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2501 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2502 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2506 /* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
2514 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2518 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
2524 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2525 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2526 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2527 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2528 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2533 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2534 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2535 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2536 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2537 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2538 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2543 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2545 * subject to WFQ credit blocking - their specifications here are not used.
2548 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2549 * use credit registers 0-5 respectively (0x543210876). Note that credit
2551 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2552 * credit registers 0-5 are valid. This register should be configured
2556 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2558 * subject to WFQ credit blocking - their specifications here are not used.
2561 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2562 * use credit registers 0-5 respectively (0x543210876). Note that credit
2564 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only
2565 * credit registers 0-5 are valid. This register should be configured
2570 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2571 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1
2572 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic.
2577 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2578 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2
2579 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is
2597 two round-robin arbitration slots to avoid starvation. A value of 0 means
2598 no strict priority cycles - the strict priority with anti-starvation
2599 arbiter becomes a round-robin arbiter. */
2602 strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2604 client; bits [35-32] are for priority 8 client. The clients are assigned
2605 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2606 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2607 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2610 is the same as the one for port 0, except that port 1 only has COS 0-2
2611 traffic. There is no traffic for COS 3-5 of port 1. */
2614 strict priority arbiter. This register specifies bits 35:32 of the 36-bit
2616 client; bits [35-32] are for priority 8 client. The clients are assigned
2617 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2618 traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic;
2619 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2622 is the same as the one for port 0, except that port 1 only has COS 0-2
2623 traffic. There is no traffic for COS 3-5 of port 1. */
2627 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP
2629 * packets from MCP are forwarded to the network when this bit is cleared -
2657 /* [RW 5] control to serdes - CL45 DEVAD */
2659 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2661 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
2695 * generator sub-module.
2702 /* [RW 1] control to xgxs - remote PHY in-band MDIO */
2704 /* [RW 5] control to xgxs - CL45 DEVAD */
2706 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2708 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
2788 * lowest priority in the strict-priority arbiter. */
2793 * lowest priority in the strict-priority arbiter. */
2803 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2808 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR
2812 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2817 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2822 * arbiter. If reset strict priority w/ anti-starvation will be performed
2825 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
2828 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2830 /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest
2874 /* [RW 6] Bit-map indicating which headers must appear in the packet */
2878 * strict-priority w/ anti-starvation arbiter is a RR arbiter. */
2891 /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2893 /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
2895 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2900 /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port
2903 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2909 /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */
2911 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2924 /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */
2926 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines
2997 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2998 * - enable. */
3000 /* [RW 18] Type B VF inbound interrupt table for CSDM: bits[17:9]-mask;
3001 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
3003 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
3004 * - enable. */
3012 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3041 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
3042 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW
3043 * arrived with a correctable error. Bit 3 - Configuration RW arrived with
3044 * an uncorrectable error. Bit 4 - Completion with Configuration Request
3045 * Retry Status. Bit 5 - Expansion ROM access received with a write request.
3046 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and
3047 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010;
3055 * details register and enables logging new error details. Bit 0 - clears
3056 * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears
3059 * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 -
3060 * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears
3061 * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6
3062 * - clears TCPL_IN_TWO_RCBS_DETAILS. */
3075 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
3076 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
3077 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 -
3078 * completer abort. 3 - Illegal value for this field. [12] valid - indicates
3083 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
3084 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
3085 * unsupported request. 2 - completer abort. 3 - Illegal value for this
3086 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a
3089 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
3092 * work-around is needed. Note: register contains bits from both paths. */
3100 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
3101 * completion did not return yet. 1 - tag is unused. Same functionality as
3102 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
3104 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
3105 * - enable. */
3113 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3120 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request.
3121 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] -
3125 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
3126 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
3127 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
3128 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
3137 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25]
3138 * - VFID. */
3141 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type -
3142 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared;
3143 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent
3144 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid -
3148 /* [RW 10] Type A PF/VF inbound interrupt table for USDM: bits[9:5]-mask;
3149 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
3158 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
3159 * - enable. */
3161 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
3162 * - enable. */
3164 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
3165 * - enable. */
3173 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3176 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
3177 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a
3184 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30]
3185 * valid - indicates if there was a request with length violation since the
3235 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
3236 * - enable. */
3244 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3289 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
3291 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
3308 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3311 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic
3315 /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
3317 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
3323 /* [RW 6] Bit-map indicating which headers must appear in the packet */
3325 /* [RW 6] Bit-map indicating which headers must appear in the packet for
3330 /* [RW 8] The 8-bit event ID for cases where there is no match on the
3431 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
3432 its[15:0]-address */
3441 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
3442 its[15:0]-address */
3451 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
3452 its[15:0]-address */
3461 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
3462 its[15:0]-address */
3550 /* [R 8] Debug only: The blocks counter - number of unused block ids */
3595 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
3599 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
3676 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
3732 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
3733 -128k */
3744 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3745 * aligned. 4 - 512B aligned. */
3748 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3749 * aligned. 4 - 512B aligned. */
3764 /* [WB 53] Onchip address table - B0 */
3772 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
3773 -128k */
3777 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3780 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
3787 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
3788 -128k */
3794 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
3795 -128k */
3865 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3868 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
3871 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3874 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3877 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3880 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3887 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3890 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3893 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
3895 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3898 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3901 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3908 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3911 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3964 queues 63-0 */
3969 queues 127-64 */
3976 queue uses port 0 else it uses port 1; queues 31-0 */
3979 queue uses port 0 else it uses port 1; queues 95-64 */
3982 queue uses port 0 else it uses port 1; queues 63-32 */
3985 queue uses port 0 else it uses port 1; queues 127-96 */
4027 physical queue uses the byte credit; queues 31-0 */
4030 physical queue uses the byte credit; queues 95-64 */
4033 physical queue uses the byte credit; queues 63-32 */
4036 physical queue uses the byte credit; queues 127-96 */
4049 be use for the almost empty indication to the HW block; queues 95-64 */
4055 be use for the almost empty indication to the HW block; queues 127-96 */
4064 /* [R 16] Pause state for physical queues 15-0 */
4066 /* [R 16] Pause state for physical queues 31-16 */
4068 /* [R 16] Pause state for physical queues 47-32 */
4070 /* [R 16] Pause state for physical queues 63-48 */
4072 /* [R 16] Pause state for physical queues 79-64 */
4074 /* [R 16] Pause state for physical queues 95-80 */
4076 /* [R 16] Pause state for physical queues 111-96 */
4078 /* [R 16] Pause state for physical queues 127-112 */
4090 /* [RW 3] pci function number of queues 15-0 */
4099 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
4103 /* [WB 54] Pointer Table Memory for queues 127-64; The mapping is as follow:
4125 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
4127 /* [R 24] The number of tasks queued for each queue; queues 127-64 */
4275 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4277 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4279 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4281 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4283 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4285 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4287 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4289 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4291 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4293 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4295 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4297 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4299 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4301 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4303 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4305 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4307 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4309 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4311 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4313 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4315 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4317 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4319 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4321 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4323 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4325 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4327 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4329 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4331 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4333 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4335 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4337 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4339 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4341 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4343 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4345 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4347 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4349 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4351 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4353 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4355 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4357 /* [RW 32] The physical queue number associated with each VOQ; queues 63-32 */
4359 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4361 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4363 /* [RW 32] The physical queue number associated with each VOQ; queues 95-64 */
4365 /* [RW 32] The physical queue number associated with each VOQ; queues 127-96 */
4405 /* [RW 1] If clr the searcher is compatible to E1 A0 - support only two
4436 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4438 usual; if 1 - normal activity. */
4440 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4441 are disregarded; all other signals are treated as usual; if 1 - normal
4444 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4446 usual; if 1 - normal activity. */
4448 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4449 input is disregarded; all other signals are treated as usual; if 1 -
4452 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4454 counter. Must be initialized to 1 at start-up. */
4460 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4462 treated as usual; if 1 - normal activity. */
4477 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
4479 credit counter. Must be initialized to 64 at start-up. */
4481 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
4483 credit counter. Must be initialized to 64 at start-up. */
4485 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4486 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
4498 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
4499 sent to STORM; for a specific connection type. The double REG-pairs are
4509 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4511 if 1 - normal activity. */
4528 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
4530 if 1 - normal activity. */
4544 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4546 treated as usual; if 1 - normal activity. */
4552 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4554 if 1 - normal activity. */
4566 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
4567 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4568 Is used to determine the number of the AG context REG-pairs written back;
4571 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4573 if 1 - normal activity. */
4575 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4577 if 1 - normal activity. */
4579 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4581 if 1 - normal activity. */
4587 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4589 treated as usual; if 1 - normal activity. */
4595 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
4597 counter. Must be initialized to 32 at start-up. */
4611 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4613 if 1 - normal activity. */
4615 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4617 if 1 - normal activity. */
4626 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4628 treated as usual; if 1 - normal activity. */
4638 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
4639 pointer; 20:16] - next pointer. */
4646 messages. Max credit available - 127.Write writes the initial credit
4648 initialized to 19 at start-up. */
4659 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
4817 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4818 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
4821 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4822 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4826 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4827 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4832 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4833 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
4839 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4840 sleeping thread with priority 1; 4- sleeping thread with priority 2.
4885 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4946 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4947 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
4949 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
4956 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4958 usual; if 1 - normal activity. */
4960 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4961 are disregarded; all other signals are treated as usual; if 1 - normal
4964 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4966 usual; if 1 - normal activity. */
4968 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4969 input is disregarded; all other signals are treated as usual; if 1 -
4972 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
4974 counter. Must be initialized to 1 at start-up. */
4980 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4982 treated as usual; if 1 - normal activity. */
4991 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4993 treated as usual; if 1 - normal activity. */
5008 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5010 credit counter. Must be initialized to 64 at start-up. */
5012 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5014 credit counter. Must be initialized to 64 at start-up. */
5016 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
5017 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
5031 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5032 sent to STORM; for a specific connection type. the double REG-pairs are
5055 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5057 treated as usual; if 1 - normal activity. */
5063 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
5065 credit counter. Must be initialized to 4 at start-up. */
5069 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5071 treated as usual; if 1 - normal activity. */
5077 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5079 treated as usual; if 1 - normal activity. */
5088 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5090 if 1 - normal activity. */
5102 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
5103 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5104 Is used to determine the number of the AG context REG-pairs written back;
5107 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5109 if 1 - normal activity. */
5111 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5113 if 1 - normal activity. */
5115 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5117 treated as usual; if 1 - normal activity. */
5119 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5121 if 1 - normal activity. */
5125 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5127 counter. Must be initialized to 32 at start-up. */
5141 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5143 if 1 - normal activity. */
5145 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5147 if 1 - normal activity. */
5156 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
5158 treated as usual; if 1 - normal activity. */
5168 mechanism. The fields are:[5:0] - message length; 14:6] - message
5169 pointer; 19:15] - next pointer. */
5177 value of the credit counter. Must be initialized to 12 at start-up. */
5185 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
5201 * decrement unit is 1 micro-second. */
5209 /* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive
5222 or auto-mask-mode (1) */
5309 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5310 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5313 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5314 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5318 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5319 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5324 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5325 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5331 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5332 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5377 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5438 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5439 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
5444 /* [RW 32] Indirect access to AG context with 32-bits granularity. The bits
5455 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
5457 usual; if 1 - normal activity. */
5459 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
5460 are disregarded; all other signals are treated as usual; if 1 - normal
5463 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
5465 usual; if 1 - normal activity. */
5467 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
5468 input is disregarded; all other signals are treated as usual; if 1 -
5471 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
5473 counter. Must be initialized to 1 at start-up. */
5479 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
5481 treated as usual; if 1 - normal activity. */
5490 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
5492 treated as usual; if 1 - normal activity. */
5507 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
5509 credit counter. Must be initialized to 64 at start-up. */
5511 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
5513 credit counter. Must be initialized to 64 at start-up. */
5519 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
5520 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
5532 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
5534 treated as usual; if 1 - normal activity. */
5543 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
5545 treated as usual; if 1 - normal activity. */
5550 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
5551 sent to STORM; for a specific connection type. The double REG-pairs are
5561 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
5563 if 1 - normal activity. */
5583 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5585 treated as usual; if 1 - normal activity. */
5587 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
5589 credit counter. Must be initialized to 4 at start-up. */
5597 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5599 treated as usual; if 1 - normal activity. */
5601 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5603 treated as usual; if 1 - normal activity. */
5614 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
5616 treated as usual; if 1 - normal activity. */
5637 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5639 if 1 - normal activity. */
5652 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
5653 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5654 Is used to determine the number of the AG context REG-pairs written back;
5657 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5659 if 1 - normal activity. */
5661 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5663 if 1 - normal activity. */
5665 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5667 treated as usual; if 1 - normal activity. */
5669 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5671 if 1 - normal activity. */
5677 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
5679 counter. Must be initialized to 32 at start-up. */
5693 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5695 if 1 - normal activity. */
5697 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5699 if 1 - normal activity. */
5709 mechanism. The fields are: [5:0] - message length; 11:6] - message
5710 pointer; 16:12] - next pointer. */
5717 messages. Max credit available - 3.Write writes the initial credit value;
5719 to 2 at start-up. */
5762 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
5782 or auto-mask-mode (1) */
5835 /* [W 17] Generate an operation after completion; bit-16 is
5863 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5864 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
5867 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5868 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5872 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5873 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5878 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5879 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
5885 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5886 sleeping thread with priority 1; 4- sleeping thread with priority 2.
5931 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5977 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5978 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. */
6299 /*E1H NIG status sync attention mapped to group 4-7*/
6550 * Since registers from 0x000-0x7ff are split across functions, each PF will
6805 ((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1)
6811 ((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1)
6816 ((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1)
6821 ((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1)
7284 /* When this pin is active high during reset, 10GBASE-T core is power
7285 * down, When it is active low the 10GBASE-T is power up
7569 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7574 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PORT * NUM_OF_PORTS_PER_PATH - 1)
7610 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
7628 /* String-to-compress [31:8] = CID (all 24 bits)
7629 * String-to-compress [7:4] = Region
7630 * String-to-compress [3:0] = Type
7720 * Calculates crc 8 on a word value: polynomial 0-1-2-8