Lines Matching +full:0 +full:x80b0
26 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
27 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1<<2)
28 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1<<5)
29 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1<<3)
30 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1<<4)
31 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1<<1)
33 #define ATC_REG_ATC_INIT_ARRAY 0x1100b8
35 #define ATC_REG_ATC_INIT_DONE 0x1100bc
36 /* [RC 6] Interrupt register #0 read clear */
37 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0
38 /* [RW 5] Parity mask register #0 read/write */
39 #define ATC_REG_ATC_PRTY_MASK 0x1101d8
40 /* [R 5] Parity register #0 read */
41 #define ATC_REG_ATC_PRTY_STS 0x1101cc
42 /* [RC 5] Parity register #0 read clear */
43 #define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0
44 /* [RW 19] Interrupt mask register #0 read/write */
45 #define BRB1_REG_BRB1_INT_MASK 0x60128
46 /* [R 19] Interrupt register #0 read */
47 #define BRB1_REG_BRB1_INT_STS 0x6011c
48 /* [RW 4] Parity mask register #0 read/write */
49 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
50 /* [R 4] Parity register #0 read */
51 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
52 /* [RC 4] Parity register #0 read clear */
53 #define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130
61 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
62 /* [RW 10] The number of free blocks below which the full signal to class 0
64 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_0 0x601d0
65 #define BRB1_REG_FULL_0_XOFF_THRESHOLD_1 0x60230
66 /* [RW 11] The number of free blocks above which the full signal to class 0
68 #define BRB1_REG_FULL_0_XON_THRESHOLD_0 0x601d4
69 #define BRB1_REG_FULL_0_XON_THRESHOLD_1 0x60234
72 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_0 0x601d8
73 #define BRB1_REG_FULL_1_XOFF_THRESHOLD_1 0x60238
76 #define BRB1_REG_FULL_1_XON_THRESHOLD_0 0x601dc
77 #define BRB1_REG_FULL_1_XON_THRESHOLD_1 0x6023c
80 #define BRB1_REG_FULL_LB_XOFF_THRESHOLD 0x601e0
83 #define BRB1_REG_FULL_LB_XON_THRESHOLD 0x601e4
86 #define BRB1_REG_HIGH_LLFC_HIGH_THRESHOLD_0 0x6014c
89 #define BRB1_REG_HIGH_LLFC_LOW_THRESHOLD_0 0x6013c
91 #define BRB1_REG_LB_GUARANTIED 0x601ec
94 #define BRB1_REG_LB_GUARANTIED_HYST 0x60264
96 #define BRB1_REG_LL_RAM 0x61000
99 #define BRB1_REG_LOW_LLFC_HIGH_THRESHOLD_0 0x6016c
102 #define BRB1_REG_LOW_LLFC_LOW_THRESHOLD_0 0x6015c
103 /* [RW 11] The number of blocks guarantied for class 0 in MAC 0. The
105 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED 0x60244
106 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
109 #define BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST 0x60254
110 /* [RW 11] The number of blocks guarantied for class 1 in MAC 0. The
112 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED 0x60248
113 /* [RW 11] The hysteresis on the guarantied buffer space for class 1in MAC 0
116 #define BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST 0x60258
117 /* [RW 11] The number of blocks guarantied for class 0in MAC1.The register
119 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED 0x6024c
120 /* [RW 11] The hysteresis on the guarantied buffer space for class 0 in MAC
123 #define BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST 0x6025c
126 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED 0x60250
130 #define BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST 0x60260
133 #define BRB1_REG_MAC_GUARANTIED_0 0x601e8
134 #define BRB1_REG_MAC_GUARANTIED_1 0x60240
136 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
137 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
139 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
140 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
141 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
142 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
144 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
145 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
146 /* [RW 10] The number of free blocks below which the pause signal to class 0
148 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0 0x601c0
149 #define BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1 0x60220
150 /* [RW 11] The number of free blocks above which the pause signal to class 0
152 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_0 0x601c4
153 #define BRB1_REG_PAUSE_0_XON_THRESHOLD_1 0x60224
156 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0 0x601c8
157 #define BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1 0x60228
160 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_0 0x601cc
161 #define BRB1_REG_PAUSE_1_XON_THRESHOLD_1 0x6022c
162 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */
163 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
164 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
165 /* [RW 10] Write client 0: Assert pause threshold. */
166 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
168 * guaranty mode (backwards-compatible mode). 0=per-MAC guaranty mode (BC
170 #define BRB1_REG_PER_CLASS_GUARANTY_MODE 0x60268
172 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094
174 #define BRB1_REG_SOFT_RESET 0x600dc
176 #define CCM_REG_CAM_OCCUP 0xd0188
177 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
180 #define CCM_REG_CCM_CFC_IFEN 0xd003c
181 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
184 #define CCM_REG_CCM_CQM_IFEN 0xd000c
186 Otherwise 0 is inserted. */
187 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
188 /* [RW 11] Interrupt mask register #0 read/write */
189 #define CCM_REG_CCM_INT_MASK 0xd01e4
190 /* [R 11] Interrupt register #0 read */
191 #define CCM_REG_CCM_INT_STS 0xd01d8
192 /* [RW 27] Parity mask register #0 read/write */
193 #define CCM_REG_CCM_PRTY_MASK 0xd01f4
194 /* [R 27] Parity register #0 read */
195 #define CCM_REG_CCM_PRTY_STS 0xd01e8
196 /* [RC 27] Parity register #0 read clear */
197 #define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec
198 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
199 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
202 #define CCM_REG_CCM_REG0_SZ 0xd00c4
203 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
206 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
207 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
210 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
211 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
214 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
215 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
218 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
219 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
222 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
223 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
226 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
230 #define CCM_REG_CFC_INIT_CRD 0xd0204
232 #define CCM_REG_CNT_AUX1_Q 0xd00c8
234 #define CCM_REG_CNT_AUX2_Q 0xd00cc
236 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
238 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
239 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
242 #define CCM_REG_CQM_CCM_IFEN 0xd0014
246 #define CCM_REG_CQM_INIT_CRD 0xd020c
247 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
250 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
251 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
254 #define CCM_REG_CQM_S_WEIGHT 0xd00bc
255 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
258 #define CCM_REG_CSDM_IFEN 0xd0018
261 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
262 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
265 #define CCM_REG_CSDM_WEIGHT 0xd00b4
268 #define CCM_REG_ERR_CCM_HDR 0xd0094
270 #define CCM_REG_ERR_EVNT_ID 0xd0098
274 #define CCM_REG_FIC0_INIT_CRD 0xd0210
278 #define CCM_REG_FIC1_INIT_CRD 0xd0214
279 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
284 #define CCM_REG_GR_ARB_TYPE 0xd015c
285 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
289 #define CCM_REG_GR_LD0_PR 0xd0164
290 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
294 #define CCM_REG_GR_LD1_PR 0xd0168
296 #define CCM_REG_INV_DONE_Q 0xd0108
300 bits. The offset of these data in the STORM context is always 0. Index
301 _(0..15) stands for the connection type (one of 16). */
302 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
303 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
304 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
305 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
306 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
307 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
310 #define CCM_REG_PBF_IFEN 0xd0028
313 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
314 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
317 #define CCM_REG_PBF_WEIGHT 0xd00ac
318 #define CCM_REG_PHYS_QNUM1_0 0xd0134
319 #define CCM_REG_PHYS_QNUM1_1 0xd0138
320 #define CCM_REG_PHYS_QNUM2_0 0xd013c
321 #define CCM_REG_PHYS_QNUM2_1 0xd0140
322 #define CCM_REG_PHYS_QNUM3_0 0xd0144
323 #define CCM_REG_PHYS_QNUM3_1 0xd0148
324 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
325 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
326 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
327 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
328 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
329 #define CCM_REG_QOS_PHYS_QNUM2_1 0xd0128
330 #define CCM_REG_QOS_PHYS_QNUM3_0 0xd012c
331 #define CCM_REG_QOS_PHYS_QNUM3_1 0xd0130
332 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
335 #define CCM_REG_STORM_CCM_IFEN 0xd0010
338 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
340 mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for
343 #define CCM_REG_STORM_WEIGHT 0xd009c
344 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
347 #define CCM_REG_TSEM_IFEN 0xd001c
350 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
351 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
354 #define CCM_REG_TSEM_WEIGHT 0xd00a0
355 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
358 #define CCM_REG_USEM_IFEN 0xd0024
361 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
362 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
365 #define CCM_REG_USEM_WEIGHT 0xd00a8
366 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
369 #define CCM_REG_XSEM_IFEN 0xd0020
372 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
373 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
376 #define CCM_REG_XSEM_WEIGHT 0xd00a4
378 mechanism. The fields are: [5:0] - message length; [12:6] - message
380 #define CCM_REG_XX_DESCR_TABLE 0xd0300
383 #define CCM_REG_XX_FREE 0xd0184
389 #define CCM_REG_XX_INIT_CRD 0xd0220
394 #define CCM_REG_XX_MSG_NUM 0xd0224
396 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
398 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
400 #define CCM_REG_XX_TABLE 0xd0280
401 #define CDU_REG_CDU_CHK_MASK0 0x101000
402 #define CDU_REG_CDU_CHK_MASK1 0x101004
403 #define CDU_REG_CDU_CONTROL0 0x101008
404 #define CDU_REG_CDU_DEBUG 0x101010
405 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
406 /* [RW 7] Interrupt mask register #0 read/write */
407 #define CDU_REG_CDU_INT_MASK 0x10103c
408 /* [R 7] Interrupt register #0 read */
409 #define CDU_REG_CDU_INT_STS 0x101030
410 /* [RW 5] Parity mask register #0 read/write */
411 #define CDU_REG_CDU_PRTY_MASK 0x10104c
412 /* [R 5] Parity register #0 read */
413 #define CDU_REG_CDU_PRTY_STS 0x101040
414 /* [RC 5] Parity register #0 read clear */
415 #define CDU_REG_CDU_PRTY_STS_CLR 0x101044
417 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
419 #define CDU_REG_ERROR_DATA 0x101014
421 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
422 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
423 #define CDU_REG_L1TT 0x101800
425 format:{RegionLength[11:0]; egionOffset[11:0]} */
426 #define CDU_REG_MATT 0x101100
428 #define CDU_REG_MF_MODE 0x101050
431 #define CFC_REG_AC_INIT_DONE 0x104078
433 #define CFC_REG_ACTIVITY_COUNTER 0x104400
436 #define CFC_REG_CAM_INIT_DONE 0x10407c
437 /* [RW 2] Interrupt mask register #0 read/write */
438 #define CFC_REG_CFC_INT_MASK 0x104108
439 /* [R 2] Interrupt register #0 read */
440 #define CFC_REG_CFC_INT_STS 0x1040fc
441 /* [RC 2] Interrupt register #0 read clear */
442 #define CFC_REG_CFC_INT_STS_CLR 0x104100
443 /* [RW 4] Parity mask register #0 read/write */
444 #define CFC_REG_CFC_PRTY_MASK 0x104118
445 /* [R 4] Parity register #0 read */
446 #define CFC_REG_CFC_PRTY_STS 0x10410c
447 /* [RC 4] Parity register #0 read clear */
448 #define CFC_REG_CFC_PRTY_STS_CLR 0x104110
449 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
450 #define CFC_REG_CID_CAM 0x104800
451 #define CFC_REG_CONTROL0 0x104028
452 #define CFC_REG_DEBUG0 0x104050
455 #define CFC_REG_DISABLE_ON_ERROR 0x104044
459 #define CFC_REG_ERROR_VECTOR 0x10403c
461 #define CFC_REG_INFO_RAM 0x105000
463 #define CFC_REG_INIT_REG 0x10404c
464 #define CFC_REG_INTERFACES 0x104058
465 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
468 #define CFC_REG_LCREQ_WEIGHTS 0x104084
470 #define CFC_REG_LINK_LIST 0x104c00
473 #define CFC_REG_LL_INIT_DONE 0x104074
475 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
477 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
478 #define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120
480 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
481 #define CFC_REG_WEAK_ENABLE_PF 0x104124
482 /* [RW 8] The event id for aggregated interrupt 0 */
483 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
484 #define CSDM_REG_AGG_INT_EVENT_10 0xc2060
485 #define CSDM_REG_AGG_INT_EVENT_11 0xc2064
486 #define CSDM_REG_AGG_INT_EVENT_12 0xc2068
487 #define CSDM_REG_AGG_INT_EVENT_13 0xc206c
488 #define CSDM_REG_AGG_INT_EVENT_14 0xc2070
489 #define CSDM_REG_AGG_INT_EVENT_15 0xc2074
490 #define CSDM_REG_AGG_INT_EVENT_16 0xc2078
491 #define CSDM_REG_AGG_INT_EVENT_2 0xc2040
492 #define CSDM_REG_AGG_INT_EVENT_3 0xc2044
493 #define CSDM_REG_AGG_INT_EVENT_4 0xc2048
494 #define CSDM_REG_AGG_INT_EVENT_5 0xc204c
495 #define CSDM_REG_AGG_INT_EVENT_6 0xc2050
496 #define CSDM_REG_AGG_INT_EVENT_7 0xc2054
497 #define CSDM_REG_AGG_INT_EVENT_8 0xc2058
498 #define CSDM_REG_AGG_INT_EVENT_9 0xc205c
499 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
501 #define CSDM_REG_AGG_INT_MODE_10 0xc21e0
502 #define CSDM_REG_AGG_INT_MODE_11 0xc21e4
503 #define CSDM_REG_AGG_INT_MODE_12 0xc21e8
504 #define CSDM_REG_AGG_INT_MODE_13 0xc21ec
505 #define CSDM_REG_AGG_INT_MODE_14 0xc21f0
506 #define CSDM_REG_AGG_INT_MODE_15 0xc21f4
507 #define CSDM_REG_AGG_INT_MODE_16 0xc21f8
508 #define CSDM_REG_AGG_INT_MODE_6 0xc21d0
509 #define CSDM_REG_AGG_INT_MODE_7 0xc21d4
510 #define CSDM_REG_AGG_INT_MODE_8 0xc21d8
511 #define CSDM_REG_AGG_INT_MODE_9 0xc21dc
513 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
514 /* [RW 16] The maximum value of the completion counter #0 */
515 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
517 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
519 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
521 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
524 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
525 /* [RW 32] Interrupt mask register #0 read/write */
526 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
527 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
528 /* [R 32] Interrupt register #0 read */
529 #define CSDM_REG_CSDM_INT_STS_0 0xc2290
530 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0
531 /* [RW 11] Parity mask register #0 read/write */
532 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
533 /* [R 11] Parity register #0 read */
534 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
535 /* [RC 11] Parity register #0 read clear */
536 #define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4
537 #define CSDM_REG_ENABLE_IN1 0xc2238
538 #define CSDM_REG_ENABLE_IN2 0xc223c
539 #define CSDM_REG_ENABLE_OUT1 0xc2240
540 #define CSDM_REG_ENABLE_OUT2 0xc2244
543 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
545 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
547 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
549 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
550 /* [ST 32] The number of commands received in queue 0 */
551 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
553 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
555 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
557 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
559 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
561 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
563 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
565 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
567 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
569 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
571 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
573 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
575 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
577 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
579 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
582 #define CSDM_REG_TIMER_TICK 0xc2000
584 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
585 /* [RW 3] The source that is associated with arbitration element 0. Source
586 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
588 #define CSEM_REG_ARB_ELEMENT0 0x200020
590 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
593 #define CSEM_REG_ARB_ELEMENT1 0x200024
595 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
599 #define CSEM_REG_ARB_ELEMENT2 0x200028
601 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
606 #define CSEM_REG_ARB_ELEMENT3 0x20002c
608 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
614 #define CSEM_REG_ARB_ELEMENT4 0x200030
615 /* [RW 32] Interrupt mask register #0 read/write */
616 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
617 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
618 /* [R 32] Interrupt register #0 read */
619 #define CSEM_REG_CSEM_INT_STS_0 0x200104
620 #define CSEM_REG_CSEM_INT_STS_1 0x200114
621 /* [RW 32] Parity mask register #0 read/write */
622 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
623 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
624 /* [R 32] Parity register #0 read */
625 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
626 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
627 /* [RC 32] Parity register #0 read clear */
628 #define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128
629 #define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138
630 #define CSEM_REG_ENABLE_IN 0x2000a4
631 #define CSEM_REG_ENABLE_OUT 0x2000a8
636 #define CSEM_REG_FAST_MEMORY 0x220000
639 #define CSEM_REG_FIC0_DISABLE 0x200224
642 #define CSEM_REG_FIC1_DISABLE 0x200234
645 #define CSEM_REG_INT_TABLE 0x200400
648 #define CSEM_REG_MSG_NUM_FIC0 0x200000
651 #define CSEM_REG_MSG_NUM_FIC1 0x200004
654 #define CSEM_REG_MSG_NUM_FOC0 0x200008
657 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
660 #define CSEM_REG_MSG_NUM_FOC2 0x200010
663 #define CSEM_REG_MSG_NUM_FOC3 0x200014
666 #define CSEM_REG_PAS_DISABLE 0x20024c
668 #define CSEM_REG_PASSIVE_BUFFER 0x202000
669 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
670 #define CSEM_REG_PRAM 0x240000
672 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
674 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
676 #define CSEM_REG_THREADS_LIST 0x2002e4
677 /* [RW 3] The arbitration scheme of time_slot 0 */
678 #define CSEM_REG_TS_0_AS 0x200038
680 #define CSEM_REG_TS_10_AS 0x200060
682 #define CSEM_REG_TS_11_AS 0x200064
684 #define CSEM_REG_TS_12_AS 0x200068
686 #define CSEM_REG_TS_13_AS 0x20006c
688 #define CSEM_REG_TS_14_AS 0x200070
690 #define CSEM_REG_TS_15_AS 0x200074
692 #define CSEM_REG_TS_16_AS 0x200078
694 #define CSEM_REG_TS_17_AS 0x20007c
696 #define CSEM_REG_TS_18_AS 0x200080
698 #define CSEM_REG_TS_1_AS 0x20003c
700 #define CSEM_REG_TS_2_AS 0x200040
702 #define CSEM_REG_TS_3_AS 0x200044
704 #define CSEM_REG_TS_4_AS 0x200048
706 #define CSEM_REG_TS_5_AS 0x20004c
708 #define CSEM_REG_TS_6_AS 0x200050
710 #define CSEM_REG_TS_7_AS 0x200054
712 #define CSEM_REG_TS_8_AS 0x200058
714 #define CSEM_REG_TS_9_AS 0x20005c
715 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
717 #define CSEM_REG_VFPF_ERR_NUM 0x200380
718 /* [RW 1] Parity mask register #0 read/write */
719 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
720 /* [R 1] Parity register #0 read */
721 #define DBG_REG_DBG_PRTY_STS 0xc09c
722 /* [RC 1] Parity register #0 read clear */
723 #define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0
725 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID=0;
726 * 4.Completion function=0; 5.Error handling=0 */
727 #define DMAE_REG_BACKWARD_COMP_EN 0x10207c
730 #define DMAE_REG_CMD_MEM 0x102400
732 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
734 #define DMAE_REG_CRC16C_INIT 0x10201c
735 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
737 #define DMAE_REG_CRC16T10_INIT 0x102020
738 /* [RW 2] Interrupt mask register #0 read/write */
739 #define DMAE_REG_DMAE_INT_MASK 0x102054
740 /* [RW 4] Parity mask register #0 read/write */
741 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
742 /* [R 4] Parity register #0 read */
743 #define DMAE_REG_DMAE_PRTY_STS 0x102058
744 /* [RC 4] Parity register #0 read clear */
745 #define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c
746 /* [RW 1] Command 0 go. */
747 #define DMAE_REG_GO_C0 0x102080
749 #define DMAE_REG_GO_C1 0x102084
751 #define DMAE_REG_GO_C10 0x102088
753 #define DMAE_REG_GO_C11 0x10208c
755 #define DMAE_REG_GO_C12 0x102090
757 #define DMAE_REG_GO_C13 0x102094
759 #define DMAE_REG_GO_C14 0x102098
761 #define DMAE_REG_GO_C15 0x10209c
763 #define DMAE_REG_GO_C2 0x1020a0
765 #define DMAE_REG_GO_C3 0x1020a4
767 #define DMAE_REG_GO_C4 0x1020a8
769 #define DMAE_REG_GO_C5 0x1020ac
771 #define DMAE_REG_GO_C6 0x1020b0
773 #define DMAE_REG_GO_C7 0x1020b4
775 #define DMAE_REG_GO_C8 0x1020b8
777 #define DMAE_REG_GO_C9 0x1020bc
778 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
781 #define DMAE_REG_GRC_IFEN 0x102008
782 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
785 #define DMAE_REG_PCI_IFEN 0x102004
789 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
791 #define DORQ_REG_AGG_CMD0 0x170060
793 #define DORQ_REG_AGG_CMD1 0x170064
795 #define DORQ_REG_AGG_CMD2 0x170068
797 #define DORQ_REG_AGG_CMD3 0x17006c
799 #define DORQ_REG_CMHEAD_RX 0x170050
800 /* [RW 32] Doorbell address for RBC doorbells (function 0). */
801 #define DORQ_REG_DB_ADDR0 0x17008c
802 /* [RW 5] Interrupt mask register #0 read/write */
803 #define DORQ_REG_DORQ_INT_MASK 0x170180
804 /* [R 5] Interrupt register #0 read */
805 #define DORQ_REG_DORQ_INT_STS 0x170174
806 /* [RC 5] Interrupt register #0 read clear */
807 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
808 /* [RW 2] Parity mask register #0 read/write */
809 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
810 /* [R 2] Parity register #0 read */
811 #define DORQ_REG_DORQ_PRTY_STS 0x170184
812 /* [RC 2] Parity register #0 read clear */
813 #define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188
815 #define DORQ_REG_DPM_CID_ADDR 0x170044
817 #define DORQ_REG_DPM_CID_OFST 0x170030
819 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
821 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
823 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
825 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
828 #define DORQ_REG_DQ_FULL_ST 0x1700c0
830 #define DORQ_REG_ERR_CMHEAD 0x170058
831 #define DORQ_REG_IF_EN 0x170004
832 #define DORQ_REG_MAX_RVFID_SIZE 0x1701ec
833 #define DORQ_REG_MODE_ACT 0x170008
835 #define DORQ_REG_NORM_CID_OFST 0x17002c
837 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
840 #define DORQ_REG_OUTST_REQ 0x17003c
841 #define DORQ_REG_PF_USAGE_CNT 0x1701d0
842 #define DORQ_REG_REGN 0x170038
846 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
850 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
854 #define DORQ_REG_RSP_INIT_CRD 0x170048
855 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
856 #define DORQ_REG_VF_NORM_CID_BASE 0x1701a0
857 #define DORQ_REG_VF_NORM_CID_OFST 0x1701f4
858 #define DORQ_REG_VF_NORM_CID_WND_SIZE 0x1701a4
859 #define DORQ_REG_VF_NORM_MAX_CID_COUNT 0x1701e4
860 #define DORQ_REG_VF_NORM_VF_BASE 0x1701a8
862 #define DORQ_REG_VF_TYPE_MASK_0 0x170218
864 #define DORQ_REG_VF_TYPE_MAX_MCID_0 0x1702d8
866 #define DORQ_REG_VF_TYPE_MIN_MCID_0 0x170298
868 #define DORQ_REG_VF_TYPE_VALUE_0 0x170258
869 #define DORQ_REG_VF_USAGE_CT_LIMIT 0x170340
873 #define DORQ_REG_SHRT_ACT_CNT 0x170070
875 #define DORQ_REG_SHRT_CMHEAD 0x170054
876 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
877 #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1<<0)
878 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
879 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1<<7)
880 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
881 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
882 #define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1<<0)
883 #define DORQ_REG_VF_USAGE_CNT 0x170320
884 #define HC_REG_AGG_INT_0 0x108050
885 #define HC_REG_AGG_INT_1 0x108054
886 #define HC_REG_ATTN_BIT 0x108120
887 #define HC_REG_ATTN_IDX 0x108100
888 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
889 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
890 #define HC_REG_ATTN_NUM_P0 0x108038
891 #define HC_REG_ATTN_NUM_P1 0x10803c
892 #define HC_REG_COMMAND_REG 0x108180
893 #define HC_REG_CONFIG_0 0x108000
894 #define HC_REG_CONFIG_1 0x108004
895 #define HC_REG_FUNC_NUM_P0 0x1080ac
896 #define HC_REG_FUNC_NUM_P1 0x1080b0
897 /* [RW 3] Parity mask register #0 read/write */
898 #define HC_REG_HC_PRTY_MASK 0x1080a0
899 /* [R 3] Parity register #0 read */
900 #define HC_REG_HC_PRTY_STS 0x108094
901 /* [RC 3] Parity register #0 read clear */
902 #define HC_REG_HC_PRTY_STS_CLR 0x108098
903 #define HC_REG_INT_MASK 0x108108
904 #define HC_REG_LEADING_EDGE_0 0x108040
905 #define HC_REG_LEADING_EDGE_1 0x108048
906 #define HC_REG_MAIN_MEMORY 0x108800
908 #define HC_REG_P0_PROD_CONS 0x108200
909 #define HC_REG_P1_PROD_CONS 0x108400
910 #define HC_REG_PBA_COMMAND 0x108140
911 #define HC_REG_PCI_CONFIG_0 0x108010
912 #define HC_REG_PCI_CONFIG_1 0x108014
913 #define HC_REG_STATISTIC_COUNTERS 0x109000
914 #define HC_REG_TRAILING_EDGE_0 0x108044
915 #define HC_REG_TRAILING_EDGE_1 0x10804c
916 #define HC_REG_UC_RAM_ADDR_0 0x108028
917 #define HC_REG_UC_RAM_ADDR_1 0x108030
918 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
919 #define HC_REG_VQID_0 0x108008
920 #define HC_REG_VQID_1 0x10800c
921 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1<<1)
922 #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1<<0)
923 #define IGU_REG_ATTENTION_ACK_BITS 0x130108
925 #define IGU_REG_ATTN_FSM 0x130054
926 #define IGU_REG_ATTN_MSG_ADDR_H 0x13011c
927 #define IGU_REG_ATTN_MSG_ADDR_L 0x130120
928 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending;
929 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but
931 #define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030
932 #define IGU_REG_BLOCK_CONFIGURATION 0x130000
933 #define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124
934 #define IGU_REG_COMMAND_REG_CTRL 0x13012c
935 /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit
937 * command. Data valid only in addresses 0-4. all the rest are zero. */
938 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200
940 #define IGU_REG_CTRL_FSM 0x130064
943 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130
944 /* [RW 11] Parity mask register #0 read/write */
945 #define IGU_REG_IGU_PRTY_MASK 0x1300a8
946 /* [R 11] Parity register #0 read */
947 #define IGU_REG_IGU_PRTY_STS 0x13009c
948 /* [RC 11] Parity register #0 read clear */
949 #define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0
951 #define IGU_REG_INT_HANDLE_FSM 0x130050
952 #define IGU_REG_LEADING_EDGE_LATCH 0x130134
953 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid.
954 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF
955 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); */
956 #define IGU_REG_MAPPING_MEMORY 0x131000
958 #define IGU_REG_PBA_STATUS_LSB 0x130138
959 #define IGU_REG_PBA_STATUS_MSB 0x13013c
960 #define IGU_REG_PCI_PF_MSI_EN 0x130140
961 #define IGU_REG_PCI_PF_MSIX_EN 0x130144
962 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148
963 /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no
965 * done was not received. Data valid only in addresses 0-4. all the rest are
967 #define IGU_REG_PENDING_BITS_STATUS 0x130300
968 #define IGU_REG_PF_CONFIGURATION 0x130154
969 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping
975 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The
979 #define IGU_REG_PROD_CONS_MEMORY 0x132000
981 #define IGU_REG_PXP_ARB_FSM 0x130068
983 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping
986 #define IGU_REG_RESET_MEMORIES 0x130158
988 #define IGU_REG_SB_CTRL_FSM 0x13004c
989 #define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c
990 #define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160
991 #define IGU_REG_SB_MASK_LSB 0x130164
992 #define IGU_REG_SB_MASK_MSB 0x130168
997 #define IGU_REG_SILENT_DROP 0x13016c
998 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 -
1001 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800
1004 #define IGU_REG_TIMER_MASKING_VALUE 0x13003c
1005 #define IGU_REG_TRAILING_EDGE_LATCH 0x130104
1006 #define IGU_REG_VF_CONFIGURATION 0x130170
1008 * (MSI/MSIX message was sent and write done was not received yet). 0 =
1009 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. */
1010 #define IGU_REG_WRITE_DONE_PENDING 0x130480
1011 #define MCP_A_REG_MCPR_SCRATCH 0x3a0000
1012 #define MCP_REG_MCPR_ACCESS_LOCK 0x8009c
1013 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
1014 #define MCP_REG_MCPR_GP_INPUTS 0x800c0
1015 #define MCP_REG_MCPR_GP_OENABLE 0x800c8
1016 #define MCP_REG_MCPR_GP_OUTPUTS 0x800c4
1017 #define MCP_REG_MCPR_IMC_COMMAND 0x85900
1018 #define MCP_REG_MCPR_IMC_DATAREG0 0x85920
1019 #define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904
1020 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c
1021 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
1022 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
1023 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
1024 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
1025 #define MCP_REG_MCPR_NVM_READ 0x86410
1026 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
1027 #define MCP_REG_MCPR_NVM_WRITE 0x86408
1028 #define MCP_REG_MCPR_SCRATCH 0xa0000
1029 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1<<1)
1030 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1<<0)
1031 /* [R 32] read first 32 bit after inversion of function 0. mapped as
1032 follows: [0] NIG attention for function0; [1] NIG attention for
1044 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
1045 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
1046 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
1059 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
1060 /* [R 32] read second 32 bit after inversion of function 0. mapped as
1061 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1073 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
1074 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
1075 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
1087 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
1088 /* [R 32] read third 32 bit after inversion of function 0. mapped as
1089 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
1101 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
1102 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
1103 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
1115 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
1116 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
1117 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1128 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
1129 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
1130 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
1142 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
1143 /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as
1144 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1147 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700
1158 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
1159 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
1160 as follows: [0] NIG attention for function0; [1] NIG attention for
1161 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1162 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1166 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1172 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
1173 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
1174 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c
1175 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
1176 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5 0xa0bc
1177 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6 0xa0cc
1178 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7 0xa0dc
1180 as follows: [0] NIG attention for function0; [1] NIG attention for
1192 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
1193 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
1194 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c
1195 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
1196 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5 0xa15c
1197 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6 0xa16c
1198 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7 0xa17c
1200 as follows: [0] NIG attention for function0; [1] NIG attention for
1201 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1202 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1206 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1212 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
1213 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
1215 as follows: [0] NIG attention for function0; [1] NIG attention for
1216 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
1217 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
1221 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
1227 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
1228 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
1229 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
1230 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1242 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
1243 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
1245 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1257 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
1258 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
1260 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1272 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1273 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1275 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
1287 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1288 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1289 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1290 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1302 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1303 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1305 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1317 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1318 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1320 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1332 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1333 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1335 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1347 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1348 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1349 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1350 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1361 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1362 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1363 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4 0xa0b8
1364 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5 0xa0c8
1365 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6 0xa0d8
1366 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7 0xa0e8
1368 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1379 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1380 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1381 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4 0xa158
1382 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5 0xa168
1383 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6 0xa178
1384 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7 0xa188
1386 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1397 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1398 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1400 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1411 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1412 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1413 /* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped
1414 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1418 #define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688
1420 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC
1424 #define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0
1425 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1427 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1428 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1429 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1430 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1431 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1432 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1433 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1434 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1435 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1436 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1437 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1438 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1439 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1440 #define MISC_REG_AEU_GENERAL_MASK 0xa61c
1441 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1442 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1454 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1455 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1456 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1457 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1469 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1470 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1471 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1473 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1474 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1476 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610
1478 kill occurred. The register is reset in por reset. Mapped as follows: [0]
1491 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600
1492 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604
1493 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608
1494 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c
1495 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1497 #define MISC_REG_BOND_ID 0xa400
1499 #define MISC_REG_CHIP_NUM 0xa408
1501 starts at 0x0 for the A0 tape-out and increments by one for each
1503 #define MISC_REG_CHIP_REV 0xa40c
1504 /* [R 14] otp_misc_do[100:0] spare bits collection: 13:11-
1506 * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. */
1507 #define MISC_REG_CHIP_TYPE 0xac60
1509 #define MISC_REG_CPMU_LP_DR_ENABLE 0xa858
1511 * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk
1513 #define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84c
1516 #define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a0
1517 /* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that
1518 * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM
1520 * the FW command that all Queues are empty is disabled. When 0 indicates
1523 * Exit command is disabled. When 0 indicates that the FW Early Exit command
1526 * is disabled. When 0 indicates that the PBF Request indication is enabled.
1528 * Request indication is disabled. When 0 indicates that the Tx Other Than
1530 * indicates that the RX EEE LPI Status indication is disabled. When 0
1534 * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause
1536 * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY
1538 * IDLE indication is disabled. When 0 indicates that the QM IDLE indication
1540 * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0
1543 * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication
1547 * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI
1549 * indicates that the P0 EEE LPI REQ indication is disabled. When =0
1552 * disabled. When =0 indicates that the P0 EEE LPI REQ indication is
1554 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
1556 * REQ indication is disabled. When =0 indicates that the L1 indication is
1559 * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status
1564 * When =0 indicates that the L1 Status Falling Edge Detect indication from
1567 #define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa880
1568 /* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates
1569 * that the Vmain SM end state is disabled. When 0 indicates that the Vmain
1571 * that the FW command that all Queues are empty is disabled. When 0
1574 * Early Exit command is disabled. When 0 indicates that the FW Early Exit
1577 * indication is disabled. When 0 indicates that the PBF Request indication
1579 * Than PBF Request indication is disabled. When 0 indicates that the Tx
1582 * When 0 indicates that the RX LPI Status indication is enabled. In the
1585 * indicates that the Tx Pause indication is disabled. When 0 indicates that
1587 * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates
1589 * indicates that the QM IDLE indication is disabled. When 0 indicates that
1592 * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for
1594 * Status indication from the PCIE CORE is disabled. When 0 indicates that
1599 * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1
1601 * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is
1603 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ
1605 * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that
1607 * indicates that the L1 REQ indication is disabled. When =0 indicates that
1610 * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that
1615 * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge
1619 #define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa888
1623 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8
1627 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc
1639 interrupt will be asserted). write to address 0 will set a request to
1644 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1645 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8
1646 /* [RW 1] e1hmf for WOL. If clr WOL signal o the PXP will be send on bit 0
1648 #define MISC_REG_E1HMF_MODE 0xa5f8
1650 #define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c
1651 /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 -
1654 Overwrite value. If bit[0] of this register is 1 this is the value that
1656 #define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738
1658 #define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754
1659 /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 -
1662 Overwrite value. If bit[0] of this register is 1 this is the value that
1664 #define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734
1666 #define MISC_REG_GENERIC_CR_0 0xa460
1667 #define MISC_REG_GENERIC_CR_1 0xa464
1669 #define MISC_REG_GENERIC_POR_1 0xa474
1670 /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to
1676 When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change
1679 #define MISC_REG_GEN_PURP_HWG 0xa9a0
1680 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1684 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1685 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1688 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1692 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1696 #define MISC_REG_GPIO 0xa490
1698 IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2]
1701 #define MISC_REG_GPIO_EVENT_EN 0xa2bc
1705 GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0;
1708 corresponding SPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1;
1711 of the pin such that if ~INT_STATE is set and this bit is '0'; then the
1713 is '1'; then the interrupt is due to a high to low edge (reset value 0).
1714 [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the
1718 (reset value 0). */
1719 #define MISC_REG_GPIO_INT 0xa494
1721 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1725 #define MISC_REG_GRC_RSV_ATTN 0xa3c0
1727 attention. bits [19:0] - address; [22:20] function; [23] reserved;
1731 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4
1737 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1739 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1740 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1743 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1748 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1749 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1750 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1751 connected to RESET input directly. [15] capRetry_en (reset value 0)
1753 value 0) bit to continuously monitor vco freq (inverted). [17]
1754 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1755 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1757 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1758 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1759 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1760 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1761 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1762 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1763 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1764 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1766 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1767 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1770 #define MISC_REG_LCPLL_E40_PWRDWN 0xaa74
1772 #define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78
1775 #define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c
1776 /* [RW 4] Interrupt mask register #0 read/write */
1777 #define MISC_REG_MISC_INT_MASK 0xa388
1778 /* [RW 1] Parity mask register #0 read/write */
1779 #define MISC_REG_MISC_PRTY_MASK 0xa398
1780 /* [R 1] Parity register #0 read */
1781 #define MISC_REG_MISC_PRTY_STS 0xa38c
1782 /* [RC 1] Parity register #0 read clear */
1783 #define MISC_REG_MISC_PRTY_STS_CLR 0xa390
1784 #define MISC_REG_NIG_WOL_P0 0xa270
1785 #define MISC_REG_NIG_WOL_P1 0xa274
1788 #define MISC_REG_PCIE_HOT_RESET 0xa618
1789 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1790 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1791 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1792 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1793 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1794 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1795 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1796 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1797 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1798 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1799 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1800 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1801 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1803 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1804 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1805 testa_en (reset value 0); */
1806 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1807 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1808 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1809 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1811 #define MISC_REG_PORT4MODE_EN 0xa750
1812 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 -
1815 * Overwrite value. If bit[0] of this register is 1 this is the value that
1817 #define MISC_REG_PORT4MODE_EN_OVWR 0xa720
1819 write/read zero = the specific block is in reset; addr 0-wr- the write
1826 [0] rst_bmac0; [1] rst_bmac1; [2] rst_emac0; [3] rst_emac1; [4] rst_grc;
1832 #define MISC_REG_RESET_REG_1 0xa580
1833 #define MISC_REG_RESET_REG_2 0xa590
1836 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1841 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1844 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1848 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1851 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1860 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1862 #define MISC_REG_SPIO 0xa4fc
1864 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1865 [7:0] reserved */
1866 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1870 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1872 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1875 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1877 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1881 match the current value in #OLD_VALUE (reset value 0). */
1882 #define MISC_REG_SPIO_INT 0xa500
1886 #define MISC_REG_SW_TIMER_RELOAD_VAL_4 0xa2fc
1888 in this register. address 0 - timer 1; address 1 - timer 2, ... address 7 -
1890 #define MISC_REG_SW_TIMER_VAL 0xa5c0
1892 #define MISC_REG_TWO_PORT_PATH_SWAP 0xa758
1893 /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the
1896 Overwrite value. If bit[0] of this register is 1 this is the value that
1898 #define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c
1900 loaded; 0-prepare; -unprepare */
1901 #define MISC_REG_UNPREPARED 0xa424
1902 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1903 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1904 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1905 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1906 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1911 #define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc
1912 #define MISC_REG_WC0_RESET 0xac30
1920 #define MISC_REG_XMAC_CORE_PORT_MODE 0xa964
1926 #define MISC_REG_XMAC_PHY_PORT_MODE 0xa960
1927 /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0.
1928 * Reads from this register will clear bits 31:0. */
1929 #define MSTAT_REG_RX_STAT_GR64_LO 0x200
1931 * 31:0. Reads from this register will clear bits 31:0. */
1932 #define MSTAT_REG_TX_STAT_GTXPOK_LO 0
1933 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST (0x1<<0)
1934 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST (0x1<<1)
1935 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN (0x1<<4)
1936 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST (0x1<<2)
1937 #define NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN (0x1<<3)
1938 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1<<0)
1939 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1<<0)
1940 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1941 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1942 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1943 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1945 #define NIG_REG_BMAC0_IN_EN 0x100ac
1947 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1948 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1949 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1951 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1953 #define NIG_REG_BRB0_OUT_EN 0x100f8
1954 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1955 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1957 #define NIG_REG_BRB1_OUT_EN 0x100fc
1959 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1961 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1962 /* [WB_W 82] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1965 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1967 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1972 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1974 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1977 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1979 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1981 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1983 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4
1985 #define NIG_REG_EMAC0_IN_EN 0x100a4
1986 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1987 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1991 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1994 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1996 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1999 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
2001 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
2003 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
2005 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
2006 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
2007 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch
2010 #define NIG_REG_LATCH_BC_0 0x16210
2011 /* [RW 27] Latch for each interrupt from Unicore.b[0]
2024 #define NIG_REG_LATCH_STATUS_0 0x18000
2025 /* [RW 1] led 10g for port 0 */
2026 #define NIG_REG_LED_10G_P0 0x10320
2028 #define NIG_REG_LED_10G_P1 0x10324
2033 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
2036 is reset to 0x080; giving a default blink period of approximately 8Hz. */
2037 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
2045 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
2050 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
2057 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
2058 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
2060 #define NIG_REG_LED_MODE_P0 0x102f0
2063 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070
2064 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074
2066 ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same
2068 #define NIG_REG_LLFC_ENABLE_0 0x16208
2069 #define NIG_REG_LLFC_ENABLE_1 0x1620c
2071 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058
2072 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c
2074 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060
2075 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064
2077 #define NIG_REG_LLFC_OUT_EN_0 0x160c8
2078 #define NIG_REG_LLFC_OUT_EN_1 0x160cc
2079 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c
2080 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154
2081 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
2082 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048
2084 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
2085 /* [RW 2] Determine the classification participants. 0: no classification.1:
2088 #define NIG_REG_LLH0_CLS_TYPE 0x16080
2090 #define NIG_REG_LLH0_CM_HEADER 0x1007c
2091 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc
2092 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0
2095 #define NIG_REG_LLH0_DEST_TCP_0 0x10220
2098 #define NIG_REG_LLH0_DEST_UDP_0 0x10214
2099 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
2101 #define NIG_REG_LLH0_EVENT_ID 0x10084
2102 #define NIG_REG_LLH0_FUNC_EN 0x160fc
2103 #define NIG_REG_LLH0_FUNC_MEM 0x16180
2104 #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140
2105 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100
2107 ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 */
2108 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208
2110 #define NIG_REG_LLH0_T_BIT 0x10074
2112 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c
2114 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
2115 #define NIG_REG_LLH0_XCM_MASK 0x10130
2116 #define NIG_REG_LLH1_BRB1_DRV_MASK 0x10248
2118 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
2119 /* [RW 2] Determine the classification participants. 0: no classification.1:
2122 #define NIG_REG_LLH1_CLS_TYPE 0x16084
2124 #define NIG_REG_LLH1_CM_HEADER 0x10080
2125 #define NIG_REG_LLH1_ERROR_MASK 0x10090
2127 #define NIG_REG_LLH1_EVENT_ID 0x10088
2128 #define NIG_REG_LLH1_FUNC_EN 0x16104
2129 #define NIG_REG_LLH1_FUNC_MEM 0x161c0
2130 #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160
2134 * only. The legacy llh_multi_function_mode bit controls port 0. */
2135 #define NIG_REG_LLH1_MF_MODE 0x18614
2137 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
2138 #define NIG_REG_LLH1_XCM_MASK 0x10134
2141 #define NIG_REG_LLH_E1HOV_MODE 0x160d8
2143 * multi-function mode; it will hold the inner VLAN type. Typically 0x8100.
2145 #define NIG_REG_LLH_E1HOV_TYPE_1 0x16028
2148 #define NIG_REG_LLH_MF_MODE 0x16024
2149 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
2150 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
2152 #define NIG_REG_NIG_EMAC0_EN 0x1003c
2154 #define NIG_REG_NIG_EMAC1_EN 0x10040
2157 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
2158 /* [R 32] Interrupt register #0 read */
2159 #define NIG_REG_NIG_INT_STS_0 0x103b0
2160 #define NIG_REG_NIG_INT_STS_1 0x103c0
2161 /* [RC 32] Interrupt register #0 read clear */
2162 #define NIG_REG_NIG_INT_STS_CLR_0 0x103b4
2164 #define NIG_REG_NIG_PRTY_MASK 0x103dc
2165 /* [RW 32] Parity mask register #0 read/write */
2166 #define NIG_REG_NIG_PRTY_MASK_0 0x183c8
2167 #define NIG_REG_NIG_PRTY_MASK_1 0x183d8
2169 #define NIG_REG_NIG_PRTY_STS 0x103d0
2170 /* [R 32] Parity register #0 read */
2171 #define NIG_REG_NIG_PRTY_STS_0 0x183bc
2172 #define NIG_REG_NIG_PRTY_STS_1 0x183cc
2174 #define NIG_REG_NIG_PRTY_STS_CLR 0x103d4
2175 /* [RC 32] Parity register #0 read clear */
2176 #define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0
2177 #define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0
2184 #define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038
2188 #define NIG_REG_P0_HWPFC_ENABLE 0x18078
2189 #define NIG_REG_P0_LLH_FUNC_MEM2 0x18480
2190 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE 0x18440
2192 * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
2196 #define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID 0x1875c
2200 #define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB 0x18754
2204 #define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB 0x18758
2207 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2208 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2209 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2210 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2211 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2214 #define NIG_REG_P0_LLH_PTP_PARAM_MASK 0x187a0
2216 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2217 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2218 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2219 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2220 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2221 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2222 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
2227 #define NIG_REG_P0_LLH_PTP_RULE_MASK 0x187a4
2229 #define NIG_REG_P0_LLH_PTP_TO_HOST 0x187ac
2231 #define NIG_REG_P0_MAC_IN_EN 0x185ac
2233 #define NIG_REG_P0_MAC_OUT_EN 0x185b0
2235 #define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4
2236 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2237 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2238 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2240 * Only COS 0 and COS 1 are supported in E2. */
2241 #define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054
2242 /* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
2243 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
2252 #define NIG_REG_P0_PTP_EN 0x18788
2253 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2254 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2257 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058
2262 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c
2267 #define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0
2272 #define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4
2277 #define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8
2282 #define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc
2285 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For
2288 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0
2290 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2291 * for client 0; bits [35:32] are for client 8. For clients that are not
2295 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2296 * use credit registers 0-5 respectively (0x543210876). Note that credit
2298 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688
2300 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2301 * for client 0; bits [35:32] are for client 8. For clients that are not
2305 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2306 * use credit registers 0-5 respectively (0x543210876). Note that credit
2308 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c
2312 * strict priorities for clients 0-2 -- management and debug traffic. */
2313 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8
2316 * tx_arb_priority_client). Default value is 0 for not using WFQ credit
2318 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec
2319 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2321 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c
2322 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110
2323 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114
2324 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118
2325 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c
2326 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0
2327 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4
2328 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8
2329 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac
2330 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2332 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8
2333 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc
2334 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100
2335 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104
2336 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108
2337 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690
2338 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694
2339 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698
2340 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c
2342 * two round-robin arbitration slots to avoid starvation. A value of 0 means
2345 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4
2347 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0]
2348 * are for priority 0 client; bits [14:12] are for priority 4 client. The
2349 * clients are assigned the following IDs: 0-management; 1-debug traffic
2351 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000)
2352 * for management at priority 0; debug traffic at priorities 1 and 2; COS0
2354 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4
2357 #define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c
2358 #define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0
2359 #define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE 0x18460a
2361 * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
2365 #define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID 0x18774
2369 #define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB 0x1876c
2373 #define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB 0x18770
2376 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2377 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2378 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2379 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2380 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2383 #define NIG_REG_P1_LLH_PTP_PARAM_MASK 0x187c8
2385 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2386 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2387 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2388 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2389 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2390 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2391 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
2396 #define NIG_REG_P1_LLH_PTP_RULE_MASK 0x187cc
2398 #define NIG_REG_P1_LLH_PTP_TO_HOST 0x187d4
2400 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2401 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2403 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2405 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2406 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2408 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680
2411 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2413 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2415 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2416 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2418 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684
2423 * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter
2427 #define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f4
2428 #define NIG_REG_P1_HWPFC_ENABLE 0x181d0
2429 #define NIG_REG_P1_MAC_IN_EN 0x185c0
2431 #define NIG_REG_P1_MAC_OUT_EN 0x185c4
2433 #define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8
2434 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for
2435 * future expansion) each priorty is to be mapped to. Bits 3:0 specify the
2436 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit
2438 * Only COS 0 and COS 1 are supported in E2. */
2439 #define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8
2440 /* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
2441 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
2450 #define NIG_REG_P1_PTP_EN 0x187b0
2451 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
2452 * priority is mapped to COS 0 when the corresponding mask bit is 1. More
2455 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac
2460 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0
2465 #define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8
2467 #define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c
2469 #define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338
2471 * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
2475 * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
2477 #define NIG_REG_P0_TLLH_PTP_BUF_SEQID 0x187e0
2481 #define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB 0x187d8
2485 #define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB 0x187dc
2488 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2489 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2490 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2491 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2492 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2495 #define NIG_REG_P0_TLLH_PTP_PARAM_MASK 0x187f0
2497 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2498 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2499 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2500 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2501 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2502 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2505 #define NIG_REG_P0_TLLH_PTP_RULE_MASK 0x187f4
2507 * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
2511 * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
2513 #define NIG_REG_P1_TLLH_PTP_BUF_SEQID 0x187ec
2517 #define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB 0x187e4
2521 #define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB 0x187e8
2524 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
2525 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
2526 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
2527 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
2528 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
2531 #define NIG_REG_P1_TLLH_PTP_PARAM_MASK 0x187f8
2533 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
2534 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
2535 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
2536 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
2537 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
2538 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
2541 #define NIG_REG_P1_TLLH_PTP_RULE_MASK 0x187fc
2543 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
2544 * for client 0; bits [35:32] are for client 8. For clients that are not
2548 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2549 * use credit registers 0-5 respectively (0x543210876). Note that credit
2552 * credit registers 0-5 are valid. This register should be configured
2554 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8
2556 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are
2557 * for client 0; bits [35:32] are for client 8. For clients that are not
2561 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to
2562 * use credit registers 0-5 respectively (0x543210876). Note that credit
2565 * credit registers 0-5 are valid. This register should be configured
2567 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec
2570 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic
2574 #define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234
2577 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port;
2580 * 0 for not using WFQ credit blocking. */
2581 #define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238
2582 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258
2583 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c
2584 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260
2585 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264
2586 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268
2587 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4
2588 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0
2590 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244
2591 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248
2592 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c
2593 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250
2594 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254
2595 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0
2597 two round-robin arbitration slots to avoid starvation. A value of 0 means
2600 #define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240
2602 strict priority arbiter. This register specifies bits 31:0 of the 36-bit
2603 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2605 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2607 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2608 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2610 is the same as the one for port 0, except that port 1 only has COS 0-2
2612 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0
2615 value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
2617 the following IDs: 0-management; 1-debug traffic from this port; 2-debug
2619 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is
2620 set to 0x345678021. This is a new register (with 2_) added in E3 B0 to
2622 is the same as the one for port 0, except that port 1 only has COS 0-2
2624 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4
2626 #define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594
2632 #define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f8
2635 #define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8
2636 /* [RW 32] Specify the upper bound that credit register 0 is allowed to
2639 ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same
2641 #define NIG_REG_PAUSE_ENABLE_0 0x160c0
2642 #define NIG_REG_PAUSE_ENABLE_1 0x160c4
2644 #define NIG_REG_PBF_LB_IN_EN 0x100b4
2647 #define NIG_REG_PORT_SWAP 0x10394
2649 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the
2651 #define NIG_REG_PPP_ENABLE_0 0x160b0
2652 #define NIG_REG_PPP_ENABLE_1 0x160b4
2654 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
2656 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
2658 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370
2659 /* [RW 1] control to serdes; 0 - clause 45; 1 - clause 22 */
2660 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c
2662 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
2664 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
2667 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
2670 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8
2673 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750
2676 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760
2679 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
2682 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0
2685 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0
2687 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
2688 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
2689 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
2690 /* [RW 1] port swap mux selection. If this register equal to 0 then port
2693 #define NIG_REG_STRAP_OVERRIDE 0x10398
2697 #define NIG_REG_TIMESYNC_GEN_REG 0x18800
2699 #define NIG_REG_XCM0_OUT_EN 0x100f0
2701 #define NIG_REG_XCM1_OUT_EN 0x100f4
2703 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348
2705 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
2706 /* [RW 1] control to xgxs; 0 - clause 45; 1 - clause 22 */
2707 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338
2709 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
2711 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
2713 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
2714 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
2715 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
2716 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
2717 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
2718 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1<<0)
2719 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
2720 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
2721 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
2724 #define PBF_REG_COS0_UPPER_BOUND 0x15c05c
2726 * of port 0. */
2727 #define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc
2730 #define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4
2732 #define PBF_REG_COS0_WEIGHT 0x15c054
2733 /* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */
2734 #define PBF_REG_COS0_WEIGHT_P0 0x15c2a8
2736 #define PBF_REG_COS0_WEIGHT_P1 0x15c2c0
2738 #define PBF_REG_COS1_UPPER_BOUND 0x15c060
2740 #define PBF_REG_COS1_WEIGHT 0x15c058
2741 /* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */
2742 #define PBF_REG_COS1_WEIGHT_P0 0x15c2ac
2744 #define PBF_REG_COS1_WEIGHT_P1 0x15c2c4
2745 /* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */
2746 #define PBF_REG_COS2_WEIGHT_P0 0x15c2b0
2748 #define PBF_REG_COS2_WEIGHT_P1 0x15c2c8
2749 /* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */
2750 #define PBF_REG_COS3_WEIGHT_P0 0x15c2b4
2751 /* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */
2752 #define PBF_REG_COS4_WEIGHT_P0 0x15c2b8
2753 /* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */
2754 #define PBF_REG_COS5_WEIGHT_P0 0x15c2bc
2757 #define PBF_REG_CREDIT_LB_Q 0x140338
2758 /* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte
2760 #define PBF_REG_CREDIT_Q0 0x14033c
2763 #define PBF_REG_CREDIT_Q1 0x140340
2764 /* [RW 1] Disable processing further tasks from port 0 (after ending the
2766 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
2769 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
2772 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
2773 #define PBF_REG_DISABLE_PF 0x1402e8
2774 #define PBF_REG_DISABLE_VF 0x1402ec
2775 /* [RW 18] For port 0: For each client that is subject to WFQ (the
2779 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288
2784 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c
2785 /* [RW 6] For port 0: Bit per client to indicate if the client competes in
2787 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2789 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278
2792 * goes to the RR arbiter (corresponding bit = 0); and then competes in the
2794 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c
2795 /* [RW 6] For port 0: Bit per client to indicate if the client is subject to
2797 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280
2798 /* [RW 3] For port 0: Bit per client to indicate if the client is subject to
2800 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284
2801 /* [RW 16] For port 0: The number of strict priority arbitration slots
2802 * between 2 RR arbitration slots. A value of 0 means no strict priority
2805 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0
2807 * between 2 RR arbitration slots. A value of 0 means no strict priority
2810 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4
2811 /* [RW 18] For port 0: Indicates which client is connected to each priority
2812 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2815 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270
2817 * in the strict-priority arbiter. Priority 0 is the highest priority, and
2820 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274
2824 #define PBF_REG_ETS_ENABLED 0x15c050
2827 #define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8
2828 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
2829 #define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8
2832 #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c
2833 #define PBF_REG_IF_ENABLE_REG 0x140044
2837 #define PBF_REG_INIT 0x140000
2840 #define PBF_REG_INIT_CRD_LB_Q 0x15c248
2841 /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte
2843 #define PBF_REG_INIT_CRD_Q0 0x15c230
2846 #define PBF_REG_INIT_CRD_Q1 0x15c234
2847 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
2850 #define PBF_REG_INIT_P0 0x140004
2854 #define PBF_REG_INIT_P1 0x140008
2858 #define PBF_REG_INIT_P4 0x14000c
2861 #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354
2863 * queue 0. Reset upon init. */
2864 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358
2867 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c
2868 /* [RW 1] Enable for mac interface 0. */
2869 #define PBF_REG_MAC_IF0_ENABLE 0x140030
2871 #define PBF_REG_MAC_IF1_ENABLE 0x140034
2873 #define PBF_REG_MAC_LB_ENABLE 0x140040
2875 #define PBF_REG_MUST_HAVE_HDRS 0x15c0c4
2877 * arbitration slots. A value of 0 means no strict priority cycles; i.e. the
2879 #define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064
2880 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
2882 #define PBF_REG_P0_ARB_THRSH 0x1400e4
2883 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
2884 #define PBF_REG_P0_CREDIT 0x140200
2885 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
2887 #define PBF_REG_P0_INIT_CRD 0x1400d0
2889 * port 0. Reset upon init. */
2890 #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308
2891 /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */
2892 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
2893 /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */
2894 #define PBF_REG_P0_TASK_CNT 0x140204
2896 * freed from the task queue of port 0. Reset upon init. */
2897 #define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0
2898 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */
2899 #define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc
2902 #define PBF_REG_P1_CREDIT 0x140208
2903 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port
2905 #define PBF_REG_P1_INIT_CRD 0x1400d4
2908 #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c
2910 #define PBF_REG_P1_TASK_CNT 0x14020c
2913 #define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4
2915 #define PBF_REG_P1_TQ_OCCUPANCY 0x140300
2917 #define PBF_REG_P4_CREDIT 0x140210
2920 #define PBF_REG_P4_INIT_CRD 0x1400e0
2923 #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310
2925 #define PBF_REG_P4_TASK_CNT 0x140214
2928 #define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8
2930 #define PBF_REG_P4_TQ_OCCUPANCY 0x140304
2931 /* [RW 5] Interrupt mask register #0 read/write */
2932 #define PBF_REG_PBF_INT_MASK 0x1401d4
2933 /* [R 5] Interrupt register #0 read */
2934 #define PBF_REG_PBF_INT_STS 0x1401c8
2935 /* [RW 20] Parity mask register #0 read/write */
2936 #define PBF_REG_PBF_PRTY_MASK 0x1401e4
2937 /* [R 28] Parity register #0 read */
2938 #define PBF_REG_PBF_PRTY_STS 0x1401d8
2939 /* [RC 20] Parity register #0 read clear */
2940 #define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc
2941 /* [RW 16] The Ethernet type value for L2 tag 0 */
2942 #define PBF_REG_TAG_ETHERTYPE_0 0x15c090
2943 /* [RW 4] The length of the info field for L2 tag 0. The length is between
2945 #define PBF_REG_TAG_LEN_0 0x15c09c
2948 #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c
2950 * queue 0. Reset upon init. */
2951 #define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390
2954 #define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394
2957 #define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8
2958 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */
2959 #define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac
2961 #define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0
2964 * Reset value is 0x8100 which is the standard VLAN type. Note that when
2965 * checking second VLAN; type is compared only to 0x8100.
2967 #define PBF_REG_VLAN_TYPE_0 0x15c06c
2968 /* [RW 2] Interrupt mask register #0 read/write */
2969 #define PB_REG_PB_INT_MASK 0x28
2970 /* [R 2] Interrupt register #0 read */
2971 #define PB_REG_PB_INT_STS 0x1c
2972 /* [RW 4] Parity mask register #0 read/write */
2973 #define PB_REG_PB_PRTY_MASK 0x38
2974 /* [R 4] Parity register #0 read */
2975 #define PB_REG_PB_PRTY_STS 0x2c
2976 /* [RC 4] Parity register #0 read clear */
2977 #define PB_REG_PB_PRTY_STS_CLR 0x30
2978 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2979 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1<<8)
2980 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1<<1)
2981 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1<<6)
2982 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1<<7)
2983 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1<<4)
2984 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1<<3)
2985 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1<<5)
2986 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1<<2)
2991 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010
2996 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014
2997 /* [RW 1] Type A PF enable inbound interrupt table for CSDM. 0 - disable; 1
2999 #define PGLUE_B_REG_CSDM_INB_INT_A_PF_ENABLE 0x9194
3001 * its[8:0]-address. Bits [1:0] must be zero (DW resolution address). */
3002 #define PGLUE_B_REG_CSDM_INB_INT_B_VF 0x916c
3003 /* [RW 1] Type B VF enable inbound interrupt table for CSDM. 0 - disable; 1
3005 #define PGLUE_B_REG_CSDM_INB_INT_B_VF_ENABLE 0x919c
3007 #define PGLUE_B_REG_CSDM_START_OFFSET_A 0x9100
3009 #define PGLUE_B_REG_CSDM_START_OFFSET_B 0x9108
3011 #define PGLUE_B_REG_CSDM_VF_SHIFT_B 0x9110
3012 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3013 #define PGLUE_B_REG_CSDM_ZONE_A_SIZE_PF 0x91ac
3014 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates
3018 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028
3019 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1
3023 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418
3027 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024
3028 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit
3031 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018
3035 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c
3039 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020
3041 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target
3049 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068
3050 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c
3051 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430
3052 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE 0x9434
3053 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438
3055 * details register and enables logging new error details. Bit 0 - clears
3063 #define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x943c
3065 /* [R 9] Interrupt register #0 read */
3066 #define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298
3067 /* [RC 9] Interrupt register #0 read clear */
3068 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c
3069 /* [RW 2] Parity mask register #0 read/write */
3070 #define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4
3071 /* [R 2] Parity register #0 read */
3072 #define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8
3073 /* [RC 2] Parity register #0 read clear */
3074 #define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac
3075 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] -
3076 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion
3081 #define PGLUE_B_REG_RX_ERR_DETAILS 0x9080
3083 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code -
3084 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 -
3088 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084
3089 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to
3093 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458
3095 * VF enable register of the corresponding PF is written to 0 and was
3099 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030
3100 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read
3102 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. */
3103 #define PGLUE_B_REG_TAGS_63_32 0x9244
3104 /* [RW 1] Type A PF enable inbound interrupt table for TSDM. 0 - disable; 1
3106 #define PGLUE_B_REG_TSDM_INB_INT_A_PF_ENABLE 0x9170
3108 #define PGLUE_B_REG_TSDM_START_OFFSET_A 0x90c4
3110 #define PGLUE_B_REG_TSDM_START_OFFSET_B 0x90cc
3112 #define PGLUE_B_REG_TSDM_VF_SHIFT_B 0x90d4
3113 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3114 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF 0x91a0
3115 /* [R 32] Address [31:0] of first read request not submitted due to error */
3116 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098
3118 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c
3119 /* [R 31] Details of first read request not submitted due to error. [4:0]
3123 #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0
3124 /* [R 26] Details of first read request not submitted due to error. [15:0]
3131 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4
3132 /* [R 32] Address [31:0] of first write request not submitted due to error */
3133 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088
3135 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c
3136 /* [R 31] Details of first write request not submitted due to error. [4:0]
3139 #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090
3140 /* [R 26] Details of first write request not submitted due to error. [15:0]
3147 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094
3149 * its[4:0]-address relative to start_offset_a. Bits [1:0] can have any
3151 #define PGLUE_B_REG_USDM_INB_INT_A_0 0x9128
3152 #define PGLUE_B_REG_USDM_INB_INT_A_1 0x912c
3153 #define PGLUE_B_REG_USDM_INB_INT_A_2 0x9130
3154 #define PGLUE_B_REG_USDM_INB_INT_A_3 0x9134
3155 #define PGLUE_B_REG_USDM_INB_INT_A_4 0x9138
3156 #define PGLUE_B_REG_USDM_INB_INT_A_5 0x913c
3157 #define PGLUE_B_REG_USDM_INB_INT_A_6 0x9140
3158 /* [RW 1] Type A PF enable inbound interrupt table for USDM. 0 - disable; 1
3160 #define PGLUE_B_REG_USDM_INB_INT_A_PF_ENABLE 0x917c
3161 /* [RW 1] Type A VF enable inbound interrupt table for USDM. 0 - disable; 1
3163 #define PGLUE_B_REG_USDM_INB_INT_A_VF_ENABLE 0x9180
3164 /* [RW 1] Type B VF enable inbound interrupt table for USDM. 0 - disable; 1
3166 #define PGLUE_B_REG_USDM_INB_INT_B_VF_ENABLE 0x9184
3168 #define PGLUE_B_REG_USDM_START_OFFSET_A 0x90d8
3170 #define PGLUE_B_REG_USDM_START_OFFSET_B 0x90e0
3172 #define PGLUE_B_REG_USDM_VF_SHIFT_B 0x90e8
3173 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3174 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF 0x91a4
3176 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write.
3181 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234
3183 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address).
3189 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230
3190 /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates
3194 #define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c
3195 /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1
3198 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470
3203 #define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078
3207 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474
3208 /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit
3212 #define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c
3213 /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes
3216 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478
3221 #define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070
3225 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c
3230 #define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074
3234 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480
3235 /* [RW 1] Type A PF enable inbound interrupt table for XSDM. 0 - disable; 1
3237 #define PGLUE_B_REG_XSDM_INB_INT_A_PF_ENABLE 0x9188
3239 #define PGLUE_B_REG_XSDM_START_OFFSET_A 0x90ec
3241 #define PGLUE_B_REG_XSDM_START_OFFSET_B 0x90f4
3243 #define PGLUE_B_REG_XSDM_VF_SHIFT_B 0x90fc
3244 /* [RW 1] 0 - Zone A size is 136x32B; 1 - Zone A size is 152x32B. */
3245 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF 0x91a8
3246 #define PRS_REG_A_PRSU_20 0x40134
3248 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
3250 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
3253 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
3254 /* [RW 24] CID for port 0 if no match */
3255 #define PRS_REG_CID_PORT_0 0x400fc
3257 load response is reset and packet type is 0. Used in packet start message
3259 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
3260 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
3261 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
3262 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
3263 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
3264 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5 0x400f0
3266 load response is set and packet type is 0. Used in packet start message
3268 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
3269 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
3270 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
3271 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
3272 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
3273 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5 0x400d0
3276 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
3277 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
3278 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
3279 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
3280 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
3282 #define PRS_REG_CM_HDR_TYPE_0 0x40078
3283 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
3284 #define PRS_REG_CM_HDR_TYPE_2 0x40080
3285 #define PRS_REG_CM_HDR_TYPE_3 0x40084
3286 #define PRS_REG_CM_HDR_TYPE_4 0x40088
3288 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
3289 /* [RW 1] Indicates if in e1hov mode. 0=non-e1hov mode; 1=e1hov mode. */
3290 #define PRS_REG_E1HOV_MODE 0x401c8
3293 #define PRS_REG_EVENT_ID_1 0x40054
3294 #define PRS_REG_EVENT_ID_2 0x40058
3295 #define PRS_REG_EVENT_ID_3 0x4005c
3297 #define PRS_REG_FCOE_TYPE 0x401d0
3298 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
3300 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
3301 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
3302 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
3303 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
3304 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
3305 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
3306 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
3307 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
3310 #define PRS_REG_HDRS_AFTER_BASIC 0x40238
3312 * Ethernet header for port 0 packets. */
3313 #define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270
3314 #define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290
3315 /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */
3316 #define PRS_REG_HDRS_AFTER_TAG_0 0x40248
3317 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for
3318 * port 0 packets */
3319 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280
3320 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0
3322 #define PRS_REG_INC_VALUE 0x40048
3324 #define PRS_REG_MUST_HAVE_HDRS 0x40254
3326 * port 0 packets */
3327 #define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c
3328 #define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac
3329 #define PRS_REG_NIC_MODE 0x40138
3332 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
3334 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
3337 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
3339 #define PRS_REG_NUM_OF_PACKETS 0x40124
3341 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
3343 packet type 0. Used in CFC load request message */
3344 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
3345 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
3346 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
3347 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
3348 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
3349 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
3350 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
3351 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
3352 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
3353 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
3355 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
3356 /* [R 1] Interrupt register #0 read */
3357 #define PRS_REG_PRS_INT_STS 0x40188
3358 /* [RW 8] Parity mask register #0 read/write */
3359 #define PRS_REG_PRS_PRTY_MASK 0x401a4
3360 /* [R 8] Parity register #0 read */
3361 #define PRS_REG_PRS_PRTY_STS 0x40198
3362 /* [RC 8] Parity register #0 read clear */
3363 #define PRS_REG_PRS_PRTY_STS_CLR 0x4019c
3366 #define PRS_REG_PURE_REGIONS 0x40024
3370 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
3374 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
3376 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
3377 /* [RW 16] The Ethernet type value for L2 tag 0 */
3378 #define PRS_REG_TAG_ETHERTYPE_0 0x401d4
3379 /* [RW 4] The length of the info field for L2 tag 0. The length is between
3381 #define PRS_REG_TAG_LEN_0 0x4022c
3383 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
3385 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
3388 * Reset value is 0x8100 which is the standard VLAN type. Note that when
3389 * checking second VLAN; type is compared only to 0x8100.
3391 #define PRS_REG_VLAN_TYPE_0 0x401a8
3392 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1<<19)
3393 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1<<20)
3394 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1<<22)
3395 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1<<23)
3396 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1<<24)
3397 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
3398 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1<<7)
3400 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
3402 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
3403 #define PXP2_REG_PGL_ADDR_88_F0 0x120534
3404 /* [R 32] GRC address for configuration access to PCIE config address 0x88.
3407 #define PXP2_REG_PGL_ADDR_88_F1 0x120544
3408 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538
3409 /* [R 32] GRC address for configuration access to PCIE config address 0x8c.
3412 #define PXP2_REG_PGL_ADDR_8C_F1 0x120548
3413 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c
3414 /* [R 32] GRC address for configuration access to PCIE config address 0x90.
3417 #define PXP2_REG_PGL_ADDR_90_F1 0x12054c
3418 #define PXP2_REG_PGL_ADDR_94_F0 0x120540
3419 /* [R 32] GRC address for configuration access to PCIE config address 0x94.
3422 #define PXP2_REG_PGL_ADDR_94_F1 0x120550
3423 #define PXP2_REG_PGL_CONTROL0 0x120490
3424 #define PXP2_REG_PGL_CONTROL1 0x120514
3425 #define PXP2_REG_PGL_DEBUG 0x120520
3430 #define PXP2_REG_PGL_EXP_ROM2 0x120808
3432 its[15:0]-address */
3433 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
3434 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
3435 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
3436 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
3437 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
3438 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
3439 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
3440 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
3442 its[15:0]-address */
3443 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
3444 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
3445 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
3446 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
3447 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
3448 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
3449 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
3450 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
3452 its[15:0]-address */
3453 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
3454 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
3455 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
3456 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
3457 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
3458 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
3459 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
3460 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
3462 its[15:0]-address */
3463 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
3464 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
3465 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
3466 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
3467 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
3468 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
3469 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
3470 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
3476 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674
3477 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678
3478 #define PXP2_REG_PGL_PRETEND_FUNC_F2 0x12067c
3479 #define PXP2_REG_PGL_PRETEND_FUNC_F3 0x120680
3480 #define PXP2_REG_PGL_PRETEND_FUNC_F4 0x120684
3481 #define PXP2_REG_PGL_PRETEND_FUNC_F5 0x120688
3482 #define PXP2_REG_PGL_PRETEND_FUNC_F6 0x12068c
3483 #define PXP2_REG_PGL_PRETEND_FUNC_F7 0x120690
3486 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
3487 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8
3489 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
3492 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
3493 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
3494 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
3495 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
3496 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
3497 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
3498 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
3499 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
3500 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
3501 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
3502 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
3503 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
3504 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
3505 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
3506 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
3507 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
3508 #define PXP2_REG_PSWRQ_BW_L28 0x120318
3509 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
3510 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
3511 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
3512 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
3513 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
3514 #define PXP2_REG_PSWRQ_BW_RD 0x120324
3515 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
3516 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
3517 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
3518 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
3519 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
3520 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
3521 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
3522 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
3523 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
3524 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
3525 #define PXP2_REG_PSWRQ_BW_WR 0x120328
3526 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
3527 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
3528 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
3529 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
3530 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0
3531 /* [RW 32] Interrupt mask register #0 read/write */
3532 #define PXP2_REG_PXP2_INT_MASK_0 0x120578
3533 /* [R 32] Interrupt register #0 read */
3534 #define PXP2_REG_PXP2_INT_STS_0 0x12056c
3535 #define PXP2_REG_PXP2_INT_STS_1 0x120608
3536 /* [RC 32] Interrupt register #0 read clear */
3537 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570
3538 /* [RW 32] Parity mask register #0 read/write */
3539 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
3540 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
3541 /* [R 32] Parity register #0 read */
3542 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
3543 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
3544 /* [RC 32] Parity register #0 read clear */
3545 #define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580
3546 #define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590
3549 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
3551 #define PXP2_REG_RD_BLK_CNT 0x120418
3554 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
3556 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
3558 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
3560 #define PXP2_REG_RD_INIT_DONE 0x120370
3563 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
3566 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
3569 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
3572 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
3575 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
3578 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
3581 #define PXP2_REG_RD_MAX_BLKS_VQ25 0x1203dc
3584 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
3587 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
3589 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
3591 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
3592 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
3594 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
3596 #define PXP2_REG_RD_SR_CNT 0x120414
3598 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
3601 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
3603 #define PXP2_REG_RD_START_INIT 0x12036c
3605 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
3607 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
3609 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
3611 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
3613 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
3615 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
3617 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
3619 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
3621 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
3623 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
3625 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
3627 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
3629 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
3631 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
3633 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
3635 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
3637 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
3639 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
3641 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
3643 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
3645 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
3647 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
3649 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
3651 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
3653 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
3655 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
3657 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
3659 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
3661 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
3663 #define PXP2_REG_RQ_BW_RD_L22 0x120300
3665 #define PXP2_REG_RQ_BW_RD_L23 0x120304
3667 #define PXP2_REG_RQ_BW_RD_L24 0x120308
3669 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
3671 #define PXP2_REG_RQ_BW_RD_L26 0x120310
3673 #define PXP2_REG_RQ_BW_RD_L27 0x120314
3675 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
3677 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
3679 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
3681 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
3683 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
3685 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
3687 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
3689 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
3691 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
3693 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
3695 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
3697 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
3699 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
3701 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
3703 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
3705 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
3707 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
3709 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
3711 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
3713 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
3715 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
3717 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
3719 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
3721 #define PXP2_REG_RQ_BW_WR_L30 0x120320
3723 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
3725 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
3726 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */
3727 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008
3729 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
3730 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c
3731 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620
3734 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
3737 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
3739 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
3742 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
3744 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3746 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0
3748 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B
3750 #define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c
3753 #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930
3756 #define PXP2_REG_RQ_ELT_DISABLE 0x12066c
3758 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
3759 /* [RW 1] when '0' ILT logic will work as in A0; otherwise B0; for back
3761 #define PXP2_REG_RQ_ILT_MODE 0x1205b4
3763 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
3765 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000
3767 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
3769 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
3770 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634
3771 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638
3774 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
3776 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
3777 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
3779 #define PXP2_REG_RQ_RD_MBS0 0x120160
3782 #define PXP2_REG_RQ_RD_MBS1 0x120168
3784 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
3785 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c
3786 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640
3789 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
3791 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
3792 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644
3793 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648
3796 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
3798 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
3799 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */
3800 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094
3801 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
3802 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
3804 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
3806 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
3808 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
3810 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
3812 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
3814 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
3816 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
3818 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
3820 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
3822 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
3824 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
3826 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
3828 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
3830 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
3832 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
3834 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
3836 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
3838 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
3840 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
3842 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
3844 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
3846 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
3848 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
3850 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
3852 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
3854 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
3856 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
3858 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
3860 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
3862 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
3864 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
3865 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
3867 #define PXP2_REG_RQ_WR_MBS0 0x12015c
3870 #define PXP2_REG_RQ_WR_MBS1 0x120164
3871 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3873 #define PXP2_REG_WR_CDU_MPS 0x1205f0
3874 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3876 #define PXP2_REG_WR_CSDM_MPS 0x1205d0
3877 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3879 #define PXP2_REG_WR_DBG_MPS 0x1205e8
3880 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3882 #define PXP2_REG_WR_DMAE_MPS 0x1205ec
3886 #define PXP2_REG_WR_DMAE_TH 0x120368
3887 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3889 #define PXP2_REG_WR_HC_MPS 0x1205c8
3890 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3892 #define PXP2_REG_WR_QM_MPS 0x1205dc
3893 /* [RW 1] 0 - working in A0 mode; - working in B0 mode */
3894 #define PXP2_REG_WR_REV_MODE 0x120670
3895 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3897 #define PXP2_REG_WR_SRC_MPS 0x1205e4
3898 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3900 #define PXP2_REG_WR_TM_MPS 0x1205e0
3901 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3903 #define PXP2_REG_WR_TSDM_MPS 0x1205d4
3907 #define PXP2_REG_WR_USDMDP_TH 0x120348
3908 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3910 #define PXP2_REG_WR_USDM_MPS 0x1205cc
3911 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the
3913 #define PXP2_REG_WR_XSDM_MPS 0x1205d8
3915 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
3918 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
3921 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4
3925 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0
3928 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8
3933 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c
3935 #define PXP_REG_HST_INBOUND_INT 0x103800
3937 * VFID[5:0]}
3939 #define PXP_REG_HST_ZONE_PERMISSION_TABLE 0x103400
3940 /* [RW 32] Interrupt mask register #0 read/write */
3941 #define PXP_REG_PXP_INT_MASK_0 0x103074
3942 #define PXP_REG_PXP_INT_MASK_1 0x103084
3943 /* [R 32] Interrupt register #0 read */
3944 #define PXP_REG_PXP_INT_STS_0 0x103068
3945 #define PXP_REG_PXP_INT_STS_1 0x103078
3946 /* [RC 32] Interrupt register #0 read clear */
3947 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
3948 #define PXP_REG_PXP_INT_STS_CLR_1 0x10307c
3949 /* [RW 27] Parity mask register #0 read/write */
3950 #define PXP_REG_PXP_PRTY_MASK 0x103094
3951 /* [R 26] Parity register #0 read */
3952 #define PXP_REG_PXP_PRTY_STS 0x103088
3953 /* [RC 27] Parity register #0 read clear */
3954 #define PXP_REG_PXP_PRTY_STS_CLR 0x10308c
3957 #define QM_REG_ACTCTRINITVAL_0 0x168040
3958 #define QM_REG_ACTCTRINITVAL_1 0x168044
3959 #define QM_REG_ACTCTRINITVAL_2 0x168048
3960 #define QM_REG_ACTCTRINITVAL_3 0x16804c
3964 queues 63-0 */
3965 #define QM_REG_BASEADDR 0x168900
3970 #define QM_REG_BASEADDR_EXT_A 0x16e100
3972 #define QM_REG_BYTECRDCOST 0x168234
3974 #define QM_REG_BYTECRDINITVAL 0x168238
3976 queue uses port 0 else it uses port 1; queues 31-0 */
3977 #define QM_REG_BYTECRDPORT_LSB 0x168228
3979 queue uses port 0 else it uses port 1; queues 95-64 */
3980 #define QM_REG_BYTECRDPORT_LSB_EXT_A 0x16e520
3982 queue uses port 0 else it uses port 1; queues 63-32 */
3983 #define QM_REG_BYTECRDPORT_MSB 0x168224
3985 queue uses port 0 else it uses port 1; queues 127-96 */
3986 #define QM_REG_BYTECRDPORT_MSB_EXT_A 0x16e51c
3989 #define QM_REG_BYTECREDITAFULLTHR 0x168094
3991 #define QM_REG_CMINITCRD_0 0x1680cc
3992 #define QM_REG_BYTECRDCMDQ_0 0x16e6e8
3993 #define QM_REG_CMINITCRD_1 0x1680d0
3994 #define QM_REG_CMINITCRD_2 0x1680d4
3995 #define QM_REG_CMINITCRD_3 0x1680d8
3996 #define QM_REG_CMINITCRD_4 0x1680dc
3997 #define QM_REG_CMINITCRD_5 0x1680e0
3998 #define QM_REG_CMINITCRD_6 0x1680e4
3999 #define QM_REG_CMINITCRD_7 0x1680e8
4000 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
4002 #define QM_REG_CMINTEN 0x1680ec
4004 interface 0 */
4005 #define QM_REG_CMINTVOQMASK_0 0x1681f4
4006 #define QM_REG_CMINTVOQMASK_1 0x1681f8
4007 #define QM_REG_CMINTVOQMASK_2 0x1681fc
4008 #define QM_REG_CMINTVOQMASK_3 0x168200
4009 #define QM_REG_CMINTVOQMASK_4 0x168204
4010 #define QM_REG_CMINTVOQMASK_5 0x168208
4011 #define QM_REG_CMINTVOQMASK_6 0x16820c
4012 #define QM_REG_CMINTVOQMASK_7 0x168210
4015 #define QM_REG_CONNNUM_0 0x168020
4017 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
4019 #define QM_REG_CTXREG_0 0x168030
4020 #define QM_REG_CTXREG_1 0x168034
4021 #define QM_REG_CTXREG_2 0x168038
4022 #define QM_REG_CTXREG_3 0x16803c
4025 #define QM_REG_ENBYPVOQMASK 0x16823c
4027 physical queue uses the byte credit; queues 31-0 */
4028 #define QM_REG_ENBYTECRD_LSB 0x168220
4031 #define QM_REG_ENBYTECRD_LSB_EXT_A 0x16e518
4034 #define QM_REG_ENBYTECRD_MSB 0x16821c
4037 #define QM_REG_ENBYTECRD_MSB_EXT_A 0x16e514
4040 #define QM_REG_ENSEC 0x1680f0
4042 #define QM_REG_FUNCNUMSEL_LSB 0x168230
4044 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
4046 be use for the almost empty indication to the HW block; queues 31:0 */
4047 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
4050 #define QM_REG_HWAEMPTYMASK_LSB_EXT_A 0x16e510
4053 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
4056 #define QM_REG_HWAEMPTYMASK_MSB_EXT_A 0x16e50c
4058 #define QM_REG_OUTLDREQ 0x168804
4061 #define QM_REG_OVFERROR 0x16805c
4063 #define QM_REG_OVFQNUM 0x168058
4064 /* [R 16] Pause state for physical queues 15-0 */
4065 #define QM_REG_PAUSESTATE0 0x168410
4067 #define QM_REG_PAUSESTATE1 0x168414
4069 #define QM_REG_PAUSESTATE2 0x16e684
4071 #define QM_REG_PAUSESTATE3 0x16e688
4073 #define QM_REG_PAUSESTATE4 0x16e68c
4075 #define QM_REG_PAUSESTATE5 0x16e690
4077 #define QM_REG_PAUSESTATE6 0x16e694
4079 #define QM_REG_PAUSESTATE7 0x16e698
4081 #define QM_REG_PCIREQAT 0x168054
4082 #define QM_REG_PF_EN 0x16e70c
4084 * functions are valid in E2 (odd I registers will be hard wired to 0) */
4085 #define QM_REG_PF_USG_CNT_0 0x16e040
4087 #define QM_REG_PORT0BYTECRD 0x168300
4089 #define QM_REG_PORT1BYTECRD 0x168304
4090 /* [RW 3] pci function number of queues 15-0 */
4091 #define QM_REG_PQ2PCIFUNC_0 0x16e6bc
4092 #define QM_REG_PQ2PCIFUNC_1 0x16e6c0
4093 #define QM_REG_PQ2PCIFUNC_2 0x16e6c4
4094 #define QM_REG_PQ2PCIFUNC_3 0x16e6c8
4095 #define QM_REG_PQ2PCIFUNC_4 0x16e6cc
4096 #define QM_REG_PQ2PCIFUNC_5 0x16e6d0
4097 #define QM_REG_PQ2PCIFUNC_6 0x16e6d4
4098 #define QM_REG_PQ2PCIFUNC_7 0x16e6d8
4099 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow:
4101 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
4102 #define QM_REG_PTRTBL 0x168a00
4105 bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
4106 #define QM_REG_PTRTBL_EXT_A 0x16e200
4107 /* [RW 2] Interrupt mask register #0 read/write */
4108 #define QM_REG_QM_INT_MASK 0x168444
4109 /* [R 2] Interrupt register #0 read */
4110 #define QM_REG_QM_INT_STS 0x168438
4111 /* [RW 12] Parity mask register #0 read/write */
4112 #define QM_REG_QM_PRTY_MASK 0x168454
4113 /* [R 12] Parity register #0 read */
4114 #define QM_REG_QM_PRTY_STS 0x168448
4115 /* [RC 12] Parity register #0 read clear */
4116 #define QM_REG_QM_PRTY_STS_CLR 0x16844c
4118 #define QM_REG_QSTATUS_HIGH 0x16802c
4120 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408
4121 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
4122 #define QM_REG_QSTATUS_LOW 0x168028
4124 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404
4125 /* [R 24] The number of tasks queued for each queue; queues 63-0 */
4126 #define QM_REG_QTASKCTR_0 0x168308
4128 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584
4130 #define QM_REG_QVOQIDX_0 0x1680f4
4131 #define QM_REG_QVOQIDX_10 0x16811c
4132 #define QM_REG_QVOQIDX_100 0x16e49c
4133 #define QM_REG_QVOQIDX_101 0x16e4a0
4134 #define QM_REG_QVOQIDX_102 0x16e4a4
4135 #define QM_REG_QVOQIDX_103 0x16e4a8
4136 #define QM_REG_QVOQIDX_104 0x16e4ac
4137 #define QM_REG_QVOQIDX_105 0x16e4b0
4138 #define QM_REG_QVOQIDX_106 0x16e4b4
4139 #define QM_REG_QVOQIDX_107 0x16e4b8
4140 #define QM_REG_QVOQIDX_108 0x16e4bc
4141 #define QM_REG_QVOQIDX_109 0x16e4c0
4142 #define QM_REG_QVOQIDX_11 0x168120
4143 #define QM_REG_QVOQIDX_110 0x16e4c4
4144 #define QM_REG_QVOQIDX_111 0x16e4c8
4145 #define QM_REG_QVOQIDX_112 0x16e4cc
4146 #define QM_REG_QVOQIDX_113 0x16e4d0
4147 #define QM_REG_QVOQIDX_114 0x16e4d4
4148 #define QM_REG_QVOQIDX_115 0x16e4d8
4149 #define QM_REG_QVOQIDX_116 0x16e4dc
4150 #define QM_REG_QVOQIDX_117 0x16e4e0
4151 #define QM_REG_QVOQIDX_118 0x16e4e4
4152 #define QM_REG_QVOQIDX_119 0x16e4e8
4153 #define QM_REG_QVOQIDX_12 0x168124
4154 #define QM_REG_QVOQIDX_120 0x16e4ec
4155 #define QM_REG_QVOQIDX_121 0x16e4f0
4156 #define QM_REG_QVOQIDX_122 0x16e4f4
4157 #define QM_REG_QVOQIDX_123 0x16e4f8
4158 #define QM_REG_QVOQIDX_124 0x16e4fc
4159 #define QM_REG_QVOQIDX_125 0x16e500
4160 #define QM_REG_QVOQIDX_126 0x16e504
4161 #define QM_REG_QVOQIDX_127 0x16e508
4162 #define QM_REG_QVOQIDX_13 0x168128
4163 #define QM_REG_QVOQIDX_14 0x16812c
4164 #define QM_REG_QVOQIDX_15 0x168130
4165 #define QM_REG_QVOQIDX_16 0x168134
4166 #define QM_REG_QVOQIDX_17 0x168138
4167 #define QM_REG_QVOQIDX_21 0x168148
4168 #define QM_REG_QVOQIDX_22 0x16814c
4169 #define QM_REG_QVOQIDX_23 0x168150
4170 #define QM_REG_QVOQIDX_24 0x168154
4171 #define QM_REG_QVOQIDX_25 0x168158
4172 #define QM_REG_QVOQIDX_26 0x16815c
4173 #define QM_REG_QVOQIDX_27 0x168160
4174 #define QM_REG_QVOQIDX_28 0x168164
4175 #define QM_REG_QVOQIDX_29 0x168168
4176 #define QM_REG_QVOQIDX_30 0x16816c
4177 #define QM_REG_QVOQIDX_31 0x168170
4178 #define QM_REG_QVOQIDX_32 0x168174
4179 #define QM_REG_QVOQIDX_33 0x168178
4180 #define QM_REG_QVOQIDX_34 0x16817c
4181 #define QM_REG_QVOQIDX_35 0x168180
4182 #define QM_REG_QVOQIDX_36 0x168184
4183 #define QM_REG_QVOQIDX_37 0x168188
4184 #define QM_REG_QVOQIDX_38 0x16818c
4185 #define QM_REG_QVOQIDX_39 0x168190
4186 #define QM_REG_QVOQIDX_40 0x168194
4187 #define QM_REG_QVOQIDX_41 0x168198
4188 #define QM_REG_QVOQIDX_42 0x16819c
4189 #define QM_REG_QVOQIDX_43 0x1681a0
4190 #define QM_REG_QVOQIDX_44 0x1681a4
4191 #define QM_REG_QVOQIDX_45 0x1681a8
4192 #define QM_REG_QVOQIDX_46 0x1681ac
4193 #define QM_REG_QVOQIDX_47 0x1681b0
4194 #define QM_REG_QVOQIDX_48 0x1681b4
4195 #define QM_REG_QVOQIDX_49 0x1681b8
4196 #define QM_REG_QVOQIDX_5 0x168108
4197 #define QM_REG_QVOQIDX_50 0x1681bc
4198 #define QM_REG_QVOQIDX_51 0x1681c0
4199 #define QM_REG_QVOQIDX_52 0x1681c4
4200 #define QM_REG_QVOQIDX_53 0x1681c8
4201 #define QM_REG_QVOQIDX_54 0x1681cc
4202 #define QM_REG_QVOQIDX_55 0x1681d0
4203 #define QM_REG_QVOQIDX_56 0x1681d4
4204 #define QM_REG_QVOQIDX_57 0x1681d8
4205 #define QM_REG_QVOQIDX_58 0x1681dc
4206 #define QM_REG_QVOQIDX_59 0x1681e0
4207 #define QM_REG_QVOQIDX_6 0x16810c
4208 #define QM_REG_QVOQIDX_60 0x1681e4
4209 #define QM_REG_QVOQIDX_61 0x1681e8
4210 #define QM_REG_QVOQIDX_62 0x1681ec
4211 #define QM_REG_QVOQIDX_63 0x1681f0
4212 #define QM_REG_QVOQIDX_64 0x16e40c
4213 #define QM_REG_QVOQIDX_65 0x16e410
4214 #define QM_REG_QVOQIDX_69 0x16e420
4215 #define QM_REG_QVOQIDX_7 0x168110
4216 #define QM_REG_QVOQIDX_70 0x16e424
4217 #define QM_REG_QVOQIDX_71 0x16e428
4218 #define QM_REG_QVOQIDX_72 0x16e42c
4219 #define QM_REG_QVOQIDX_73 0x16e430
4220 #define QM_REG_QVOQIDX_74 0x16e434
4221 #define QM_REG_QVOQIDX_75 0x16e438
4222 #define QM_REG_QVOQIDX_76 0x16e43c
4223 #define QM_REG_QVOQIDX_77 0x16e440
4224 #define QM_REG_QVOQIDX_78 0x16e444
4225 #define QM_REG_QVOQIDX_79 0x16e448
4226 #define QM_REG_QVOQIDX_8 0x168114
4227 #define QM_REG_QVOQIDX_80 0x16e44c
4228 #define QM_REG_QVOQIDX_81 0x16e450
4229 #define QM_REG_QVOQIDX_85 0x16e460
4230 #define QM_REG_QVOQIDX_86 0x16e464
4231 #define QM_REG_QVOQIDX_87 0x16e468
4232 #define QM_REG_QVOQIDX_88 0x16e46c
4233 #define QM_REG_QVOQIDX_89 0x16e470
4234 #define QM_REG_QVOQIDX_9 0x168118
4235 #define QM_REG_QVOQIDX_90 0x16e474
4236 #define QM_REG_QVOQIDX_91 0x16e478
4237 #define QM_REG_QVOQIDX_92 0x16e47c
4238 #define QM_REG_QVOQIDX_93 0x16e480
4239 #define QM_REG_QVOQIDX_94 0x16e484
4240 #define QM_REG_QVOQIDX_95 0x16e488
4241 #define QM_REG_QVOQIDX_96 0x16e48c
4242 #define QM_REG_QVOQIDX_97 0x16e490
4243 #define QM_REG_QVOQIDX_98 0x16e494
4244 #define QM_REG_QVOQIDX_99 0x16e498
4246 #define QM_REG_SOFT_RESET 0x168428
4248 #define QM_REG_TASKCRDCOST_0 0x16809c
4249 #define QM_REG_TASKCRDCOST_1 0x1680a0
4250 #define QM_REG_TASKCRDCOST_2 0x1680a4
4251 #define QM_REG_TASKCRDCOST_4 0x1680ac
4252 #define QM_REG_TASKCRDCOST_5 0x1680b0
4254 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
4256 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
4258 #define QM_REG_VOQCRDERRREG 0x168408
4260 #define QM_REG_VOQCREDIT_0 0x1682d0
4261 #define QM_REG_VOQCREDIT_1 0x1682d4
4262 #define QM_REG_VOQCREDIT_4 0x1682e0
4264 #define QM_REG_VOQCREDITAFULLTHR 0x168090
4266 #define QM_REG_VOQINITCREDIT_0 0x168060
4267 #define QM_REG_VOQINITCREDIT_1 0x168064
4268 #define QM_REG_VOQINITCREDIT_2 0x168068
4269 #define QM_REG_VOQINITCREDIT_4 0x168070
4270 #define QM_REG_VOQINITCREDIT_5 0x168074
4272 #define QM_REG_VOQPORT_0 0x1682a0
4273 #define QM_REG_VOQPORT_1 0x1682a4
4274 #define QM_REG_VOQPORT_2 0x1682a8
4275 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4276 #define QM_REG_VOQQMASK_0_LSB 0x168240
4278 #define QM_REG_VOQQMASK_0_LSB_EXT_A 0x16e524
4280 #define QM_REG_VOQQMASK_0_MSB 0x168244
4282 #define QM_REG_VOQQMASK_0_MSB_EXT_A 0x16e528
4283 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4284 #define QM_REG_VOQQMASK_10_LSB 0x168290
4286 #define QM_REG_VOQQMASK_10_LSB_EXT_A 0x16e574
4288 #define QM_REG_VOQQMASK_10_MSB 0x168294
4290 #define QM_REG_VOQQMASK_10_MSB_EXT_A 0x16e578
4291 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4292 #define QM_REG_VOQQMASK_11_LSB 0x168298
4294 #define QM_REG_VOQQMASK_11_LSB_EXT_A 0x16e57c
4296 #define QM_REG_VOQQMASK_11_MSB 0x16829c
4298 #define QM_REG_VOQQMASK_11_MSB_EXT_A 0x16e580
4299 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4300 #define QM_REG_VOQQMASK_1_LSB 0x168248
4302 #define QM_REG_VOQQMASK_1_LSB_EXT_A 0x16e52c
4304 #define QM_REG_VOQQMASK_1_MSB 0x16824c
4306 #define QM_REG_VOQQMASK_1_MSB_EXT_A 0x16e530
4307 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4308 #define QM_REG_VOQQMASK_2_LSB 0x168250
4310 #define QM_REG_VOQQMASK_2_LSB_EXT_A 0x16e534
4312 #define QM_REG_VOQQMASK_2_MSB 0x168254
4314 #define QM_REG_VOQQMASK_2_MSB_EXT_A 0x16e538
4315 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4316 #define QM_REG_VOQQMASK_3_LSB 0x168258
4318 #define QM_REG_VOQQMASK_3_LSB_EXT_A 0x16e53c
4320 #define QM_REG_VOQQMASK_3_MSB_EXT_A 0x16e540
4321 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4322 #define QM_REG_VOQQMASK_4_LSB 0x168260
4324 #define QM_REG_VOQQMASK_4_LSB_EXT_A 0x16e544
4326 #define QM_REG_VOQQMASK_4_MSB 0x168264
4328 #define QM_REG_VOQQMASK_4_MSB_EXT_A 0x16e548
4329 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4330 #define QM_REG_VOQQMASK_5_LSB 0x168268
4332 #define QM_REG_VOQQMASK_5_LSB_EXT_A 0x16e54c
4334 #define QM_REG_VOQQMASK_5_MSB 0x16826c
4336 #define QM_REG_VOQQMASK_5_MSB_EXT_A 0x16e550
4337 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4338 #define QM_REG_VOQQMASK_6_LSB 0x168270
4340 #define QM_REG_VOQQMASK_6_LSB_EXT_A 0x16e554
4342 #define QM_REG_VOQQMASK_6_MSB 0x168274
4344 #define QM_REG_VOQQMASK_6_MSB_EXT_A 0x16e558
4345 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4346 #define QM_REG_VOQQMASK_7_LSB 0x168278
4348 #define QM_REG_VOQQMASK_7_LSB_EXT_A 0x16e55c
4350 #define QM_REG_VOQQMASK_7_MSB 0x16827c
4352 #define QM_REG_VOQQMASK_7_MSB_EXT_A 0x16e560
4353 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4354 #define QM_REG_VOQQMASK_8_LSB 0x168280
4356 #define QM_REG_VOQQMASK_8_LSB_EXT_A 0x16e564
4358 #define QM_REG_VOQQMASK_8_MSB 0x168284
4360 #define QM_REG_VOQQMASK_8_MSB_EXT_A 0x16e568
4361 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */
4362 #define QM_REG_VOQQMASK_9_LSB 0x168288
4364 #define QM_REG_VOQQMASK_9_LSB_EXT_A 0x16e56c
4366 #define QM_REG_VOQQMASK_9_MSB_EXT_A 0x16e570
4368 #define QM_REG_WRRWEIGHTS_0 0x16880c
4369 #define QM_REG_WRRWEIGHTS_1 0x168810
4370 #define QM_REG_WRRWEIGHTS_10 0x168814
4371 #define QM_REG_WRRWEIGHTS_11 0x168818
4372 #define QM_REG_WRRWEIGHTS_12 0x16881c
4373 #define QM_REG_WRRWEIGHTS_13 0x168820
4374 #define QM_REG_WRRWEIGHTS_14 0x168824
4375 #define QM_REG_WRRWEIGHTS_15 0x168828
4376 #define QM_REG_WRRWEIGHTS_16 0x16e000
4377 #define QM_REG_WRRWEIGHTS_17 0x16e004
4378 #define QM_REG_WRRWEIGHTS_18 0x16e008
4379 #define QM_REG_WRRWEIGHTS_19 0x16e00c
4380 #define QM_REG_WRRWEIGHTS_2 0x16882c
4381 #define QM_REG_WRRWEIGHTS_20 0x16e010
4382 #define QM_REG_WRRWEIGHTS_21 0x16e014
4383 #define QM_REG_WRRWEIGHTS_22 0x16e018
4384 #define QM_REG_WRRWEIGHTS_23 0x16e01c
4385 #define QM_REG_WRRWEIGHTS_24 0x16e020
4386 #define QM_REG_WRRWEIGHTS_25 0x16e024
4387 #define QM_REG_WRRWEIGHTS_26 0x16e028
4388 #define QM_REG_WRRWEIGHTS_27 0x16e02c
4389 #define QM_REG_WRRWEIGHTS_28 0x16e030
4390 #define QM_REG_WRRWEIGHTS_29 0x16e034
4391 #define QM_REG_WRRWEIGHTS_3 0x168830
4392 #define QM_REG_WRRWEIGHTS_30 0x16e038
4393 #define QM_REG_WRRWEIGHTS_31 0x16e03c
4394 #define QM_REG_WRRWEIGHTS_4 0x168834
4395 #define QM_REG_WRRWEIGHTS_5 0x168838
4396 #define QM_REG_WRRWEIGHTS_6 0x16883c
4397 #define QM_REG_WRRWEIGHTS_7 0x168840
4398 #define QM_REG_WRRWEIGHTS_8 0x168844
4399 #define QM_REG_WRRWEIGHTS_9 0x168848
4401 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
4403 #define SEM_FAST_REG_PARITY_RST 0x18840
4404 #define SRC_REG_COUNTFREE0 0x40500
4407 #define SRC_REG_E1HMF_ENABLE 0x404cc
4408 #define SRC_REG_FIRSTFREE0 0x40510
4409 #define SRC_REG_KEYRSS0_0 0x40408
4410 #define SRC_REG_KEYRSS0_7 0x40424
4411 #define SRC_REG_KEYRSS1_9 0x40454
4412 #define SRC_REG_KEYSEARCH_0 0x40458
4413 #define SRC_REG_KEYSEARCH_1 0x4045c
4414 #define SRC_REG_KEYSEARCH_2 0x40460
4415 #define SRC_REG_KEYSEARCH_3 0x40464
4416 #define SRC_REG_KEYSEARCH_4 0x40468
4417 #define SRC_REG_KEYSEARCH_5 0x4046c
4418 #define SRC_REG_KEYSEARCH_6 0x40470
4419 #define SRC_REG_KEYSEARCH_7 0x40474
4420 #define SRC_REG_KEYSEARCH_8 0x40478
4421 #define SRC_REG_KEYSEARCH_9 0x4047c
4422 #define SRC_REG_LASTFREE0 0x40530
4423 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
4425 #define SRC_REG_SOFT_RST 0x4049c
4426 /* [R 3] Interrupt register #0 read */
4427 #define SRC_REG_SRC_INT_STS 0x404ac
4428 /* [RW 3] Parity mask register #0 read/write */
4429 #define SRC_REG_SRC_PRTY_MASK 0x404c8
4430 /* [R 3] Parity register #0 read */
4431 #define SRC_REG_SRC_PRTY_STS 0x404bc
4432 /* [RC 3] Parity register #0 read clear */
4433 #define SRC_REG_SRC_PRTY_STS_CLR 0x404c0
4435 #define TCM_REG_CAM_OCCUP 0x5017c
4436 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4439 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
4440 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4443 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
4444 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4447 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
4448 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4451 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
4455 #define TCM_REG_CFC_INIT_CRD 0x50204
4456 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4459 #define TCM_REG_CP_WEIGHT 0x500c0
4460 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4463 #define TCM_REG_CSEM_IFEN 0x5002c
4466 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
4467 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4470 #define TCM_REG_CSEM_WEIGHT 0x500bc
4472 #define TCM_REG_ERR_EVNT_ID 0x500a0
4474 #define TCM_REG_ERR_TCM_HDR 0x5009c
4476 #define TCM_REG_EXPR_EVNT_ID 0x500a4
4480 #define TCM_REG_FIC0_INIT_CRD 0x5020c
4484 #define TCM_REG_FIC1_INIT_CRD 0x50210
4485 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
4489 #define TCM_REG_GR_ARB_TYPE 0x50114
4490 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
4493 #define TCM_REG_GR_LD0_PR 0x5011c
4494 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
4497 #define TCM_REG_GR_LD1_PR 0x50120
4501 data in the STORM context is always 0. Index _i stands for the connection
4503 #define TCM_REG_N_SM_CTX_LD_0 0x50050
4504 #define TCM_REG_N_SM_CTX_LD_1 0x50054
4505 #define TCM_REG_N_SM_CTX_LD_2 0x50058
4506 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
4507 #define TCM_REG_N_SM_CTX_LD_4 0x50060
4508 #define TCM_REG_N_SM_CTX_LD_5 0x50064
4509 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
4512 #define TCM_REG_PBF_IFEN 0x50024
4515 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
4516 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
4519 #define TCM_REG_PBF_WEIGHT 0x500b4
4520 #define TCM_REG_PHYS_QNUM0_0 0x500e0
4521 #define TCM_REG_PHYS_QNUM0_1 0x500e4
4522 #define TCM_REG_PHYS_QNUM1_0 0x500e8
4523 #define TCM_REG_PHYS_QNUM1_1 0x500ec
4524 #define TCM_REG_PHYS_QNUM2_0 0x500f0
4525 #define TCM_REG_PHYS_QNUM2_1 0x500f4
4526 #define TCM_REG_PHYS_QNUM3_0 0x500f8
4527 #define TCM_REG_PHYS_QNUM3_1 0x500fc
4528 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
4531 #define TCM_REG_PRS_IFEN 0x50020
4534 #define TCM_REG_PRS_LENGTH_MIS 0x50168
4535 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
4538 #define TCM_REG_PRS_WEIGHT 0x500b0
4540 #define TCM_REG_STOP_EVNT_ID 0x500a8
4543 #define TCM_REG_STORM_LENGTH_MIS 0x50160
4544 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
4547 #define TCM_REG_STORM_TCM_IFEN 0x50010
4548 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
4551 #define TCM_REG_STORM_WEIGHT 0x500ac
4552 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
4555 #define TCM_REG_TCM_CFC_IFEN 0x50040
4556 /* [RW 11] Interrupt mask register #0 read/write */
4557 #define TCM_REG_TCM_INT_MASK 0x501dc
4558 /* [R 11] Interrupt register #0 read */
4559 #define TCM_REG_TCM_INT_STS 0x501d0
4560 /* [RW 27] Parity mask register #0 read/write */
4561 #define TCM_REG_TCM_PRTY_MASK 0x501ec
4562 /* [R 27] Parity register #0 read */
4563 #define TCM_REG_TCM_PRTY_STS 0x501e0
4564 /* [RC 27] Parity register #0 read clear */
4565 #define TCM_REG_TCM_PRTY_STS_CLR 0x501e4
4566 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
4567 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
4570 #define TCM_REG_TCM_REG0_SZ 0x500d8
4571 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
4574 #define TCM_REG_TCM_STORM0_IFEN 0x50004
4575 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
4578 #define TCM_REG_TCM_STORM1_IFEN 0x50008
4579 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
4582 #define TCM_REG_TCM_TQM_IFEN 0x5000c
4584 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
4586 #define TCM_REG_TM_TCM_HDR 0x50098
4587 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
4590 #define TCM_REG_TM_TCM_IFEN 0x5001c
4591 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
4594 #define TCM_REG_TM_WEIGHT 0x500d0
4598 #define TCM_REG_TQM_INIT_CRD 0x5021c
4599 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
4602 #define TCM_REG_TQM_P_WEIGHT 0x500c8
4603 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
4606 #define TCM_REG_TQM_S_WEIGHT 0x500cc
4608 #define TCM_REG_TQM_TCM_HDR_P 0x50090
4610 #define TCM_REG_TQM_TCM_HDR_S 0x50094
4611 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
4614 #define TCM_REG_TQM_TCM_IFEN 0x50014
4615 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
4618 #define TCM_REG_TSDM_IFEN 0x50018
4621 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
4622 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
4625 #define TCM_REG_TSDM_WEIGHT 0x500c4
4626 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
4629 #define TCM_REG_USEM_IFEN 0x50028
4632 #define TCM_REG_USEM_LENGTH_MIS 0x50170
4633 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
4636 #define TCM_REG_USEM_WEIGHT 0x500b8
4638 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
4640 #define TCM_REG_XX_DESCR_TABLE 0x50280
4643 #define TCM_REG_XX_FREE 0x50178
4649 #define TCM_REG_XX_INIT_CRD 0x50220
4652 #define TCM_REG_XX_MAX_LL_SZ 0x50044
4655 #define TCM_REG_XX_MSG_NUM 0x50224
4657 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
4659 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
4661 #define TCM_REG_XX_TABLE 0x50240
4663 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
4665 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
4667 #define TM_REG_CL0_CONT_REGION 0x164030
4669 #define TM_REG_CL1_CONT_REGION 0x164034
4671 #define TM_REG_CL2_CONT_REGION 0x164038
4673 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
4675 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
4677 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
4679 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
4681 #define TM_REG_EN_CL0_INPUT 0x164008
4683 #define TM_REG_EN_CL1_INPUT 0x16400c
4685 #define TM_REG_EN_CL2_INPUT 0x164010
4686 #define TM_REG_EN_LINEAR0_TIMER 0x164014
4688 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
4690 #define TM_REG_EN_TIMERS 0x164000
4693 #define TM_REG_EXP_CRDCNT_VAL 0x164238
4695 #define TM_REG_LIN0_LOGIC_ADDR 0x164240
4697 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
4699 #define TM_REG_LIN0_NUM_SCANS 0x1640a0
4701 #define TM_REG_LIN0_PHY_ADDR 0x164270
4703 #define TM_REG_LIN0_PHY_ADDR_VALID 0x164248
4704 #define TM_REG_LIN0_SCAN_ON 0x1640d0
4706 #define TM_REG_LIN0_SCAN_TIME 0x16403c
4707 #define TM_REG_LIN0_VNIC_UC 0x164128
4709 #define TM_REG_LIN1_LOGIC_ADDR 0x164250
4711 #define TM_REG_LIN1_PHY_ADDR 0x164280
4713 #define TM_REG_LIN1_PHY_ADDR_VALID 0x164258
4715 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
4717 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
4719 #define TM_REG_TIMER_TICK_SIZE 0x16401c
4721 #define TM_REG_TM_CONTEXT_REGION 0x164044
4722 /* [RW 1] Interrupt mask register #0 read/write */
4723 #define TM_REG_TM_INT_MASK 0x1640fc
4724 /* [R 1] Interrupt register #0 read */
4725 #define TM_REG_TM_INT_STS 0x1640f0
4726 /* [RW 7] Parity mask register #0 read/write */
4727 #define TM_REG_TM_PRTY_MASK 0x16410c
4728 /* [R 7] Parity register #0 read */
4729 #define TM_REG_TM_PRTY_STS 0x164100
4730 /* [RC 7] Parity register #0 read clear */
4731 #define TM_REG_TM_PRTY_STS_CLR 0x164104
4732 /* [RW 8] The event id for aggregated interrupt 0 */
4733 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
4734 #define TSDM_REG_AGG_INT_EVENT_1 0x4203c
4735 #define TSDM_REG_AGG_INT_EVENT_2 0x42040
4736 #define TSDM_REG_AGG_INT_EVENT_3 0x42044
4737 #define TSDM_REG_AGG_INT_EVENT_4 0x42048
4738 /* [RW 1] The T bit for aggregated interrupt 0 */
4739 #define TSDM_REG_AGG_INT_T_0 0x420b8
4740 #define TSDM_REG_AGG_INT_T_1 0x420bc
4742 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
4743 /* [RW 16] The maximum value of the completion counter #0 */
4744 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
4746 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
4748 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
4750 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
4753 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
4754 #define TSDM_REG_ENABLE_IN1 0x42238
4755 #define TSDM_REG_ENABLE_IN2 0x4223c
4756 #define TSDM_REG_ENABLE_OUT1 0x42240
4757 #define TSDM_REG_ENABLE_OUT2 0x42244
4760 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
4762 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
4764 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
4766 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
4767 /* [ST 32] The number of commands received in queue 0 */
4768 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
4770 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
4772 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
4774 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
4776 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
4778 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
4780 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
4782 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
4784 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
4786 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
4788 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
4790 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
4792 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
4794 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
4796 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
4798 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
4801 #define TSDM_REG_TIMER_TICK 0x42000
4802 /* [RW 32] Interrupt mask register #0 read/write */
4803 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
4804 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
4805 /* [R 32] Interrupt register #0 read */
4806 #define TSDM_REG_TSDM_INT_STS_0 0x42290
4807 #define TSDM_REG_TSDM_INT_STS_1 0x422a0
4808 /* [RW 11] Parity mask register #0 read/write */
4809 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
4810 /* [R 11] Parity register #0 read */
4811 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
4812 /* [RC 11] Parity register #0 read clear */
4813 #define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4
4815 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
4816 /* [RW 3] The source that is associated with arbitration element 0. Source
4817 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4819 #define TSEM_REG_ARB_ELEMENT0 0x180020
4821 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4824 #define TSEM_REG_ARB_ELEMENT1 0x180024
4826 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4830 #define TSEM_REG_ARB_ELEMENT2 0x180028
4832 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4837 #define TSEM_REG_ARB_ELEMENT3 0x18002c
4839 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
4845 #define TSEM_REG_ARB_ELEMENT4 0x180030
4846 #define TSEM_REG_ENABLE_IN 0x1800a4
4847 #define TSEM_REG_ENABLE_OUT 0x1800a8
4852 #define TSEM_REG_FAST_MEMORY 0x1a0000
4855 #define TSEM_REG_FIC0_DISABLE 0x180224
4858 #define TSEM_REG_FIC1_DISABLE 0x180234
4861 #define TSEM_REG_INT_TABLE 0x180400
4864 #define TSEM_REG_MSG_NUM_FIC0 0x180000
4867 #define TSEM_REG_MSG_NUM_FIC1 0x180004
4870 #define TSEM_REG_MSG_NUM_FOC0 0x180008
4873 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
4876 #define TSEM_REG_MSG_NUM_FOC2 0x180010
4879 #define TSEM_REG_MSG_NUM_FOC3 0x180014
4882 #define TSEM_REG_PAS_DISABLE 0x18024c
4884 #define TSEM_REG_PASSIVE_BUFFER 0x181000
4885 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
4886 #define TSEM_REG_PRAM 0x1c0000
4888 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
4890 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
4892 #define TSEM_REG_THREADS_LIST 0x1802e4
4893 /* [RC 32] Parity register #0 read clear */
4894 #define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118
4895 #define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128
4896 /* [RW 3] The arbitration scheme of time_slot 0 */
4897 #define TSEM_REG_TS_0_AS 0x180038
4899 #define TSEM_REG_TS_10_AS 0x180060
4901 #define TSEM_REG_TS_11_AS 0x180064
4903 #define TSEM_REG_TS_12_AS 0x180068
4905 #define TSEM_REG_TS_13_AS 0x18006c
4907 #define TSEM_REG_TS_14_AS 0x180070
4909 #define TSEM_REG_TS_15_AS 0x180074
4911 #define TSEM_REG_TS_16_AS 0x180078
4913 #define TSEM_REG_TS_17_AS 0x18007c
4915 #define TSEM_REG_TS_18_AS 0x180080
4917 #define TSEM_REG_TS_1_AS 0x18003c
4919 #define TSEM_REG_TS_2_AS 0x180040
4921 #define TSEM_REG_TS_3_AS 0x180044
4923 #define TSEM_REG_TS_4_AS 0x180048
4925 #define TSEM_REG_TS_5_AS 0x18004c
4927 #define TSEM_REG_TS_6_AS 0x180050
4929 #define TSEM_REG_TS_7_AS 0x180054
4931 #define TSEM_REG_TS_8_AS 0x180058
4933 #define TSEM_REG_TS_9_AS 0x18005c
4934 /* [RW 32] Interrupt mask register #0 read/write */
4935 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
4936 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
4937 /* [R 32] Interrupt register #0 read */
4938 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4
4939 #define TSEM_REG_TSEM_INT_STS_1 0x180104
4940 /* [RW 32] Parity mask register #0 read/write */
4941 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
4942 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
4943 /* [R 32] Parity register #0 read */
4944 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
4945 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
4946 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
4948 #define TSEM_REG_VFPF_ERR_NUM 0x180380
4951 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
4953 #define UCM_REG_AG_CTX 0xe2000
4955 #define UCM_REG_CAM_OCCUP 0xe0170
4956 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
4959 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
4960 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
4963 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
4964 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
4967 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
4968 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
4971 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
4975 #define UCM_REG_CFC_INIT_CRD 0xe0204
4976 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
4979 #define UCM_REG_CP_WEIGHT 0xe00c4
4980 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
4983 #define UCM_REG_CSEM_IFEN 0xe0028
4986 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
4987 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
4990 #define UCM_REG_CSEM_WEIGHT 0xe00b8
4991 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
4994 #define UCM_REG_DORQ_IFEN 0xe0030
4997 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
4998 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
5001 #define UCM_REG_DORQ_WEIGHT 0xe00c0
5003 #define UCM_REG_ERR_EVNT_ID 0xe00a4
5005 #define UCM_REG_ERR_UCM_HDR 0xe00a0
5007 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
5011 #define UCM_REG_FIC0_INIT_CRD 0xe020c
5015 #define UCM_REG_FIC1_INIT_CRD 0xe0210
5016 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
5020 #define UCM_REG_GR_ARB_TYPE 0xe0144
5021 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
5024 #define UCM_REG_GR_LD0_PR 0xe014c
5025 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
5028 #define UCM_REG_GR_LD1_PR 0xe0150
5030 #define UCM_REG_INV_CFLG_Q 0xe00e4
5034 of these data in the STORM context is always 0. Index _i stands for the
5036 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
5037 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
5038 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
5039 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
5040 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
5041 #define UCM_REG_N_SM_CTX_LD_5 0xe0068
5042 #define UCM_REG_PHYS_QNUM0_0 0xe0110
5043 #define UCM_REG_PHYS_QNUM0_1 0xe0114
5044 #define UCM_REG_PHYS_QNUM1_0 0xe0118
5045 #define UCM_REG_PHYS_QNUM1_1 0xe011c
5046 #define UCM_REG_PHYS_QNUM2_0 0xe0120
5047 #define UCM_REG_PHYS_QNUM2_1 0xe0124
5048 #define UCM_REG_PHYS_QNUM3_0 0xe0128
5049 #define UCM_REG_PHYS_QNUM3_1 0xe012c
5051 #define UCM_REG_STOP_EVNT_ID 0xe00ac
5054 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
5055 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5058 #define UCM_REG_STORM_UCM_IFEN 0xe0010
5059 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5062 #define UCM_REG_STORM_WEIGHT 0xe00b0
5066 #define UCM_REG_TM_INIT_CRD 0xe021c
5068 #define UCM_REG_TM_UCM_HDR 0xe009c
5069 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5072 #define UCM_REG_TM_UCM_IFEN 0xe001c
5073 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5076 #define UCM_REG_TM_WEIGHT 0xe00d4
5077 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5080 #define UCM_REG_TSEM_IFEN 0xe0024
5083 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
5084 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5087 #define UCM_REG_TSEM_WEIGHT 0xe00b4
5088 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5091 #define UCM_REG_UCM_CFC_IFEN 0xe0044
5092 /* [RW 11] Interrupt mask register #0 read/write */
5093 #define UCM_REG_UCM_INT_MASK 0xe01d4
5094 /* [R 11] Interrupt register #0 read */
5095 #define UCM_REG_UCM_INT_STS 0xe01c8
5096 /* [RW 27] Parity mask register #0 read/write */
5097 #define UCM_REG_UCM_PRTY_MASK 0xe01e4
5098 /* [R 27] Parity register #0 read */
5099 #define UCM_REG_UCM_PRTY_STS 0xe01d8
5100 /* [RC 27] Parity register #0 read clear */
5101 #define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc
5102 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
5103 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5106 #define UCM_REG_UCM_REG0_SZ 0xe00dc
5107 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5110 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
5111 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5114 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
5115 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5118 #define UCM_REG_UCM_TM_IFEN 0xe0020
5119 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5122 #define UCM_REG_UCM_UQM_IFEN 0xe000c
5124 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
5128 #define UCM_REG_UQM_INIT_CRD 0xe0220
5129 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5132 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
5133 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5136 #define UCM_REG_UQM_S_WEIGHT 0xe00d0
5138 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
5140 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
5141 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5144 #define UCM_REG_UQM_UCM_IFEN 0xe0014
5145 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5148 #define UCM_REG_USDM_IFEN 0xe0018
5151 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
5152 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5155 #define UCM_REG_USDM_WEIGHT 0xe00c8
5156 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
5159 #define UCM_REG_XSEM_IFEN 0xe002c
5162 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
5163 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
5166 #define UCM_REG_XSEM_WEIGHT 0xe00bc
5168 mechanism. The fields are:[5:0] - message length; 14:6] - message
5170 #define UCM_REG_XX_DESCR_TABLE 0xe0280
5173 #define UCM_REG_XX_FREE 0xe016c
5178 #define UCM_REG_XX_INIT_CRD 0xe0224
5181 #define UCM_REG_XX_MSG_NUM 0xe0228
5183 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
5185 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
5187 #define UCM_REG_XX_TABLE 0xe0300
5188 #define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1<<10)
5189 #define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1<<28)
5190 #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1<<15)
5191 #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1<<24)
5192 #define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1<<5)
5193 #define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1<<8)
5194 #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1<<4)
5195 #define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1<<1)
5196 #define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1<<13)
5197 #define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1<<0)
5198 #define UMAC_REG_COMMAND_CONFIG 0x8
5202 #define UMAC_REG_EEE_WAKE_TIMER 0x6c
5203 /* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers
5205 #define UMAC_REG_MAC_ADDR0 0xc
5206 /* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1
5208 #define UMAC_REG_MAC_ADDR1 0x10
5211 #define UMAC_REG_MAXFR 0x14
5212 #define UMAC_REG_UMAC_EEE_CTRL 0x64
5213 #define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1<<3)
5214 /* [RW 8] The event id for aggregated interrupt 0 */
5215 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
5216 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
5217 #define USDM_REG_AGG_INT_EVENT_2 0xc4040
5218 #define USDM_REG_AGG_INT_EVENT_4 0xc4048
5219 #define USDM_REG_AGG_INT_EVENT_5 0xc404c
5220 #define USDM_REG_AGG_INT_EVENT_6 0xc4050
5221 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5223 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
5224 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
5225 #define USDM_REG_AGG_INT_MODE_4 0xc41c8
5226 #define USDM_REG_AGG_INT_MODE_5 0xc41cc
5227 #define USDM_REG_AGG_INT_MODE_6 0xc41d0
5229 #define USDM_REG_AGG_INT_T_5 0xc40cc
5230 #define USDM_REG_AGG_INT_T_6 0xc40d0
5232 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
5233 /* [RW 16] The maximum value of the completion counter #0 */
5234 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
5236 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
5238 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
5240 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
5243 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
5244 #define USDM_REG_ENABLE_IN1 0xc4238
5245 #define USDM_REG_ENABLE_IN2 0xc423c
5246 #define USDM_REG_ENABLE_OUT1 0xc4240
5247 #define USDM_REG_ENABLE_OUT2 0xc4244
5250 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
5252 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
5254 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
5256 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
5257 /* [ST 32] The number of commands received in queue 0 */
5258 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
5260 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
5262 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
5264 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
5266 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
5268 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
5270 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
5272 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
5274 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
5276 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
5278 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
5280 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
5282 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
5284 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
5286 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
5288 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
5290 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
5293 #define USDM_REG_TIMER_TICK 0xc4000
5294 /* [RW 32] Interrupt mask register #0 read/write */
5295 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
5296 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
5297 /* [R 32] Interrupt register #0 read */
5298 #define USDM_REG_USDM_INT_STS_0 0xc4294
5299 #define USDM_REG_USDM_INT_STS_1 0xc42a4
5300 /* [RW 11] Parity mask register #0 read/write */
5301 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
5302 /* [R 11] Parity register #0 read */
5303 #define USDM_REG_USDM_PRTY_STS 0xc42b4
5304 /* [RC 11] Parity register #0 read clear */
5305 #define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8
5307 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
5308 /* [RW 3] The source that is associated with arbitration element 0. Source
5309 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5311 #define USEM_REG_ARB_ELEMENT0 0x300020
5313 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5316 #define USEM_REG_ARB_ELEMENT1 0x300024
5318 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5322 #define USEM_REG_ARB_ELEMENT2 0x300028
5324 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5329 #define USEM_REG_ARB_ELEMENT3 0x30002c
5331 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5337 #define USEM_REG_ARB_ELEMENT4 0x300030
5338 #define USEM_REG_ENABLE_IN 0x3000a4
5339 #define USEM_REG_ENABLE_OUT 0x3000a8
5344 #define USEM_REG_FAST_MEMORY 0x320000
5347 #define USEM_REG_FIC0_DISABLE 0x300224
5350 #define USEM_REG_FIC1_DISABLE 0x300234
5353 #define USEM_REG_INT_TABLE 0x300400
5356 #define USEM_REG_MSG_NUM_FIC0 0x300000
5359 #define USEM_REG_MSG_NUM_FIC1 0x300004
5362 #define USEM_REG_MSG_NUM_FOC0 0x300008
5365 #define USEM_REG_MSG_NUM_FOC1 0x30000c
5368 #define USEM_REG_MSG_NUM_FOC2 0x300010
5371 #define USEM_REG_MSG_NUM_FOC3 0x300014
5374 #define USEM_REG_PAS_DISABLE 0x30024c
5376 #define USEM_REG_PASSIVE_BUFFER 0x302000
5377 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5378 #define USEM_REG_PRAM 0x340000
5380 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
5382 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
5384 #define USEM_REG_THREADS_LIST 0x3002e4
5385 /* [RW 3] The arbitration scheme of time_slot 0 */
5386 #define USEM_REG_TS_0_AS 0x300038
5388 #define USEM_REG_TS_10_AS 0x300060
5390 #define USEM_REG_TS_11_AS 0x300064
5392 #define USEM_REG_TS_12_AS 0x300068
5394 #define USEM_REG_TS_13_AS 0x30006c
5396 #define USEM_REG_TS_14_AS 0x300070
5398 #define USEM_REG_TS_15_AS 0x300074
5400 #define USEM_REG_TS_16_AS 0x300078
5402 #define USEM_REG_TS_17_AS 0x30007c
5404 #define USEM_REG_TS_18_AS 0x300080
5406 #define USEM_REG_TS_1_AS 0x30003c
5408 #define USEM_REG_TS_2_AS 0x300040
5410 #define USEM_REG_TS_3_AS 0x300044
5412 #define USEM_REG_TS_4_AS 0x300048
5414 #define USEM_REG_TS_5_AS 0x30004c
5416 #define USEM_REG_TS_6_AS 0x300050
5418 #define USEM_REG_TS_7_AS 0x300054
5420 #define USEM_REG_TS_8_AS 0x300058
5422 #define USEM_REG_TS_9_AS 0x30005c
5423 /* [RW 32] Interrupt mask register #0 read/write */
5424 #define USEM_REG_USEM_INT_MASK_0 0x300110
5425 #define USEM_REG_USEM_INT_MASK_1 0x300120
5426 /* [R 32] Interrupt register #0 read */
5427 #define USEM_REG_USEM_INT_STS_0 0x300104
5428 #define USEM_REG_USEM_INT_STS_1 0x300114
5429 /* [RW 32] Parity mask register #0 read/write */
5430 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
5431 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
5432 /* [R 32] Parity register #0 read */
5433 #define USEM_REG_USEM_PRTY_STS_0 0x300124
5434 #define USEM_REG_USEM_PRTY_STS_1 0x300134
5435 /* [RC 32] Parity register #0 read clear */
5436 #define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128
5437 #define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138
5438 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5440 #define USEM_REG_VFPF_ERR_NUM 0x300380
5441 #define VFC_MEMORIES_RST_REG_CAM_RST (0x1<<0)
5442 #define VFC_MEMORIES_RST_REG_RAM_RST (0x1<<1)
5443 #define VFC_REG_MEMORIES_RST 0x1943c
5446 * context; the bits [7:0] are the accessed LCID.Example: to write to REG10
5448 #define XCM_REG_AG_CTX 0x28000
5450 #define XCM_REG_AUX1_Q 0x20134
5452 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
5454 #define XCM_REG_CAM_OCCUP 0x20244
5455 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
5458 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
5459 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
5462 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
5463 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
5466 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
5467 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
5470 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
5474 #define XCM_REG_CFC_INIT_CRD 0x20404
5475 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
5478 #define XCM_REG_CP_WEIGHT 0x200dc
5479 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
5482 #define XCM_REG_CSEM_IFEN 0x20028
5485 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
5486 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
5489 #define XCM_REG_CSEM_WEIGHT 0x200c4
5490 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
5493 #define XCM_REG_DORQ_IFEN 0x20030
5496 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
5497 /* [RW 3] The weight of the input dorq in the WRR mechanism. 0 stands for
5500 #define XCM_REG_DORQ_WEIGHT 0x200cc
5502 #define XCM_REG_ERR_EVNT_ID 0x200b0
5504 #define XCM_REG_ERR_XCM_HDR 0x200ac
5506 #define XCM_REG_EXPR_EVNT_ID 0x200b4
5510 #define XCM_REG_FIC0_INIT_CRD 0x2040c
5514 #define XCM_REG_FIC1_INIT_CRD 0x20410
5515 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
5516 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
5517 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
5518 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
5519 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
5523 #define XCM_REG_GR_ARB_TYPE 0x2020c
5524 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
5527 #define XCM_REG_GR_LD0_PR 0x20214
5528 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
5531 #define XCM_REG_GR_LD1_PR 0x20218
5532 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
5535 #define XCM_REG_NIG0_IFEN 0x20038
5538 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
5539 /* [RW 3] The weight of the input nig0 in the WRR mechanism. 0 stands for
5542 #define XCM_REG_NIG0_WEIGHT 0x200d4
5543 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
5546 #define XCM_REG_NIG1_IFEN 0x2003c
5549 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
5553 of these data in the STORM context is always 0. Index _i stands for the
5555 #define XCM_REG_N_SM_CTX_LD_0 0x20060
5556 #define XCM_REG_N_SM_CTX_LD_1 0x20064
5557 #define XCM_REG_N_SM_CTX_LD_2 0x20068
5558 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
5559 #define XCM_REG_N_SM_CTX_LD_4 0x20070
5560 #define XCM_REG_N_SM_CTX_LD_5 0x20074
5561 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
5564 #define XCM_REG_PBF_IFEN 0x20034
5567 #define XCM_REG_PBF_LENGTH_MIS 0x20234
5568 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
5571 #define XCM_REG_PBF_WEIGHT 0x200d0
5572 #define XCM_REG_PHYS_QNUM3_0 0x20100
5573 #define XCM_REG_PHYS_QNUM3_1 0x20104
5575 #define XCM_REG_STOP_EVNT_ID 0x200b8
5578 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
5579 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
5582 #define XCM_REG_STORM_WEIGHT 0x200bc
5583 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
5586 #define XCM_REG_STORM_XCM_IFEN 0x20010
5590 #define XCM_REG_TM_INIT_CRD 0x2041c
5591 /* [RW 3] The weight of the Timers input in the WRR mechanism. 0 stands for
5594 #define XCM_REG_TM_WEIGHT 0x200ec
5596 #define XCM_REG_TM_XCM_HDR 0x200a8
5597 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
5600 #define XCM_REG_TM_XCM_IFEN 0x2001c
5601 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
5604 #define XCM_REG_TSEM_IFEN 0x20024
5607 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
5608 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
5611 #define XCM_REG_TSEM_WEIGHT 0x200c0
5613 #define XCM_REG_UNA_GT_NXT_Q 0x20120
5614 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
5617 #define XCM_REG_USEM_IFEN 0x2002c
5620 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
5621 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
5624 #define XCM_REG_USEM_WEIGHT 0x200c8
5625 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
5626 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
5627 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
5628 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
5629 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
5630 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
5631 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
5632 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
5633 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
5634 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
5635 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
5636 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
5637 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
5640 #define XCM_REG_XCM_CFC_IFEN 0x20050
5641 /* [RW 14] Interrupt mask register #0 read/write */
5642 #define XCM_REG_XCM_INT_MASK 0x202b4
5643 /* [R 14] Interrupt register #0 read */
5644 #define XCM_REG_XCM_INT_STS 0x202a8
5645 /* [RW 30] Parity mask register #0 read/write */
5646 #define XCM_REG_XCM_PRTY_MASK 0x202c4
5647 /* [R 30] Parity register #0 read */
5648 #define XCM_REG_XCM_PRTY_STS 0x202b8
5649 /* [RC 30] Parity register #0 read clear */
5650 #define XCM_REG_XCM_PRTY_STS_CLR 0x202bc
5652 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
5653 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
5656 #define XCM_REG_XCM_REG0_SZ 0x200f4
5657 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
5660 #define XCM_REG_XCM_STORM0_IFEN 0x20004
5661 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
5664 #define XCM_REG_XCM_STORM1_IFEN 0x20008
5665 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
5668 #define XCM_REG_XCM_TM_IFEN 0x20020
5669 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
5672 #define XCM_REG_XCM_XQM_IFEN 0x2000c
5674 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
5676 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
5680 #define XCM_REG_XQM_INIT_CRD 0x20420
5681 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
5684 #define XCM_REG_XQM_P_WEIGHT 0x200e4
5685 /* [RW 3] The weight of the QM (secondary) input in the WRR mechanism. 0
5688 #define XCM_REG_XQM_S_WEIGHT 0x200e8
5690 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
5692 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
5693 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
5696 #define XCM_REG_XQM_XCM_IFEN 0x20014
5697 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
5700 #define XCM_REG_XSDM_IFEN 0x20018
5703 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
5704 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
5707 #define XCM_REG_XSDM_WEIGHT 0x200e0
5709 mechanism. The fields are: [5:0] - message length; 11:6] - message
5711 #define XCM_REG_XX_DESCR_TABLE 0x20480
5714 #define XCM_REG_XX_FREE 0x20240
5720 #define XCM_REG_XX_INIT_CRD 0x20424
5723 #define XCM_REG_XX_MSG_NUM 0x20428
5725 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
5726 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1<<0)
5727 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1<<1)
5728 #define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1<<2)
5729 #define XMAC_CTRL_REG_RX_EN (0x1<<1)
5730 #define XMAC_CTRL_REG_SOFT_RESET (0x1<<6)
5731 #define XMAC_CTRL_REG_TX_EN (0x1<<0)
5732 #define XMAC_CTRL_REG_XLGMII_ALIGN_ENB (0x1<<7)
5733 #define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1<<18)
5734 #define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1<<17)
5735 #define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1<<1)
5736 #define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1<<0)
5737 #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1<<3)
5738 #define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1<<4)
5739 #define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1<<5)
5740 #define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60
5741 #define XMAC_REG_CTRL 0
5744 #define XMAC_REG_CTRL_SA_HI 0x2c
5747 #define XMAC_REG_CTRL_SA_LO 0x28
5748 #define XMAC_REG_EEE_CTRL 0xd8
5749 #define XMAC_REG_EEE_TIMERS_HI 0xe4
5750 #define XMAC_REG_PAUSE_CTRL 0x68
5751 #define XMAC_REG_PFC_CTRL 0x70
5752 #define XMAC_REG_PFC_CTRL_HI 0x74
5753 #define XMAC_REG_RX_LSS_CTRL 0x50
5754 #define XMAC_REG_RX_LSS_STATUS 0x58
5757 #define XMAC_REG_RX_MAX_SIZE 0x40
5758 #define XMAC_REG_TX_CTRL 0x20
5759 #define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE (0x1<<0)
5760 #define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE (0x1<<1)
5762 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
5764 #define XCM_REG_XX_TABLE 0x20500
5765 /* [RW 8] The event id for aggregated interrupt 0 */
5766 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
5767 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
5768 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
5769 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
5770 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
5771 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
5772 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
5773 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
5774 #define XSDM_REG_AGG_INT_EVENT_3 0x166044
5775 #define XSDM_REG_AGG_INT_EVENT_4 0x166048
5776 #define XSDM_REG_AGG_INT_EVENT_5 0x16604c
5777 #define XSDM_REG_AGG_INT_EVENT_6 0x166050
5778 #define XSDM_REG_AGG_INT_EVENT_7 0x166054
5779 #define XSDM_REG_AGG_INT_EVENT_8 0x166058
5780 #define XSDM_REG_AGG_INT_EVENT_9 0x16605c
5781 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
5783 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
5784 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
5786 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
5787 /* [RW 16] The maximum value of the completion counter #0 */
5788 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
5790 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
5792 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
5794 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
5797 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
5798 #define XSDM_REG_ENABLE_IN1 0x166238
5799 #define XSDM_REG_ENABLE_IN2 0x16623c
5800 #define XSDM_REG_ENABLE_OUT1 0x166240
5801 #define XSDM_REG_ENABLE_OUT2 0x166244
5804 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
5806 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
5808 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
5810 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
5811 /* [ST 32] The number of commands received in queue 0 */
5812 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
5814 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
5816 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
5818 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
5820 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
5822 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
5824 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
5826 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
5828 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
5830 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
5832 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
5834 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
5837 * bits 4:0 are the T124Param[4:0] */
5838 #define XSDM_REG_OPERATION_GEN 0x1664c4
5840 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
5842 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
5844 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
5847 #define XSDM_REG_TIMER_TICK 0x166000
5848 /* [RW 32] Interrupt mask register #0 read/write */
5849 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
5850 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
5851 /* [R 32] Interrupt register #0 read */
5852 #define XSDM_REG_XSDM_INT_STS_0 0x166290
5853 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0
5854 /* [RW 11] Parity mask register #0 read/write */
5855 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
5856 /* [R 11] Parity register #0 read */
5857 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
5858 /* [RC 11] Parity register #0 read clear */
5859 #define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4
5861 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
5862 /* [RW 3] The source that is associated with arbitration element 0. Source
5863 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5865 #define XSEM_REG_ARB_ELEMENT0 0x280020
5867 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5870 #define XSEM_REG_ARB_ELEMENT1 0x280024
5872 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5876 #define XSEM_REG_ARB_ELEMENT2 0x280028
5878 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5883 #define XSEM_REG_ARB_ELEMENT3 0x28002c
5885 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
5891 #define XSEM_REG_ARB_ELEMENT4 0x280030
5892 #define XSEM_REG_ENABLE_IN 0x2800a4
5893 #define XSEM_REG_ENABLE_OUT 0x2800a8
5898 #define XSEM_REG_FAST_MEMORY 0x2a0000
5901 #define XSEM_REG_FIC0_DISABLE 0x280224
5904 #define XSEM_REG_FIC1_DISABLE 0x280234
5907 #define XSEM_REG_INT_TABLE 0x280400
5910 #define XSEM_REG_MSG_NUM_FIC0 0x280000
5913 #define XSEM_REG_MSG_NUM_FIC1 0x280004
5916 #define XSEM_REG_MSG_NUM_FOC0 0x280008
5919 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
5922 #define XSEM_REG_MSG_NUM_FOC2 0x280010
5925 #define XSEM_REG_MSG_NUM_FOC3 0x280014
5928 #define XSEM_REG_PAS_DISABLE 0x28024c
5930 #define XSEM_REG_PASSIVE_BUFFER 0x282000
5931 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
5932 #define XSEM_REG_PRAM 0x2c0000
5934 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
5936 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
5938 #define XSEM_REG_THREADS_LIST 0x2802e4
5939 /* [RW 3] The arbitration scheme of time_slot 0 */
5940 #define XSEM_REG_TS_0_AS 0x280038
5942 #define XSEM_REG_TS_10_AS 0x280060
5944 #define XSEM_REG_TS_11_AS 0x280064
5946 #define XSEM_REG_TS_12_AS 0x280068
5948 #define XSEM_REG_TS_13_AS 0x28006c
5950 #define XSEM_REG_TS_14_AS 0x280070
5952 #define XSEM_REG_TS_15_AS 0x280074
5954 #define XSEM_REG_TS_16_AS 0x280078
5956 #define XSEM_REG_TS_17_AS 0x28007c
5958 #define XSEM_REG_TS_18_AS 0x280080
5960 #define XSEM_REG_TS_1_AS 0x28003c
5962 #define XSEM_REG_TS_2_AS 0x280040
5964 #define XSEM_REG_TS_3_AS 0x280044
5966 #define XSEM_REG_TS_4_AS 0x280048
5968 #define XSEM_REG_TS_5_AS 0x28004c
5970 #define XSEM_REG_TS_6_AS 0x280050
5972 #define XSEM_REG_TS_7_AS 0x280054
5974 #define XSEM_REG_TS_8_AS 0x280058
5976 #define XSEM_REG_TS_9_AS 0x28005c
5977 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64
5979 #define XSEM_REG_VFPF_ERR_NUM 0x280380
5980 /* [RW 32] Interrupt mask register #0 read/write */
5981 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
5982 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
5983 /* [R 32] Interrupt register #0 read */
5984 #define XSEM_REG_XSEM_INT_STS_0 0x280104
5985 #define XSEM_REG_XSEM_INT_STS_1 0x280114
5986 /* [RW 32] Parity mask register #0 read/write */
5987 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
5988 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
5989 /* [R 32] Parity register #0 read */
5990 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
5991 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
5992 /* [RC 32] Parity register #0 read clear */
5993 #define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128
5994 #define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138
5996 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
5998 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
5999 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
6008 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
6009 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
6010 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
6011 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
6012 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
6013 #define BIGMAC_REGISTER_RX_LSS_STATUS (0x43<<3)
6014 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
6015 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
6016 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
6017 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
6018 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
6019 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
6020 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
6021 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
6022 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
6023 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00<<3)
6024 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
6025 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05<<3)
6026 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06<<3)
6027 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A<<3)
6028 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62<<3)
6029 #define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E<<3)
6030 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C<<3)
6031 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40<<3)
6032 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f<<3)
6033 #define BIGMAC2_REGISTER_RX_STAT_GRPP (0x51<<3)
6034 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C<<3)
6035 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E<<3)
6036 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20<<3)
6037 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D<<3)
6038 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39<<3)
6039 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22<<3)
6040 #define BIGMAC2_REGISTER_TX_STAT_GTPP (0x24<<3)
6045 #define EMAC_LED_OVERRIDE (1L<<0)
6047 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
6052 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
6056 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL<<16)
6064 #define EMAC_MODE_RESET (1L<<0)
6065 #define EMAC_REG_EMAC_LED 0xc
6066 #define EMAC_REG_EMAC_MAC_MATCH 0x10
6067 #define EMAC_REG_EMAC_MDIO_COMM 0xac
6068 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
6069 #define EMAC_REG_EMAC_MDIO_STATUS 0xb0
6070 #define EMAC_REG_EMAC_MODE 0x0
6071 #define EMAC_REG_EMAC_RX_MODE 0xc8
6072 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
6073 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
6074 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
6076 #define EMAC_REG_EMAC_TX_MODE 0xbc
6077 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
6079 #define EMAC_REG_RX_PFC_MODE 0x320
6082 #define EMAC_REG_RX_PFC_MODE_TX_EN (1L<<0)
6083 #define EMAC_REG_RX_PFC_PARAM 0x324
6084 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0
6086 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328
6087 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff<<0)
6088 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330
6089 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff<<0)
6090 #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c
6091 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff<<0)
6092 #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334
6093 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff<<0)
6098 #define EMAC_RX_MODE_RESET (1L<<0)
6102 #define EMAC_TX_MODE_RESET (1L<<0)
6103 #define MISC_REGISTERS_GPIO_0 0
6108 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
6113 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0
6116 #define MISC_REGISTERS_GPIO_LOW 0
6118 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
6121 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
6122 #define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1<<0)
6123 #define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1<<19)
6124 #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1<<29)
6125 #define MISC_REGISTERS_RESET_REG_1_RST_NIG (0x1<<7)
6126 #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1<<26)
6127 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1<<27)
6128 #define MISC_REGISTERS_RESET_REG_1_RST_XSEM (0x1<<22)
6129 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
6130 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
6131 #define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1<<24)
6132 #define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1<<25)
6133 #define MISC_REGISTERS_RESET_REG_2_PGLC (0x1<<19)
6134 #define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1<<17)
6135 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
6136 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1<<1)
6137 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1<<2)
6138 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
6139 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1<<3)
6140 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1<<15)
6141 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1<<4)
6142 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1<<6)
6143 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1<<8)
6144 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1<<7)
6145 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1<<5)
6146 #define MISC_REGISTERS_RESET_REG_2_RST_MDIO (0x1<<13)
6147 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1<<11)
6148 #define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1<<13)
6149 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1<<9)
6150 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
6151 #define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1<<20)
6152 #define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1<<21)
6153 #define MISC_REGISTERS_RESET_REG_2_XMAC (0x1<<22)
6154 #define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1<<23)
6155 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
6156 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
6157 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
6158 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
6159 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
6160 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
6161 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
6162 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
6163 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
6164 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
6165 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
6170 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
6175 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
6178 #define MISC_SPIO_FLOAT (0xffL<<24)
6183 #define MISC_SPIO_OUTPUT_LOW 0
6185 #define MISC_SPIO_SPIO4 0x10
6186 #define MISC_SPIO_SPIO5 0x20
6191 #define HW_LOCK_RESOURCE_MDIO 0
6199 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1<<4)
6200 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1<<5)
6201 #define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1<<19)
6202 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1<<18)
6203 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1<<31)
6204 #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1<<30)
6205 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1<<9)
6206 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1<<8)
6207 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1<<7)
6208 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1<<6)
6209 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1<<29)
6210 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1<<28)
6211 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1<<1)
6212 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1<<0)
6213 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1<<18)
6214 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1<<11)
6215 #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1<<10)
6216 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1<<13)
6217 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1<<12)
6218 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1<<2)
6219 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1<<12)
6220 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1<<28)
6221 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1U<<31)
6222 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1<<29)
6223 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1<<30)
6224 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1<<15)
6225 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1<<14)
6226 #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1<<14)
6227 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1<<20)
6228 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1<<31)
6229 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1<<30)
6230 #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1<<0)
6231 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1<<2)
6232 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1<<3)
6233 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1<<5)
6234 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1<<4)
6235 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1<<3)
6236 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1<<2)
6237 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1<<3)
6238 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1<<2)
6239 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1<<22)
6240 #define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1<<15)
6241 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1<<27)
6242 #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1<<26)
6243 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1<<5)
6244 #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1<<4)
6245 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1<<25)
6246 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1<<24)
6247 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1<<29)
6248 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1<<28)
6249 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1<<23)
6250 #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1<<22)
6251 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1<<27)
6252 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1<<26)
6253 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1<<21)
6254 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1<<20)
6255 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1<<25)
6256 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1<<24)
6257 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1<<16)
6258 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1<<9)
6259 #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1<<8)
6260 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1<<7)
6261 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1<<6)
6262 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1<<11)
6263 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1<<10)
6265 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 (0x1<<5)
6266 #define AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 (0x1<<9)
6268 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
6270 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0
6271 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
6332 #define GRCBASE_PXPCS 0x000000
6333 #define GRCBASE_PCICONFIG 0x002000
6334 #define GRCBASE_PCIREG 0x002400
6335 #define GRCBASE_EMAC0 0x008000
6336 #define GRCBASE_EMAC1 0x008400
6337 #define GRCBASE_DBU 0x008800
6338 #define GRCBASE_MISC 0x00A000
6339 #define GRCBASE_DBG 0x00C000
6340 #define GRCBASE_NIG 0x010000
6341 #define GRCBASE_XCM 0x020000
6342 #define GRCBASE_PRS 0x040000
6343 #define GRCBASE_SRCH 0x040400
6344 #define GRCBASE_TSDM 0x042000
6345 #define GRCBASE_TCM 0x050000
6346 #define GRCBASE_BRB1 0x060000
6347 #define GRCBASE_MCP 0x080000
6348 #define GRCBASE_UPB 0x0C1000
6349 #define GRCBASE_CSDM 0x0C2000
6350 #define GRCBASE_USDM 0x0C4000
6351 #define GRCBASE_CCM 0x0D0000
6352 #define GRCBASE_UCM 0x0E0000
6353 #define GRCBASE_CDU 0x101000
6354 #define GRCBASE_DMAE 0x102000
6355 #define GRCBASE_PXP 0x103000
6356 #define GRCBASE_CFC 0x104000
6357 #define GRCBASE_HC 0x108000
6358 #define GRCBASE_PXP2 0x120000
6359 #define GRCBASE_PBF 0x140000
6360 #define GRCBASE_UMAC0 0x160000
6361 #define GRCBASE_UMAC1 0x160400
6362 #define GRCBASE_XPB 0x161000
6363 #define GRCBASE_MSTAT0 0x162000
6364 #define GRCBASE_MSTAT1 0x162800
6365 #define GRCBASE_XMAC0 0x163000
6366 #define GRCBASE_XMAC1 0x163800
6367 #define GRCBASE_TIMERS 0x164000
6368 #define GRCBASE_XSDM 0x166000
6369 #define GRCBASE_QM 0x168000
6370 #define GRCBASE_DQ 0x170000
6371 #define GRCBASE_TSEM 0x180000
6372 #define GRCBASE_CSEM 0x200000
6373 #define GRCBASE_XSEM 0x280000
6374 #define GRCBASE_USEM 0x300000
6379 #define PCICFG_OFFSET 0x2000
6380 #define PCICFG_VENDOR_ID_OFFSET 0x00
6381 #define PCICFG_DEVICE_ID_OFFSET 0x02
6382 #define PCICFG_COMMAND_OFFSET 0x04
6383 #define PCICFG_COMMAND_IO_SPACE (1<<0)
6394 #define PCICFG_COMMAND_RESERVED (0x1f<<11)
6395 #define PCICFG_STATUS_OFFSET 0x06
6396 #define PCICFG_REVISION_ID_OFFSET 0x08
6397 #define PCICFG_REVESION_ID_MASK 0xff
6398 #define PCICFG_REVESION_ID_ERROR_VAL 0xff
6399 #define PCICFG_CACHE_LINE_SIZE 0x0c
6400 #define PCICFG_LATENCY_TIMER 0x0d
6401 #define PCICFG_BAR_1_LOW 0x10
6402 #define PCICFG_BAR_1_HIGH 0x14
6403 #define PCICFG_BAR_2_LOW 0x18
6404 #define PCICFG_BAR_2_HIGH 0x1c
6405 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
6406 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
6407 #define PCICFG_INT_LINE 0x3c
6408 #define PCICFG_INT_PIN 0x3d
6409 #define PCICFG_PM_CAPABILITY 0x48
6410 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16)
6414 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22)
6422 #define PCICFG_PM_CSR_OFFSET 0x4c
6423 #define PCICFG_PM_CSR_STATE (0x3<<0)
6426 #define PCICFG_MSI_CAP_ID_OFFSET 0x58
6427 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16)
6428 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17)
6429 #define PCICFG_MSI_CONTROL_MENA (0x7<<20)
6430 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23)
6431 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24)
6432 #define PCICFG_GRC_ADDRESS 0x78
6433 #define PCICFG_GRC_DATA 0x80
6434 #define PCICFG_ME_REGISTER 0x98
6435 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0
6436 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16)
6437 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27)
6438 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30)
6439 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31)
6441 #define PCICFG_DEVICE_CONTROL 0xb4
6442 #define PCICFG_DEVICE_STATUS 0xb6
6443 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0)
6449 #define PCICFG_LINK_CONTROL 0xbc
6452 #define BAR_USTRORM_INTMEM 0x400000
6453 #define BAR_CSTRORM_INTMEM 0x410000
6454 #define BAR_XSTRORM_INTMEM 0x420000
6455 #define BAR_TSTRORM_INTMEM 0x430000
6458 #define BAR_IGU_INTMEM 0x440000
6460 #define BAR_DOORBELL_OFFSET 0x800000
6462 #define BAR_ME_REGISTER 0x450000
6465 #define GRC_CONFIG_2_SIZE_REG 0x408
6466 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
6467 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
6468 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
6469 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
6470 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
6471 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
6472 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
6473 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
6474 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
6475 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
6476 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
6477 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
6478 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
6479 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
6480 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
6481 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
6482 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
6487 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
6488 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
6505 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
6508 #define GRC_CONFIG_3_SIZE_REG 0x40c
6509 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
6513 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
6517 #define GRC_BAR2_CONFIG 0x4e0
6518 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
6519 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
6520 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
6521 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
6522 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
6523 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
6524 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
6525 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
6526 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
6527 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
6528 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
6529 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
6530 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
6531 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
6532 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
6533 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
6534 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
6537 #define PCI_PM_DATA_A 0x410
6538 #define PCI_PM_DATA_B 0x414
6539 #define PCI_ID_VAL1 0x434
6540 #define PCI_ID_VAL2 0x438
6541 #define PCI_ID_VAL3 0x43c
6543 #define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C
6544 #define GRC_CONFIG_REG_PF_INIT_VF 0x624
6545 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK 0xf
6550 * Since registers from 0x000-0x7ff are split across functions, each PF will
6554 #define PXPCS_TL_CONTROL_5 0x814
6584 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/
6587 #define PXPCS_TL_FUNC345_STAT 0x854
6679 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \
6683 #define PXPCS_TL_FUNC678_STAT 0x85C
6775 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \
6779 #define BAR_USTRORM_INTMEM 0x400000
6780 #define BAR_CSTRORM_INTMEM 0x410000
6781 #define BAR_XSTRORM_INTMEM 0x420000
6782 #define BAR_TSTRORM_INTMEM 0x430000
6785 #define BAR_IGU_INTMEM 0x440000
6787 #define BAR_DOORBELL_OFFSET 0x800000
6789 #define BAR_ME_REGISTER 0x450000
6790 #define ME_REG_PF_NUM_SHIFT 0
6795 #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT)
6796 #define ME_REG_VF_ERR (0x1<<3)
6802 #define PXP_VF_ADDR_IGU_START 0
6803 #define PXP_VF_ADDR_IGU_SIZE 0x3000
6807 #define PXP_VF_ADDR_USDM_QUEUES_START 0x3000
6813 #define PXP_VF_ADDR_CSDM_GLOBAL_START 0x7600
6818 #define PXP_VF_ADDR_DB_START 0x7c00
6819 #define PXP_VF_ADDR_DB_SIZE 0x200
6823 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
6824 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
6825 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
6826 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
6827 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
6829 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
6830 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
6831 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
6832 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
6833 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
6834 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
6835 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
6836 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
6837 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
6838 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
6839 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
6840 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
6841 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
6842 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
6843 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
6844 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
6845 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
6847 #define MDIO_REG_BANK_RX0 0x80b0
6848 #define MDIO_RX0_RX_STATUS 0x10
6849 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
6850 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
6851 #define MDIO_RX0_RX_EQ_BOOST 0x1c
6852 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6853 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
6855 #define MDIO_REG_BANK_RX1 0x80c0
6856 #define MDIO_RX1_RX_EQ_BOOST 0x1c
6857 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6858 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
6860 #define MDIO_REG_BANK_RX2 0x80d0
6861 #define MDIO_RX2_RX_EQ_BOOST 0x1c
6862 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6863 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
6865 #define MDIO_REG_BANK_RX3 0x80e0
6866 #define MDIO_RX3_RX_EQ_BOOST 0x1c
6867 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6868 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
6870 #define MDIO_REG_BANK_RX_ALL 0x80f0
6871 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
6872 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
6873 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
6875 #define MDIO_REG_BANK_TX0 0x8060
6876 #define MDIO_TX0_TX_DRIVER 0x17
6877 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6879 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6881 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6883 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6887 #define MDIO_REG_BANK_TX1 0x8070
6888 #define MDIO_TX1_TX_DRIVER 0x17
6889 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6891 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6893 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6895 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6899 #define MDIO_REG_BANK_TX2 0x8080
6900 #define MDIO_TX2_TX_DRIVER 0x17
6901 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6903 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6905 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6907 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6911 #define MDIO_REG_BANK_TX3 0x8090
6912 #define MDIO_TX3_TX_DRIVER 0x17
6913 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
6915 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
6917 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
6919 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
6923 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
6924 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
6926 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
6927 #define MDIO_BLOCK1_LANE_CTRL0 0x15
6928 #define MDIO_BLOCK1_LANE_CTRL1 0x16
6929 #define MDIO_BLOCK1_LANE_CTRL2 0x17
6930 #define MDIO_BLOCK1_LANE_PRBS 0x19
6932 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
6933 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
6934 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
6935 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
6936 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
6937 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
6938 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
6939 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
6940 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
6941 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
6943 #define MDIO_REG_BANK_GP_STATUS 0x8120
6944 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
6945 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
6946 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
6947 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
6948 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
6949 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
6950 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
6951 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
6952 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
6953 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
6954 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
6955 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
6956 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
6957 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
6958 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
6959 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
6960 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
6961 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
6962 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
6963 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
6964 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
6965 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
6966 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
6967 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
6968 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
6969 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
6970 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
6971 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
6972 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
6973 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
6976 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
6977 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
6978 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
6979 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
6980 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
6981 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
6982 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
6984 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
6985 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
6986 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
6987 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
6988 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
6989 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
6990 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
6991 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
6992 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
6993 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
6994 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
6995 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
6996 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
6997 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
6998 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
6999 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
7001 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
7002 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
7003 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
7004 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
7005 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
7006 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
7007 #define MDIO_SERDES_DIGITAL_MISC1 0x18
7008 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
7009 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
7010 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
7011 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
7012 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
7013 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
7014 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
7015 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
7016 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
7017 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
7018 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
7019 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
7020 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
7021 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
7022 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
7023 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
7024 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
7025 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
7027 #define MDIO_REG_BANK_OVER_1G 0x8320
7028 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
7029 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
7031 #define MDIO_OVER_1G_UP1 0x19
7032 #define MDIO_OVER_1G_UP1_2_5G 0x0001
7033 #define MDIO_OVER_1G_UP1_5G 0x0002
7034 #define MDIO_OVER_1G_UP1_6G 0x0004
7035 #define MDIO_OVER_1G_UP1_10G 0x0010
7036 #define MDIO_OVER_1G_UP1_10GH 0x0008
7037 #define MDIO_OVER_1G_UP1_12G 0x0020
7038 #define MDIO_OVER_1G_UP1_12_5G 0x0040
7039 #define MDIO_OVER_1G_UP1_13G 0x0080
7040 #define MDIO_OVER_1G_UP1_15G 0x0100
7041 #define MDIO_OVER_1G_UP1_16G 0x0200
7042 #define MDIO_OVER_1G_UP2 0x1A
7043 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
7044 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
7045 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
7046 #define MDIO_OVER_1G_UP3 0x1B
7047 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
7048 #define MDIO_OVER_1G_LP_UP1 0x1C
7049 #define MDIO_OVER_1G_LP_UP2 0x1D
7050 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
7051 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
7053 #define MDIO_OVER_1G_LP_UP3 0x1E
7055 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
7056 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
7057 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
7058 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
7060 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
7061 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
7062 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
7063 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
7065 #define MDIO_REG_BANK_CL73_USERB0 0x8370
7066 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
7067 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
7068 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
7069 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
7070 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
7071 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
7072 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
7073 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
7074 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
7075 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
7076 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
7078 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
7079 #define MDIO_AER_BLOCK_AER_REG 0x1E
7081 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
7082 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
7083 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
7084 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
7085 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
7086 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
7087 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
7088 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
7089 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
7090 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
7091 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
7092 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
7093 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
7094 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
7095 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
7096 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
7097 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
7098 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
7099 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
7100 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
7101 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
7102 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
7103 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
7104 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
7105 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
7106 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
7107 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
7108 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
7109 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
7110 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
7111 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
7115 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
7118 #define MDIO_PMA_DEVAD 0x1
7120 #define MDIO_PMA_REG_CTRL 0x0
7121 #define MDIO_PMA_REG_STATUS 0x1
7122 #define MDIO_PMA_REG_10G_CTRL2 0x7
7123 #define MDIO_PMA_REG_TX_DISABLE 0x0009
7124 #define MDIO_PMA_REG_RX_SD 0xa
7126 #define MDIO_PMA_REG_BCM_CTRL 0x0096
7127 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
7128 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
7129 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
7130 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
7131 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
7132 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
7133 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
7134 #define MDIO_PMA_REG_GEN_CTRL 0xca10
7135 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
7136 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
7137 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
7138 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
7139 #define MDIO_PMA_REG_ROM_VER1 0xca19
7140 #define MDIO_PMA_REG_ROM_VER2 0xca1a
7141 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
7142 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
7143 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
7144 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
7145 #define MDIO_PMA_REG_LRM_MODE 0xca3f
7146 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
7147 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
7149 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
7150 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
7151 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
7152 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
7153 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
7154 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
7155 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
7156 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
7157 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
7158 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
7159 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
7160 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
7162 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
7163 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
7164 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
7165 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
7166 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
7167 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
7168 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
7169 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
7170 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
7172 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
7174 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
7175 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
7176 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
7177 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
7179 #define MDIO_PMA_REG_7101_RESET 0xc000
7180 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
7181 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
7182 #define MDIO_PMA_REG_7101_VER1 0xc026
7183 #define MDIO_PMA_REG_7101_VER2 0xc027
7185 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
7186 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
7187 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
7188 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
7189 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
7190 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
7191 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
7192 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
7193 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
7197 #define MDIO_WIS_DEVAD 0x2
7199 #define MDIO_WIS_REG_LASI_CNTL 0x9002
7200 #define MDIO_WIS_REG_LASI_STATUS 0x9005
7202 #define MDIO_PCS_DEVAD 0x3
7203 #define MDIO_PCS_REG_STATUS 0x0020
7204 #define MDIO_PCS_REG_LASI_STATUS 0x9005
7205 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
7206 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
7207 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
7209 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
7211 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
7213 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
7216 #define MDIO_XS_DEVAD 0x4
7217 #define MDIO_XS_PLL_SEQUENCER 0x8000
7218 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
7220 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
7221 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
7222 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
7223 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
7224 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
7226 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
7228 #define MDIO_AN_DEVAD 0x7
7230 #define MDIO_AN_REG_CTRL 0x0000
7231 #define MDIO_AN_REG_STATUS 0x0001
7232 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
7233 #define MDIO_AN_REG_ADV_PAUSE 0x0010
7234 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
7235 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
7236 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
7237 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
7238 #define MDIO_AN_REG_ADV 0x0011
7239 #define MDIO_AN_REG_ADV2 0x0012
7240 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
7241 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
7242 #define MDIO_AN_REG_MASTER_STATUS 0x0021
7243 #define MDIO_AN_REG_EEE_ADV 0x003c
7244 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
7246 #define MDIO_AN_REG_LINK_STATUS 0x8304
7247 #define MDIO_AN_REG_CL37_CL73 0x8370
7248 #define MDIO_AN_REG_CL37_AN 0xffe0
7249 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
7250 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
7251 #define MDIO_AN_REG_1000T_STATUS 0xffea
7253 #define MDIO_AN_REG_8073_2_5G 0x8329
7254 #define MDIO_AN_REG_8073_BAM 0x8350
7256 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
7257 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
7258 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
7259 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
7260 #define MDIO_AN_REG_848xx_ID_MSB 0xffe2
7261 #define BCM84858_PHY_ID 0x600d
7262 #define MDIO_AN_REG_848xx_ID_LSB 0xffe3
7263 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
7264 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
7265 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
7266 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
7267 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
7268 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
7269 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
7270 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
7271 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
7274 #define MDIO_CTL_DEVAD 0x1e
7275 #define MDIO_CTL_REG_84823_MEDIA 0x401a
7276 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
7278 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
7279 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
7281 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
7282 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
7283 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
7287 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
7288 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
7289 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
7290 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
7291 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
7292 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
7293 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
7294 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
7295 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
7296 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
7297 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
7298 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
7300 #define MDIO_PMA_REG_84858_ALLOW_GPHY_ACT 0x8000
7303 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
7304 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
7305 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
7306 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
7307 #define MDIO_84833_SUPER_ISOLATE 0x8000
7309 #define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005
7310 #define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006
7311 #define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007
7312 #define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008
7313 #define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009
7314 #define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037
7315 #define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038
7316 #define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039
7317 #define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a
7318 #define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b
7319 #define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c
7329 #define PHY848xx_CMD_SET_PAIR_SWAP 0x8001
7330 #define PHY848xx_CMD_GET_EEE_MODE 0x8008
7331 #define PHY848xx_CMD_SET_EEE_MODE 0x8009
7333 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
7334 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
7335 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
7336 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
7337 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
7338 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
7339 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
7340 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
7341 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
7348 #define PHY84858_STATUS_CMD_RECEIVED 0x0001
7349 #define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002
7350 #define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004
7351 #define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008
7352 #define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb
7356 #define MDIO_WC_DEVAD 0x3
7357 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
7358 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
7359 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
7360 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
7361 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
7362 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
7363 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
7364 #define MDIO_WC_REG_PCS_STATUS2 0x0021
7365 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
7366 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
7367 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
7368 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
7369 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
7370 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
7371 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
7372 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
7373 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
7374 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
7375 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
7376 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
7377 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01
7378 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e
7379 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
7380 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
7381 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
7382 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
7383 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
7384 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
7385 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
7386 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
7387 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
7388 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
7389 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
7390 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
7391 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
7392 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
7393 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
7394 #define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
7395 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
7396 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
7397 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
7398 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
7399 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
7400 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
7401 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
7402 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
7403 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
7404 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
7405 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
7406 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
7407 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
7408 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
7409 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
7410 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
7411 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
7412 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
7413 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
7414 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
7415 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
7416 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
7417 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
7418 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
7419 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
7420 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
7421 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
7422 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
7423 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
7424 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
7425 #define MDIO_WC_REG_DSC_SMC 0x8213
7426 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
7427 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
7428 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
7429 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
7430 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
7431 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
7432 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
7433 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
7434 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
7435 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
7436 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
7437 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
7438 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
7439 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
7440 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
7441 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
7442 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
7443 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
7444 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
7445 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
7446 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
7447 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
7448 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
7449 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
7450 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
7451 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
7452 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
7453 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
7454 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
7455 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
7456 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
7457 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
7458 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
7459 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
7460 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
7461 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
7462 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
7463 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
7464 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
7465 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
7466 #define MDIO_WC_REG_RX66_SCW0 0x83c2
7467 #define MDIO_WC_REG_RX66_SCW1 0x83c3
7468 #define MDIO_WC_REG_RX66_SCW2 0x83c4
7469 #define MDIO_WC_REG_RX66_SCW3 0x83c5
7470 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
7471 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
7472 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
7473 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
7474 #define MDIO_WC_REG_FX100_CTRL1 0x8400
7475 #define MDIO_WC_REG_FX100_CTRL3 0x8402
7476 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
7477 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
7478 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
7479 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
7480 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
7481 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
7482 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
7483 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
7484 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
7485 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
7486 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
7487 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
7488 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
7489 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
7491 #define MDIO_WC_REG_AERBLK_AER 0xffde
7492 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
7493 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
7495 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
7496 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
7499 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
7501 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
7504 #define MDIO_REG_GPHY_PHYID_LSB 0x3
7505 #define MDIO_REG_GPHY_ID_54618SE 0x5cd5
7506 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
7507 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
7508 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
7509 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
7510 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
7511 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
7512 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
7513 #define MDIO_REG_GPHY_AUX_STATUS 0x19
7514 #define MDIO_REG_INTR_STATUS 0x1a
7515 #define MDIO_REG_INTR_MASK 0x1b
7516 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
7517 #define MDIO_REG_GPHY_SHADOW 0x1c
7518 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
7519 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
7520 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
7521 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
7522 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
7524 #define IGU_FUNC_BASE 0x0400
7526 #define IGU_ADDR_MSIX 0x0000
7527 #define IGU_ADDR_INT_ACK 0x0200
7528 #define IGU_ADDR_PROD_UPD 0x0201
7529 #define IGU_ADDR_ATTN_BITS_UPD 0x0202
7530 #define IGU_ADDR_ATTN_BITS_SET 0x0203
7531 #define IGU_ADDR_ATTN_BITS_CLR 0x0204
7532 #define IGU_ADDR_COALESCE_NOW 0x0205
7533 #define IGU_ADDR_SIMD_MASK 0x0206
7534 #define IGU_ADDR_SIMD_NOMASK 0x0207
7535 #define IGU_ADDR_MSI_CTL 0x0210
7536 #define IGU_ADDR_MSI_ADDR_LO 0x0211
7537 #define IGU_ADDR_MSI_ADDR_HI 0x0212
7538 #define IGU_ADDR_MSI_DATA 0x0213
7540 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0
7545 #define COMMAND_REG_INT_ACK 0x0
7546 #define COMMAND_REG_PROD_UPD 0x4
7547 #define COMMAND_REG_ATTN_BITS_UPD 0x8
7548 #define COMMAND_REG_ATTN_BITS_SET 0xc
7549 #define COMMAND_REG_ATTN_BITS_CLR 0x10
7550 #define COMMAND_REG_COALESCE_NOW 0x14
7551 #define COMMAND_REG_SIMD_MASK 0x18
7552 #define COMMAND_REG_SIMD_NOMASK 0x1c
7555 #define IGU_MEM_BASE 0x0000
7557 #define IGU_MEM_MSIX_BASE 0x0000
7558 #define IGU_MEM_MSIX_UPPER 0x007f
7559 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
7561 #define IGU_MEM_PBA_MSIX_BASE 0x0200
7562 #define IGU_MEM_PBA_MSIX_UPPER 0x0200
7564 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201
7565 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
7567 #define IGU_CMD_INT_ACK_BASE 0x0400
7570 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff
7572 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500
7575 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f
7577 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0
7578 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1
7579 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2
7581 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3
7582 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4
7583 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5
7584 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6
7586 #define IGU_REG_RESERVED_UPPER 0x05ff
7588 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */
7589 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
7590 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */
7591 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */
7592 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
7593 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */
7596 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */
7597 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */
7598 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */
7600 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */
7610 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \
7611 [5:2] = 0; [1:0] = PF number) */
7612 #define IGU_FID_ENCODE_IS_PF (0x1<<6)
7614 #define IGU_FID_VF_NUM_MASK (0x3f)
7615 #define IGU_FID_PF_NUM_MASK (0x7)
7617 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0)
7618 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1)
7620 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7)
7630 * String-to-compress [3:0] = Type
7633 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
7635 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
7637 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
7639 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7))
7640 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80)
7643 #define PXP_REG_HST_VF_DISABLED_ERROR_VALID 0x1030bc
7644 #define PXP_REG_HST_VF_DISABLED_ERROR_DATA 0x1030b8
7645 #define PXP_REG_HST_PER_VIOLATION_VALID 0x1030e0
7646 #define PXP_REG_HST_INCORRECT_ACCESS_VALID 0x1030cc
7647 #define PXP2_REG_RD_CPL_ERR_DETAILS 0x120778
7648 #define PXP2_REG_RD_CPL_ERR_DETAILS2 0x12077c
7649 #define PXP2_REG_RQ_GARB 0x120748
7650 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q0 0x15c1bc
7651 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q1 0x15c1c0
7652 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q2 0x15c1c4
7653 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q3 0x15c1c8
7654 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q4 0x15c1cc
7655 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q5 0x15c1d0
7656 #define PBF_REG_CREDIT_Q2 0x140344
7657 #define PBF_REG_CREDIT_Q3 0x140348
7658 #define PBF_REG_CREDIT_Q4 0x14034c
7659 #define PBF_REG_CREDIT_Q5 0x140350
7660 #define PBF_REG_INIT_CRD_Q2 0x15c238
7661 #define PBF_REG_INIT_CRD_Q3 0x15c23c
7662 #define PBF_REG_INIT_CRD_Q4 0x15c240
7663 #define PBF_REG_INIT_CRD_Q5 0x15c244
7664 #define PBF_REG_TASK_CNT_Q0 0x140374
7665 #define PBF_REG_TASK_CNT_Q1 0x140378
7666 #define PBF_REG_TASK_CNT_Q2 0x14037c
7667 #define PBF_REG_TASK_CNT_Q3 0x140380
7668 #define PBF_REG_TASK_CNT_Q4 0x140384
7669 #define PBF_REG_TASK_CNT_Q5 0x140388
7670 #define PBF_REG_TASK_CNT_LB_Q 0x140370
7671 #define QM_REG_BYTECRD0 0x16e6fc
7672 #define QM_REG_BYTECRD1 0x16e700
7673 #define QM_REG_BYTECRD2 0x16e704
7674 #define QM_REG_BYTECRD3 0x16e7ac
7675 #define QM_REG_BYTECRD4 0x16e7b0
7676 #define QM_REG_BYTECRD5 0x16e7b4
7677 #define QM_REG_BYTECRD6 0x16e7b8
7678 #define QM_REG_BYTECRDCMDQ_0 0x16e6e8
7679 #define QM_REG_BYTECRDERRREG 0x16e708
7680 #define MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID 0xa714
7681 #define QM_REG_VOQCREDIT_2 0x1682d8
7682 #define QM_REG_VOQCREDIT_3 0x1682dc
7683 #define QM_REG_VOQCREDIT_5 0x1682e4
7684 #define QM_REG_VOQCREDIT_6 0x1682e8
7685 #define QM_REG_VOQINITCREDIT_3 0x16806c
7686 #define QM_REG_VOQINITCREDIT_6 0x168078
7687 #define QM_REG_FWVOQ0TOHWVOQ 0x16e7bc
7688 #define QM_REG_FWVOQ1TOHWVOQ 0x16e7c0
7689 #define QM_REG_FWVOQ2TOHWVOQ 0x16e7c4
7690 #define QM_REG_FWVOQ3TOHWVOQ 0x16e7c8
7691 #define QM_REG_FWVOQ4TOHWVOQ 0x16e7cc
7692 #define QM_REG_FWVOQ5TOHWVOQ 0x16e7d0
7693 #define QM_REG_FWVOQ6TOHWVOQ 0x16e7d4
7694 #define QM_REG_FWVOQ7TOHWVOQ 0x16e7d8
7695 #define NIG_REG_INGRESS_EOP_PORT0_EMPTY 0x104ec
7696 #define NIG_REG_INGRESS_EOP_PORT1_EMPTY 0x104f8
7697 #define NIG_REG_INGRESS_RMP0_DSCR_EMPTY 0x10530
7698 #define NIG_REG_INGRESS_RMP1_DSCR_EMPTY 0x10538
7699 #define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY 0x10508
7700 #define NIG_REG_EGRESS_MNG0_FIFO_EMPTY 0x10460
7701 #define NIG_REG_EGRESS_MNG1_FIFO_EMPTY 0x10474
7702 #define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY 0x10418
7703 #define NIG_REG_EGRESS_DELAY0_EMPTY 0x10420
7704 #define NIG_REG_EGRESS_DELAY1_EMPTY 0x10428
7705 #define NIG_REG_LLH0_FIFO_EMPTY 0x10548
7706 #define NIG_REG_LLH1_FIFO_EMPTY 0x10558
7707 #define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY 0x182a8
7708 #define NIG_REG_P0_TLLH_FIFO_EMPTY 0x18308
7709 #define NIG_REG_P0_HBUF_DSCR_EMPTY 0x18318
7710 #define NIG_REG_P1_HBUF_DSCR_EMPTY 0x18348
7711 #define NIG_REG_P0_RX_MACFIFO_EMPTY 0x18570
7712 #define NIG_REG_P0_TX_MACFIFO_EMPTY 0x18578
7713 #define NIG_REG_EGRESS_DELAY2_EMPTY 0x1862c
7714 #define NIG_REG_EGRESS_DELAY3_EMPTY 0x18630
7715 #define NIG_REG_EGRESS_DELAY4_EMPTY 0x18634
7716 #define NIG_REG_EGRESS_DELAY5_EMPTY 0x18638
7720 * Calculates crc 8 on a word value: polynomial 0-1-2-8
7733 for (i = 0; i < 32; i++) { in calc_crc8()
7739 for (i = 0; i < 8; i++) { in calc_crc8()
7744 NewCRC[0] = D[31] ^ D[30] ^ D[28] ^ D[23] ^ D[21] ^ D[19] ^ D[18] ^ in calc_crc8()
7745 D[16] ^ D[14] ^ D[12] ^ D[8] ^ D[7] ^ D[6] ^ D[0] ^ C[4] ^ in calc_crc8()
7749 D[12] ^ D[9] ^ D[6] ^ D[1] ^ D[0] ^ C[0] ^ C[4] ^ C[5] ^ in calc_crc8()
7752 D[13] ^ D[12] ^ D[10] ^ D[8] ^ D[6] ^ D[2] ^ D[1] ^ D[0] ^ in calc_crc8()
7753 C[0] ^ C[1] ^ C[4] ^ C[5]; in calc_crc8()
7759 C[0] ^ C[2] ^ C[3] ^ C[6] ^ C[7]; in calc_crc8()
7770 crc_res = 0; in calc_crc8()
7771 for (i = 0; i < 8; i++) in calc_crc8()