Lines Matching +full:0 +full:x80b0
40 #define I2C_BSC0 0
54 #define NIG_LATCH_BC_ENABLE_MI_INT 0
152 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
153 #define SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
154 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
155 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
156 #define SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
159 #define SFP_EEPROM_10G_COMP_CODE_ADDR 0x3
164 #define SFP_EEPROM_1G_COMP_CODE_ADDR 0x6
165 #define SFP_EEPROM_1G_COMP_CODE_SX (1<<0)
170 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
171 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
172 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
174 #define SFP_EEPROM_OPTIONS_ADDR 0x40
175 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
178 #define EDC_MODE_LINEAR 0x0022
179 #define EDC_MODE_LIMITING 0x0044
180 #define EDC_MODE_PASSIVE_DAC 0x0055
181 #define EDC_MODE_ACTIVE_DAC 0x0066
184 #define DCBX_INVALID_COS (0xFF)
186 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
187 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
195 #define DEFAULT_TX_DRV_IFIR 0
206 (_bank + (_addr & 0xf)), \
212 (_bank + (_addr & 0xf)), \
243 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
279 return 0; in bnx2x_check_lfa()
291 lfa_mask = 0xffffffff; in bnx2x_check_lfa()
294 lfa_mask = 0xffff; in bnx2x_check_lfa()
300 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); in bnx2x_check_lfa()
309 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); in bnx2x_check_lfa()
318 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); in bnx2x_check_lfa()
325 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { in bnx2x_check_lfa()
363 return 0; in bnx2x_check_lfa()
371 *en = 0; in bnx2x_get_epio()
417 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; in bnx2x_set_cfg_pin()
430 u8 gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; in bnx2x_get_cfg_pin()
434 return 0; in bnx2x_get_cfg_pin()
447 /* mapping between entry priority to client number (0,1,2 -debug and in bnx2x_ets_e2e3a0_disabled()
454 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); in bnx2x_ets_e2e3a0_disabled()
456 * as strict. Bits 0,1,2 - debug and management entries, 3 - in bnx2x_ets_e2e3a0_disabled()
463 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_e2e3a0_disabled()
465 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); in bnx2x_ets_e2e3a0_disabled()
469 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_e2e3a0_disabled()
473 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); in bnx2x_ets_e2e3a0_disabled()
474 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); in bnx2x_ets_e2e3a0_disabled()
475 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); in bnx2x_ets_e2e3a0_disabled()
477 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); in bnx2x_ets_e2e3a0_disabled()
478 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); in bnx2x_ets_e2e3a0_disabled()
479 REG_WR(bp, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); in bnx2x_ets_e2e3a0_disabled()
481 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_e2e3a0_disabled()
485 REG_WR(bp, PBF_REG_COS0_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
486 REG_WR(bp, PBF_REG_COS1_WEIGHT, 0x2710); in bnx2x_ets_e2e3a0_disabled()
488 REG_WR(bp, PBF_REG_COS0_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
489 REG_WR(bp, PBF_REG_COS1_UPPER_BOUND, 0x989680); in bnx2x_ets_e2e3a0_disabled()
491 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_e2e3a0_disabled()
500 u32 min_w_val = 0; in bnx2x_ets_get_min_w_val_nig()
575 /* Mapping between entry priority to client number (0,1,2 -debug and in bnx2x_ets_e3b0_nig_disabled()
581 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); in bnx2x_ets_e3b0_nig_disabled()
582 REG_WR(bp, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
584 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); in bnx2x_ets_e3b0_nig_disabled()
585 REG_WR(bp, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); in bnx2x_ets_e3b0_nig_disabled()
591 NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_e3b0_nig_disabled()
597 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); in bnx2x_ets_e3b0_nig_disabled()
598 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); in bnx2x_ets_e3b0_nig_disabled()
600 /*Port 0 has 9 COS*/ in bnx2x_ets_e3b0_nig_disabled()
602 0x43210876); in bnx2x_ets_e3b0_nig_disabled()
603 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); in bnx2x_ets_e3b0_nig_disabled()
607 * as strict. Bits 0,1,2 - debug and management entries, 3 - in bnx2x_ets_e3b0_nig_disabled()
614 REG_WR(bp, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); in bnx2x_ets_e3b0_nig_disabled()
616 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); in bnx2x_ets_e3b0_nig_disabled()
619 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); in bnx2x_ets_e3b0_nig_disabled()
628 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); in bnx2x_ets_e3b0_nig_disabled()
630 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); in bnx2x_ets_e3b0_nig_disabled()
632 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); in bnx2x_ets_e3b0_nig_disabled()
634 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); in bnx2x_ets_e3b0_nig_disabled()
636 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); in bnx2x_ets_e3b0_nig_disabled()
638 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); in bnx2x_ets_e3b0_nig_disabled()
640 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); in bnx2x_ets_e3b0_nig_disabled()
641 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); in bnx2x_ets_e3b0_nig_disabled()
642 REG_WR(bp, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); in bnx2x_ets_e3b0_nig_disabled()
660 u32 base_upper_bound = 0; in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
661 u8 max_cos = 0; in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
662 u8 i = 0; in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
674 for (i = 0; i < max_cos; i++) in bnx2x_ets_e3b0_set_credit_upper_bound_pbf()
691 u8 i = 0; in bnx2x_ets_e3b0_pbf_disabled()
692 u32 base_weight = 0; in bnx2x_ets_e3b0_pbf_disabled()
693 u8 max_cos = 0; in bnx2x_ets_e3b0_pbf_disabled()
695 /* Mapping between entry priority to client number 0 - COS0 in bnx2x_ets_e3b0_pbf_disabled()
700 /* 0x688 (|011|0 10|00 1|000) */ in bnx2x_ets_e3b0_pbf_disabled()
701 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); in bnx2x_ets_e3b0_pbf_disabled()
703 /* (10 1|100 |011|0 10|00 1|000) */ in bnx2x_ets_e3b0_pbf_disabled()
704 REG_WR(bp, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
708 /* 0x688 (|011|0 10|00 1|000)*/ in bnx2x_ets_e3b0_pbf_disabled()
709 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); in bnx2x_ets_e3b0_pbf_disabled()
711 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ in bnx2x_ets_e3b0_pbf_disabled()
712 REG_WR(bp, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); in bnx2x_ets_e3b0_pbf_disabled()
715 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); in bnx2x_ets_e3b0_pbf_disabled()
719 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); in bnx2x_ets_e3b0_pbf_disabled()
722 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); in bnx2x_ets_e3b0_pbf_disabled()
734 for (i = 0; i < max_cos; i++) in bnx2x_ets_e3b0_pbf_disabled()
735 REG_WR(bp, base_weight + (0x4 * i), 0); in bnx2x_ets_e3b0_pbf_disabled()
759 return 0; in bnx2x_ets_e3b0_disabled()
771 int bnx2x_status = 0; in bnx2x_ets_disabled()
797 const u8 nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); in bnx2x_ets_e3b0_cli_map()
816 return 0; in bnx2x_ets_e3b0_cli_map()
832 u32 nig_reg_adress_crd_weight = 0; in bnx2x_ets_e3b0_set_cos_bw()
833 u32 pbf_reg_adress_crd_weight = 0; in bnx2x_ets_e3b0_set_cos_bw()
834 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ in bnx2x_ets_e3b0_set_cos_bw()
839 case 0: in bnx2x_ets_e3b0_set_cos_bw()
885 return 0; in bnx2x_ets_e3b0_set_cos_bw()
889 * Calculate the total BW.A value of 0 isn't legal.
898 u8 cos_idx = 0; in bnx2x_ets_e3b0_get_total_bw()
899 u8 is_bw_cos_exist = 0; in bnx2x_ets_e3b0_get_total_bw()
901 *total_bw = 0 ; in bnx2x_ets_e3b0_get_total_bw()
903 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { in bnx2x_ets_e3b0_get_total_bw()
908 "was set to 0\n"); in bnx2x_ets_e3b0_get_total_bw()
922 if (*total_bw == 0) { in bnx2x_ets_e3b0_get_total_bw()
924 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n"); in bnx2x_ets_e3b0_get_total_bw()
933 return 0; in bnx2x_ets_e3b0_get_total_bw()
943 u8 pri = 0; in bnx2x_ets_e3b0_sp_pri_to_cos_init()
944 for (pri = 0; pri < DCBX_MAX_NUM_COS; pri++) in bnx2x_ets_e3b0_sp_pri_to_cos_init()
976 return 0; in bnx2x_ets_e3b0_sp_pri_to_cos_set()
991 u64 pri_cli_nig = 0; in bnx2x_e3b0_sp_get_pri_cli_reg()
1021 const u8 pbf_cos_offset = 0; in bnx2x_e3b0_sp_get_pri_cli_reg_pbf()
1022 const u8 pbf_pri_offset = 0; in bnx2x_e3b0_sp_get_pri_cli_reg_pbf()
1039 u8 i = 0; in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1042 u64 pri_cli_nig = 0x210; in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1043 u32 pri_cli_pbf = 0x0; in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1044 u8 pri_set = 0; in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1045 u8 pri_bitmask = 0; in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1052 for (i = 0; i < max_num_of_cos; i++) { in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1081 for (i = 0; i < max_num_of_cos; i++) { in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1112 const u32 pri_cli_nig_msb = (u32) ((pri_cli_nig >> 32) & 0xF); in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1121 return 0; in bnx2x_ets_e3b0_sp_set_pri_cli_reg()
1133 int bnx2x_status = 0; in bnx2x_ets_e3b0_config()
1135 u16 total_bw = 0; in bnx2x_ets_e3b0_config()
1138 u8 cos_bw_bitmap = 0; in bnx2x_ets_e3b0_config()
1139 u8 cos_sp_bitmap = 0; in bnx2x_ets_e3b0_config()
1140 u8 sp_pri_to_cos[DCBX_MAX_NUM_COS] = {0}; in bnx2x_ets_e3b0_config()
1143 u8 cos_entry = 0; in bnx2x_ets_e3b0_config()
1176 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { in bnx2x_ets_e3b0_config()
1228 return 0; in bnx2x_ets_e3b0_config()
1236 * COS0 0x8 in bnx2x_ets_bw_limit_common()
1237 * COS1 0x10 in bnx2x_ets_bw_limit_common()
1239 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); in bnx2x_ets_bw_limit_common()
1242 * client 0) in bnx2x_ets_bw_limit_common()
1246 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); in bnx2x_ets_bw_limit_common()
1257 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); in bnx2x_ets_bw_limit_common()
1259 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 in bnx2x_ets_bw_limit_common()
1265 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); in bnx2x_ets_bw_limit_common()
1280 u32 cos0_credit_weight = 0; in bnx2x_ets_bw_limit()
1281 u32 cos1_credit_weight = 0; in bnx2x_ets_bw_limit()
1310 u32 val = 0; in bnx2x_ets_strict()
1314 * as strict. Bits 0,1,2 - debug and management entries, in bnx2x_ets_strict()
1320 REG_WR(bp, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); in bnx2x_ets_strict()
1324 REG_WR(bp, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1326 REG_WR(bp, PBF_REG_ETS_ENABLED, 0); in bnx2x_ets_strict()
1328 REG_WR(bp, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); in bnx2x_ets_strict()
1333 /* Mapping between entry priority to client number (0,1,2 -debug and in bnx2x_ets_strict()
1340 val = (!strict_cos) ? 0x2318 : 0x22E0; in bnx2x_ets_strict()
1343 return 0; in bnx2x_ets_strict()
1361 pause_val = 0x18000; in bnx2x_update_pfc_xmac()
1362 pfc0_val = 0xFFFF8000; in bnx2x_update_pfc_xmac()
1363 pfc1_val = 0x2; in bnx2x_update_pfc_xmac()
1404 ((params->mac_addr[0] << 8) | in bnx2x_update_pfc_xmac()
1419 * (a value of 49==0x31) and make sure that the AUTO poll is off in bnx2x_set_mdio_clk()
1437 DP(NETIF_MSG_LINK, "Changing emac_mode from 0x%x to 0x%x\n", in bnx2x_set_mdio_clk()
1459 if (port4mode_ovwr_val & (1<<0)) { in bnx2x_is_4_port_mode()
1501 val = ((params->mac_addr[0] << 8) | in bnx2x_emac_init()
1570 val |= (0<<2); in bnx2x_umac_enable()
1603 REG_WR(bp, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); in bnx2x_umac_enable()
1605 REG_WR(bp, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); in bnx2x_umac_enable()
1615 ((params->mac_addr[0] << 8) | in bnx2x_umac_enable()
1636 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_umac_enable()
1638 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); in bnx2x_umac_enable()
1683 REG_WR(bp, MISC_REG_XMAC_CORE_PORT_MODE, 0); in bnx2x_xmac_init()
1752 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); in bnx2x_xmac_enable()
1761 REG_WR(bp, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_xmac_enable()
1767 REG_WR(bp, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); in bnx2x_xmac_enable()
1770 REG_WR(bp, xmac_base + XMAC_REG_TX_CTRL, 0xC800); in bnx2x_xmac_enable()
1773 bnx2x_update_pfc_xmac(params, vars, 0); in bnx2x_xmac_enable()
1777 REG_WR(bp, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); in bnx2x_xmac_enable()
1778 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x1); in bnx2x_xmac_enable()
1780 REG_WR(bp, xmac_base + XMAC_REG_EEE_CTRL, 0x0); in bnx2x_xmac_enable()
1797 ((vars->flow_ctrl & BNX2X_FLOW_CTRL_TX) != 0), 1); in bnx2x_xmac_enable()
1801 return 0; in bnx2x_xmac_enable()
1828 /* select the master lanes (out of 0-3) */ in bnx2x_emac_enable()
1836 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); in bnx2x_emac_enable()
1878 EMAC_WR(bp, EMAC_REG_RX_PFC_MODE, 0); in bnx2x_emac_enable()
1888 ((0x0101 << in bnx2x_emac_enable()
1890 (0x00ff << in bnx2x_emac_enable()
1899 val |= 0x810; in bnx2x_emac_enable()
1901 val &= ~0x810; in bnx2x_emac_enable()
1913 REG_WR(bp, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); in bnx2x_emac_enable()
1916 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x0); in bnx2x_emac_enable()
1917 REG_WR(bp, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1918 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1921 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x1); in bnx2x_emac_enable()
1922 val = 0; in bnx2x_emac_enable()
1929 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); in bnx2x_emac_enable()
1931 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); in bnx2x_emac_enable()
1934 return 0; in bnx2x_emac_enable()
1945 u32 val = 0x14; in bnx2x_update_pfc_bmac1()
1951 wb_data[0] = val; in bnx2x_update_pfc_bmac1()
1952 wb_data[1] = 0; in bnx2x_update_pfc_bmac1()
1956 val = 0xc0; in bnx2x_update_pfc_bmac1()
1960 val |= 0x800000; in bnx2x_update_pfc_bmac1()
1961 wb_data[0] = val; in bnx2x_update_pfc_bmac1()
1962 wb_data[1] = 0; in bnx2x_update_pfc_bmac1()
1977 u32 val = 0x14; in bnx2x_update_pfc_bmac2()
1984 wb_data[0] = val; in bnx2x_update_pfc_bmac2()
1985 wb_data[1] = 0; in bnx2x_update_pfc_bmac2()
1990 val = 0xc0; in bnx2x_update_pfc_bmac2()
1994 val |= 0x800000; in bnx2x_update_pfc_bmac2()
1995 wb_data[0] = val; in bnx2x_update_pfc_bmac2()
1996 wb_data[1] = 0; in bnx2x_update_pfc_bmac2()
2002 wb_data[0] = 0x0; in bnx2x_update_pfc_bmac2()
2003 wb_data[0] |= (1<<0); /* RX */ in bnx2x_update_pfc_bmac2()
2004 wb_data[0] |= (1<<1); /* TX */ in bnx2x_update_pfc_bmac2()
2005 wb_data[0] |= (1<<2); /* Force initial Xon */ in bnx2x_update_pfc_bmac2()
2006 wb_data[0] |= (1<<3); /* 8 cos */ in bnx2x_update_pfc_bmac2()
2007 wb_data[0] |= (1<<5); /* STATS */ in bnx2x_update_pfc_bmac2()
2008 wb_data[1] = 0; in bnx2x_update_pfc_bmac2()
2012 wb_data[0] &= ~(1<<2); in bnx2x_update_pfc_bmac2()
2016 wb_data[0] = 0x8; in bnx2x_update_pfc_bmac2()
2017 wb_data[1] = 0; in bnx2x_update_pfc_bmac2()
2027 val = 0x8000; in bnx2x_update_pfc_bmac2()
2031 wb_data[0] = val; in bnx2x_update_pfc_bmac2()
2032 wb_data[1] = 0; in bnx2x_update_pfc_bmac2()
2037 val = 0x3; /* Enable RX and TX */ in bnx2x_update_pfc_bmac2()
2039 val |= 0x4; /* Local loopback */ in bnx2x_update_pfc_bmac2()
2046 wb_data[0] = val; in bnx2x_update_pfc_bmac2()
2047 wb_data[1] = 0; in bnx2x_update_pfc_bmac2()
2060 u32 nig_reg_rx_priority_mask_add = 0; in bnx2x_pfc_nig_rx_priority_mask()
2063 case 0: in bnx2x_pfc_nig_rx_priority_mask()
2097 return 0; in bnx2x_pfc_nig_rx_priority_mask()
2122 u32 xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; in bnx2x_update_pfc_nig()
2123 u32 llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; in bnx2x_update_pfc_nig()
2124 u32 pkt_priority_to_cos = 0; in bnx2x_update_pfc_nig()
2142 pause_enable = 0; in bnx2x_update_pfc_nig()
2143 llfc_out_en = 0; in bnx2x_update_pfc_nig()
2144 llfc_enable = 0; in bnx2x_update_pfc_nig()
2146 ppp_enable = 0; in bnx2x_update_pfc_nig()
2151 xcm_out_en = 0; in bnx2x_update_pfc_nig()
2183 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); in bnx2x_update_pfc_nig()
2194 u8 i = 0; in bnx2x_update_pfc_nig()
2197 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) in bnx2x_update_pfc_nig()
2237 return 0; in bnx2x_update_pfc()
2243 bnx2x_update_pfc_xmac(params, vars, 0); in bnx2x_update_pfc()
2248 == 0) { in bnx2x_update_pfc()
2250 bnx2x_emac_enable(params, vars, 0); in bnx2x_update_pfc()
2251 return 0; in bnx2x_update_pfc()
2258 val = 0; in bnx2x_update_pfc()
2265 return 0; in bnx2x_update_pfc()
2282 wb_data[0] = 0x3c; in bnx2x_bmac1_enable()
2283 wb_data[1] = 0; in bnx2x_bmac1_enable()
2288 wb_data[0] = ((params->mac_addr[2] << 24) | in bnx2x_bmac1_enable()
2292 wb_data[1] = ((params->mac_addr[0] << 8) | in bnx2x_bmac1_enable()
2297 val = 0x3; in bnx2x_bmac1_enable()
2299 val |= 0x4; in bnx2x_bmac1_enable()
2302 wb_data[0] = val; in bnx2x_bmac1_enable()
2303 wb_data[1] = 0; in bnx2x_bmac1_enable()
2307 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; in bnx2x_bmac1_enable()
2308 wb_data[1] = 0; in bnx2x_bmac1_enable()
2314 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; in bnx2x_bmac1_enable()
2315 wb_data[1] = 0; in bnx2x_bmac1_enable()
2319 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; in bnx2x_bmac1_enable()
2320 wb_data[1] = 0; in bnx2x_bmac1_enable()
2324 wb_data[0] = 0x1000200; in bnx2x_bmac1_enable()
2325 wb_data[1] = 0; in bnx2x_bmac1_enable()
2329 return 0; in bnx2x_bmac1_enable()
2344 wb_data[0] = 0; in bnx2x_bmac2_enable()
2345 wb_data[1] = 0; in bnx2x_bmac2_enable()
2350 wb_data[0] = 0x3c; in bnx2x_bmac2_enable()
2351 wb_data[1] = 0; in bnx2x_bmac2_enable()
2358 wb_data[0] = ((params->mac_addr[2] << 24) | in bnx2x_bmac2_enable()
2362 wb_data[1] = ((params->mac_addr[0] << 8) | in bnx2x_bmac2_enable()
2370 wb_data[0] = 0x1000200; in bnx2x_bmac2_enable()
2371 wb_data[1] = 0; in bnx2x_bmac2_enable()
2377 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; in bnx2x_bmac2_enable()
2378 wb_data[1] = 0; in bnx2x_bmac2_enable()
2383 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD; in bnx2x_bmac2_enable()
2384 wb_data[1] = 0; in bnx2x_bmac2_enable()
2388 wb_data[0] = ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVERHEAD - 2; in bnx2x_bmac2_enable()
2389 wb_data[1] = 0; in bnx2x_bmac2_enable()
2394 return 0; in bnx2x_bmac2_enable()
2401 int rc = 0; in bnx2x_bmac_enable()
2416 REG_WR(bp, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2423 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); in bnx2x_bmac_enable()
2424 REG_WR(bp, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); in bnx2x_bmac_enable()
2425 REG_WR(bp, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); in bnx2x_bmac_enable()
2426 val = 0; in bnx2x_bmac_enable()
2432 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2433 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0x0); in bnx2x_bmac_enable()
2434 REG_WR(bp, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); in bnx2x_bmac_enable()
2435 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0x1); in bnx2x_bmac_enable()
2436 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); in bnx2x_bmac_enable()
2460 wb_data[0] |= BMAC_CONTROL_RX_ENABLE; in bnx2x_set_bmac_rx()
2462 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE; in bnx2x_set_bmac_rx()
2477 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); in bnx2x_pbf_update()
2482 DP(NETIF_MSG_LINK, "init_crd 0x%x crd 0x%x\n", init_crd, crd); in bnx2x_pbf_update()
2491 DP(NETIF_MSG_LINK, "BUG! init_crd 0x%x != crd 0x%x\n", in bnx2x_pbf_update()
2503 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, 0); in bnx2x_pbf_update()
2510 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); in bnx2x_pbf_update()
2519 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", in bnx2x_pbf_update()
2529 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x1); in bnx2x_pbf_update()
2531 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0x0); in bnx2x_pbf_update()
2534 REG_WR(bp, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); in bnx2x_pbf_update()
2535 return 0; in bnx2x_pbf_update()
2556 u32 emac_base = 0; in bnx2x_get_emac_base()
2594 int rc = 0; in bnx2x_cl22_write()
2606 for (i = 0; i < 50; i++) { in bnx2x_cl22_write()
2629 int rc = 0; in bnx2x_cl22_read()
2642 for (i = 0; i < 50; i++) { in bnx2x_cl22_read()
2655 *ret_val = 0; in bnx2x_cl22_read()
2670 int rc = 0; in bnx2x_cl45_read()
2674 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); in bnx2x_cl45_read()
2687 for (i = 0; i < 50; i++) { in bnx2x_cl45_read()
2699 *ret_val = 0; in bnx2x_cl45_read()
2708 for (i = 0; i < 50; i++) { in bnx2x_cl45_read()
2721 *ret_val = 0; in bnx2x_cl45_read()
2730 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_read()
2745 int rc = 0; in bnx2x_cl45_write()
2749 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); in bnx2x_cl45_write()
2763 for (i = 0; i < 50; i++) { in bnx2x_cl45_write()
2783 for (i = 0; i < 50; i++) { in bnx2x_cl45_write()
2804 bnx2x_cl45_read(bp, phy, devad, 0xf, &temp_val); in bnx2x_cl45_write()
2822 return 0; in bnx2x_eee_has_cap()
2840 *idle_timer = 0; in bnx2x_eee_nvram_to_time()
2844 return 0; in bnx2x_eee_nvram_to_time()
2864 return 0; in bnx2x_eee_time_to_nvram()
2881 return 0; in bnx2x_eee_calc_timer()
2893 return 0; in bnx2x_eee_calc_timer()
2902 u32 eee_idle = 0, eee_mode; in bnx2x_eee_set_timers()
2913 DP(NETIF_MSG_LINK, "Error: Tx LPI is enabled with timer 0\n"); in bnx2x_eee_set_timers()
2929 return 0; in bnx2x_eee_set_timers()
2958 REG_WR(bp, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); in bnx2x_eee_disable()
2960 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); in bnx2x_eee_disable()
2964 return 0; in bnx2x_eee_disable()
2972 u16 val = 0; in bnx2x_eee_advertise()
2975 REG_WR(bp, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); in bnx2x_eee_advertise()
2979 val |= 0x8; in bnx2x_eee_advertise()
2983 val |= 0x4; in bnx2x_eee_advertise()
2991 return 0; in bnx2x_eee_advertise()
3009 u16 adv = 0, lp = 0; in bnx2x_eee_an_resolve()
3010 u32 lp_adv = 0; in bnx2x_eee_an_resolve()
3011 u8 neg = 0; in bnx2x_eee_an_resolve()
3016 if (lp & 0x2) { in bnx2x_eee_an_resolve()
3018 if (adv & 0x2) { in bnx2x_eee_an_resolve()
3024 if (lp & 0x14) { in bnx2x_eee_an_resolve()
3026 if (adv & 0x14) { in bnx2x_eee_an_resolve()
3032 if (lp & 0x68) { in bnx2x_eee_an_resolve()
3034 if (adv & 0x68) { in bnx2x_eee_an_resolve()
3073 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; in bnx2x_bsc_module_sel()
3074 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; in bnx2x_bsc_module_sel()
3076 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) in bnx2x_bsc_module_sel()
3090 int rc = 0; in bnx2x_bsc_read()
3110 /* Start xfer with 0 byte to update the address pointer ???*/ in bnx2x_bsc_read()
3114 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); in bnx2x_bsc_read()
3120 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { in bnx2x_bsc_read()
3123 DP(NETIF_MSG_LINK, "wr 0 byte timed out after %Lu ns\n", in bnx2x_bsc_read()
3145 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { in bnx2x_bsc_read()
3162 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | in bnx2x_bsc_read()
3163 ((data_array[i] & 0x0000ff00) << 8) | in bnx2x_bsc_read()
3164 ((data_array[i] & 0x00ff0000) >> 8) | in bnx2x_bsc_read()
3165 ((data_array[i] & 0xff000000) >> 24); in bnx2x_bsc_read()
3195 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { in bnx2x_phy_read()
3212 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { in bnx2x_phy_write()
3224 u8 lane = 0; in bnx2x_get_warpcore_lane()
3237 if (path_swap_ovr & 0x1) in bnx2x_get_warpcore_lane()
3238 path_swap = (path_swap_ovr & 0x2); in bnx2x_get_warpcore_lane()
3247 if (port_swap_ovr & 0x1) in bnx2x_get_warpcore_lane()
3248 port_swap = (port_swap_ovr & 0x2); in bnx2x_get_warpcore_lane()
3261 if (path_swap_ovr & 0x1) { in bnx2x_get_warpcore_lane()
3262 path_swap = (path_swap_ovr & 0x2); in bnx2x_get_warpcore_lane()
3286 (phy->addr + ser_lane) : 0; in bnx2x_set_aer_mmd()
3293 * 0x200 is the broadcast address for lanes 0,1 in bnx2x_set_aer_mmd()
3294 * 0x201 is the broadcast address for lanes 2,3 in bnx2x_set_aer_mmd()
3297 aer_val = (aer_val >> 1) | 0x200; in bnx2x_set_aer_mmd()
3299 aer_val = 0x3800 + offset - 1; in bnx2x_set_aer_mmd()
3301 aer_val = 0x3800 + offset; in bnx2x_set_aer_mmd()
3317 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); in bnx2x_set_serdes_access()
3318 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); in bnx2x_set_serdes_access()
3320 REG_WR(bp, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); in bnx2x_set_serdes_access()
3323 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); in bnx2x_set_serdes_access()
3341 REG_WR(bp, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, in bnx2x_serdes_deassert()
3353 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); in bnx2x_xgxs_specific_func()
3354 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, in bnx2x_xgxs_specific_func()
3416 DP(NETIF_MSG_LINK, "ieee_fc = 0x%x\n", *ieee_fc); in bnx2x_calc_ieee_aneg_adv()
3483 DP(NETIF_MSG_LINK, "Ext phy AN advertize 0x%x\n", val); in bnx2x_ext_phy_set_pause()
3495 case 0xb: /* 1 0 1 1 */ in bnx2x_pause_resolve()
3500 case 0xe: /* 1 1 1 0 */ in bnx2x_pause_resolve()
3505 case 0x5: /* 0 1 0 1 */ in bnx2x_pause_resolve()
3506 case 0x7: /* 0 1 1 1 */ in bnx2x_pause_resolve()
3507 case 0xd: /* 1 1 0 1 */ in bnx2x_pause_resolve()
3508 case 0xf: /* 1 1 1 1 */ in bnx2x_pause_resolve()
3527 if (pause_result & (1<<0)) in bnx2x_pause_resolve()
3543 bnx2x_cl22_read(bp, phy, 0x4, &ld_pause); in bnx2x_ext_phy_update_adv_fc()
3544 bnx2x_cl22_read(bp, phy, 0x5, &lp_pause); in bnx2x_ext_phy_update_adv_fc()
3584 DP(NETIF_MSG_LINK, "Ext PHY pause result 0x%x\n", pause_result); in bnx2x_ext_phy_update_adv_fc()
3593 u8 ret = 0; in bnx2x_ext_phy_resolve_fc()
3636 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, in bnx2x_warpcore_enable_AN_KR2()
3637 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, in bnx2x_warpcore_enable_AN_KR2()
3638 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, in bnx2x_warpcore_enable_AN_KR2()
3639 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, in bnx2x_warpcore_enable_AN_KR2()
3640 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, in bnx2x_warpcore_enable_AN_KR2()
3641 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, in bnx2x_warpcore_enable_AN_KR2()
3643 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, in bnx2x_warpcore_enable_AN_KR2()
3644 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, in bnx2x_warpcore_enable_AN_KR2()
3645 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, in bnx2x_warpcore_enable_AN_KR2()
3646 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, in bnx2x_warpcore_enable_AN_KR2()
3647 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, in bnx2x_warpcore_enable_AN_KR2()
3648 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, in bnx2x_warpcore_enable_AN_KR2()
3649 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, in bnx2x_warpcore_enable_AN_KR2()
3650 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, in bnx2x_warpcore_enable_AN_KR2()
3651 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} in bnx2x_warpcore_enable_AN_KR2()
3658 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in bnx2x_warpcore_enable_AN_KR2()
3675 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, in bnx2x_disable_kr2()
3676 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, in bnx2x_disable_kr2()
3677 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, in bnx2x_disable_kr2()
3678 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, in bnx2x_disable_kr2()
3679 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, in bnx2x_disable_kr2()
3680 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, in bnx2x_disable_kr2()
3681 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, in bnx2x_disable_kr2()
3682 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, in bnx2x_disable_kr2()
3683 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, in bnx2x_disable_kr2()
3684 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, in bnx2x_disable_kr2()
3685 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, in bnx2x_disable_kr2()
3686 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, in bnx2x_disable_kr2()
3687 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, in bnx2x_disable_kr2()
3688 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, in bnx2x_disable_kr2()
3689 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} in bnx2x_disable_kr2()
3693 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in bnx2x_disable_kr2()
3709 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); in bnx2x_warpcore_set_lpi_passthrough()
3711 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); in bnx2x_warpcore_set_lpi_passthrough()
3723 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); in bnx2x_warpcore_restart_AN_KR()
3732 u16 lane, i, cl72_ctrl, an_adv = 0, val; in bnx2x_warpcore_enable_AN_KR()
3736 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, in bnx2x_warpcore_enable_AN_KR()
3737 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, in bnx2x_warpcore_enable_AN_KR()
3738 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, in bnx2x_warpcore_enable_AN_KR()
3739 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, in bnx2x_warpcore_enable_AN_KR()
3741 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, in bnx2x_warpcore_enable_AN_KR()
3742 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, in bnx2x_warpcore_enable_AN_KR()
3743 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, in bnx2x_warpcore_enable_AN_KR()
3747 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in bnx2x_warpcore_enable_AN_KR()
3753 cl72_ctrl &= 0x08ff; in bnx2x_warpcore_enable_AN_KR()
3754 cl72_ctrl |= 0x3800; in bnx2x_warpcore_enable_AN_KR()
3766 bnx2x_cl45_read_or_write(bp, phy, MDIO_WC_DEVAD, addr, 0x1); in bnx2x_warpcore_enable_AN_KR()
3776 MDIO_AER_BLOCK_AER_REG, 0); in bnx2x_warpcore_enable_AN_KR()
3787 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, in bnx2x_warpcore_enable_AN_KR()
3788 WC_TX_DRIVER(0x02, 0x06, 0x09, 0)); in bnx2x_warpcore_enable_AN_KR()
3792 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), in bnx2x_warpcore_enable_AN_KR()
3793 WC_TX_DRIVER(0x02, 0x06, 0x09, 0)); in bnx2x_warpcore_enable_AN_KR()
3796 0x03f0); in bnx2x_warpcore_enable_AN_KR()
3799 0x03f0); in bnx2x_warpcore_enable_AN_KR()
3826 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); in bnx2x_warpcore_enable_AN_KR()
3830 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); in bnx2x_warpcore_enable_AN_KR()
3840 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), in bnx2x_warpcore_enable_AN_KR()
3844 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); in bnx2x_warpcore_enable_AN_KR()
3851 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10); in bnx2x_warpcore_enable_AN_KR()
3889 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, in bnx2x_warpcore_set_10G_KR()
3891 0x3f00}, in bnx2x_warpcore_set_10G_KR()
3892 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, in bnx2x_warpcore_set_10G_KR()
3893 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, in bnx2x_warpcore_set_10G_KR()
3894 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, in bnx2x_warpcore_set_10G_KR()
3895 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, in bnx2x_warpcore_set_10G_KR()
3897 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} in bnx2x_warpcore_set_10G_KR()
3900 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in bnx2x_warpcore_set_10G_KR()
3907 MDIO_AER_BLOCK_AER_REG, 0); in bnx2x_warpcore_set_10G_KR()
3911 val16 &= ~(0x0011 << lane); in bnx2x_warpcore_set_10G_KR()
3917 val16 |= (0x0303 << (lane << 1)); in bnx2x_warpcore_set_10G_KR()
3924 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); in bnx2x_warpcore_set_10G_KR()
3927 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); in bnx2x_warpcore_set_10G_KR()
3931 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); in bnx2x_warpcore_set_10G_KR()
3935 MDIO_WC_REG_TX66_CONTROL, 0x9); in bnx2x_warpcore_set_10G_KR()
3939 MDIO_WC_REG_RX66_CONTROL, 0xF9); in bnx2x_warpcore_set_10G_KR()
3943 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); in bnx2x_warpcore_set_10G_KR()
3945 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); in bnx2x_warpcore_set_10G_KR()
3960 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); in bnx2x_warpcore_set_10G_XFI()
3964 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); in bnx2x_warpcore_set_10G_XFI()
3967 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); in bnx2x_warpcore_set_10G_XFI()
3971 MDIO_WC_REG_FX100_CTRL1, 0xFFFA); in bnx2x_warpcore_set_10G_XFI()
3975 MDIO_WC_REG_FX100_CTRL3, 0x0080); in bnx2x_warpcore_set_10G_XFI()
3979 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); in bnx2x_warpcore_set_10G_XFI()
3984 0xFFEE); in bnx2x_warpcore_set_10G_XFI()
3991 ((val | 0x0006) & 0xFFFE)); in bnx2x_warpcore_set_10G_XFI()
3997 misc1_val &= ~(0x1f); in bnx2x_warpcore_set_10G_XFI()
4000 misc1_val |= 0x5; in bnx2x_warpcore_set_10G_XFI()
4001 tap_val = WC_TX_FIR(0x08, 0x37, 0x00); in bnx2x_warpcore_set_10G_XFI()
4002 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0); in bnx2x_warpcore_set_10G_XFI()
4011 misc1_val |= 0x9; in bnx2x_warpcore_set_10G_XFI()
4013 /* TAP values are controlled by nvram, if value there isn't 0 */ in bnx2x_warpcore_set_10G_XFI()
4017 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); in bnx2x_warpcore_set_10G_XFI()
4059 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, in bnx2x_warpcore_set_10G_XFI()
4064 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); in bnx2x_warpcore_set_10G_XFI()
4068 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); in bnx2x_warpcore_set_10G_XFI()
4074 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); in bnx2x_warpcore_set_10G_XFI()
4079 0xFFFE); in bnx2x_warpcore_set_10G_XFI()
4082 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); in bnx2x_warpcore_set_10G_XFI()
4090 /* Set global registers, so set AER lane to 0 */ in bnx2x_warpcore_set_20G_force_KR2()
4092 MDIO_AER_BLOCK_AER_REG, 0); in bnx2x_warpcore_set_20G_force_KR2()
4103 MDIO_AN_REG_CTRL, 0); in bnx2x_warpcore_set_20G_force_KR2()
4114 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); in bnx2x_warpcore_set_20G_force_KR2()
4126 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); in bnx2x_warpcore_set_20G_force_KR2()
4128 /* Enable sequencer (over lane 0) */ in bnx2x_warpcore_set_20G_force_KR2()
4130 MDIO_AER_BLOCK_AER_REG, 0); in bnx2x_warpcore_set_20G_force_KR2()
4144 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); in bnx2x_warpcore_set_20G_DXGXS()
4148 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); in bnx2x_warpcore_set_20G_DXGXS()
4151 MDIO_WC_REG_RX66_SCW0, 0xE070); in bnx2x_warpcore_set_20G_DXGXS()
4154 MDIO_WC_REG_RX66_SCW1, 0xC0D0); in bnx2x_warpcore_set_20G_DXGXS()
4157 MDIO_WC_REG_RX66_SCW2, 0xA0B0); in bnx2x_warpcore_set_20G_DXGXS()
4160 MDIO_WC_REG_RX66_SCW3, 0x8090); in bnx2x_warpcore_set_20G_DXGXS()
4163 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); in bnx2x_warpcore_set_20G_DXGXS()
4166 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); in bnx2x_warpcore_set_20G_DXGXS()
4169 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); in bnx2x_warpcore_set_20G_DXGXS()
4172 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); in bnx2x_warpcore_set_20G_DXGXS()
4176 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); in bnx2x_warpcore_set_20G_DXGXS()
4180 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); in bnx2x_warpcore_set_20G_DXGXS()
4185 (WC_TX_FIR(0x12, 0x2d, 0x00) | in bnx2x_warpcore_set_20G_DXGXS()
4188 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, in bnx2x_warpcore_set_20G_DXGXS()
4189 WC_TX_DRIVER(0x02, 0x02, 0x02, 0)); in bnx2x_warpcore_set_20G_DXGXS()
4210 0x1000); in bnx2x_warpcore_set_sgmii_speed()
4215 val16 &= 0xcebf; in bnx2x_warpcore_set_sgmii_speed()
4220 val16 |= 0x2000; in bnx2x_warpcore_set_sgmii_speed()
4223 val16 |= 0x0040; in bnx2x_warpcore_set_sgmii_speed()
4227 "Speed not supported: 0x%x\n", phy->req_line_speed); in bnx2x_warpcore_set_sgmii_speed()
4232 val16 |= 0x0100; in bnx2x_warpcore_set_sgmii_speed()
4250 digctrl_kx1 &= 0xff4a; in bnx2x_warpcore_set_sgmii_speed()
4271 (digctrl_kx1 | 0x10)); in bnx2x_warpcore_set_sgmii_speed()
4283 val |= 0xC000; in bnx2x_warpcore_reset_lane()
4285 val &= 0x3FFF; in bnx2x_warpcore_reset_lane()
4299 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, in bnx2x_warpcore_clear_regs()
4300 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, in bnx2x_warpcore_clear_regs()
4301 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, in bnx2x_warpcore_clear_regs()
4302 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, in bnx2x_warpcore_clear_regs()
4304 0x0195}, in bnx2x_warpcore_clear_regs()
4306 0x0007}, in bnx2x_warpcore_clear_regs()
4308 0x0002}, in bnx2x_warpcore_clear_regs()
4309 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, in bnx2x_warpcore_clear_regs()
4310 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, in bnx2x_warpcore_clear_regs()
4311 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, in bnx2x_warpcore_clear_regs()
4312 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} in bnx2x_warpcore_clear_regs()
4318 for (i = 0; i < ARRAY_SIZE(wc_regs); i++) in bnx2x_warpcore_clear_regs()
4324 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); in bnx2x_warpcore_clear_regs()
4334 *gpio_num = 0; in bnx2x_get_mod_abs_int_cfg()
4335 *gpio_port = 0; in bnx2x_get_mod_abs_int_cfg()
4357 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; in bnx2x_get_mod_abs_int_cfg()
4364 return 0; in bnx2x_get_mod_abs_int_cfg()
4375 &gpio_num, &gpio_port) != 0) in bnx2x_is_sfp_module_plugged()
4376 return 0; in bnx2x_is_sfp_module_plugged()
4380 if (gpio_val == 0) in bnx2x_is_sfp_module_plugged()
4383 return 0; in bnx2x_is_sfp_module_plugged()
4396 return (gp2_status_reg0 >> (8+lane)) & 0x1; in bnx2x_warpcore_get_sigdet()
4405 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0; in bnx2x_warpcore_config_runtime()
4407 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; in bnx2x_warpcore_config_runtime()
4422 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1, in bnx2x_warpcore_config_runtime()
4424 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ in bnx2x_warpcore_config_runtime()
4426 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; in bnx2x_warpcore_config_runtime()
4429 vars->rx_tx_asic_rst = 0; in bnx2x_warpcore_config_runtime()
4433 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_runtime()
4437 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); in bnx2x_warpcore_config_runtime()
4440 DP(NETIF_MSG_LINK, "0x%x retry left\n", in bnx2x_warpcore_config_runtime()
4462 bnx2x_warpcore_set_10G_XFI(phy, params, 0); in bnx2x_warpcore_config_sfi()
4465 bnx2x_warpcore_set_sgmii_speed(phy, params, 1, 0); in bnx2x_warpcore_config_sfi()
4503 "serdes_net_if = 0x%x\n", in bnx2x_warpcore_config_init()
4515 bnx2x_warpcore_set_sgmii_speed(phy, params, 0, 1); in bnx2x_warpcore_config_init()
4539 fiber_mode = 0; in bnx2x_warpcore_config_init()
4544 0); in bnx2x_warpcore_config_init()
4587 "Unsupported Serdes Net Interface 0x%x\n", in bnx2x_warpcore_config_init()
4594 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_config_init()
4603 bnx2x_sfp_e3_set_transmitter(params, phy, 0); in bnx2x_warpcore_link_reset()
4612 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); in bnx2x_warpcore_link_reset()
4615 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); in bnx2x_warpcore_link_reset()
4619 MDIO_AER_BLOCK_AER_REG, 0); in bnx2x_warpcore_link_reset()
4623 ~0x10); in bnx2x_warpcore_link_reset()
4626 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); in bnx2x_warpcore_link_reset()
4631 val16 |= (0x11 << lane); in bnx2x_warpcore_link_reset()
4633 val16 |= (0x22 << lane); in bnx2x_warpcore_link_reset()
4639 val16 &= ~(0x0303 << (lane << 1)); in bnx2x_warpcore_link_reset()
4640 val16 |= (0x0101 << (lane << 1)); in bnx2x_warpcore_link_reset()
4642 val16 &= ~(0x0c0c << (lane << 1)); in bnx2x_warpcore_link_reset()
4643 val16 |= (0x0404 << (lane << 1)); in bnx2x_warpcore_link_reset()
4668 MDIO_AER_BLOCK_AER_REG, 0); in bnx2x_set_warpcore_loopback()
4672 0x10); in bnx2x_set_warpcore_loopback()
4690 0x4000); in bnx2x_set_warpcore_loopback()
4692 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); in bnx2x_set_warpcore_loopback()
4751 vars->flow_ctrl = 0; in bnx2x_sync_link()
4789 vars->phy_link_up = 0; in bnx2x_sync_link()
4791 vars->line_speed = 0; in bnx2x_sync_link()
4844 DP(NETIF_MSG_LINK, "media_types = 0x%x\n", media_types); in bnx2x_link_status_update()
4865 DP(NETIF_MSG_LINK, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", in bnx2x_link_status_update()
4867 DP(NETIF_MSG_LINK, "line_speed %x duplex %x flow_ctrl 0x%x\n", in bnx2x_link_status_update()
4913 for (i = 0; i < MDIO_ACCESS_TIMEOUT; i++) { in bnx2x_reset_unicore()
4924 return 0; in bnx2x_reset_unicore()
4941 * No swap is 0123 => 0x1b no need to enable the swap in bnx2x_set_swap_lanes()
4952 if (rx_lane_swap != 0x1b) { in bnx2x_set_swap_lanes()
4962 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); in bnx2x_set_swap_lanes()
4965 if (tx_lane_swap != 0x1b) { in bnx2x_set_swap_lanes()
4974 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); in bnx2x_set_swap_lanes()
4991 DP(NETIF_MSG_LINK, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", in bnx2x_set_parallel_detection()
5096 0xe); in bnx2x_set_autoneg()
5127 reg_val = 0; in bnx2x_set_autoneg()
5162 DP(NETIF_MSG_LINK, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); in bnx2x_program_serdes()
5188 u16 val = 0; in bnx2x_set_brcm_cl37_advertisement()
5201 MDIO_OVER_1G_UP3, 0x400); in bnx2x_set_brcm_cl37_advertisement()
5254 "bnx2x_restart_autoneg mii_control before = 0x%x\n", in bnx2x_restart_autoneg()
5315 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", in bnx2x_initialize_sgmii_process()
5331 bnx2x_restart_autoneg(phy, params, 0); in bnx2x_initialize_sgmii_process()
5343 return 0; in bnx2x_direct_parallel_detect_used()
5368 return 0; in bnx2x_direct_parallel_detect_used()
5398 DP(NETIF_MSG_LINK, "pause_result CL73 0x%x\n", pause_result); in bnx2x_update_adv_fc()
5412 DP(NETIF_MSG_LINK, "pause_result CL37 0x%x\n", pause_result); in bnx2x_update_adv_fc()
5443 DP(NETIF_MSG_LINK, "flow_ctrl 0x%x\n", vars->flow_ctrl); in bnx2x_flow_ctrl_resolve()
5460 "rx_status(0x80b0) = 0x%x\n", rx_status); in bnx2x_check_fallback_to_cl37()
5478 "ustat_val(0x8371) = 0x%x\n", ustat_val); in bnx2x_check_fallback_to_cl37()
5494 "misc_rx_status(0x8330) = 0x%x\n", in bnx2x_check_fallback_to_cl37()
5508 0); in bnx2x_check_fallback_to_cl37()
5510 bnx2x_restart_autoneg(phy, params, 0); in bnx2x_check_fallback_to_cl37()
5580 "link speed unsupported gp_status 0x%x\n", in bnx2x_get_link_speed_duplex()
5600 "link speed unsupported gp_status 0x%x\n", in bnx2x_get_link_speed_duplex()
5607 vars->phy_link_up = 0; in bnx2x_get_link_speed_duplex()
5615 return 0; in bnx2x_get_link_speed_duplex()
5624 u16 gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; in bnx2x_link_settings_status()
5625 int rc = 0; in bnx2x_link_settings_status()
5637 DP(NETIF_MSG_LINK, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", in bnx2x_link_settings_status()
5687 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", in bnx2x_link_settings_status()
5699 int rc = 0; in bnx2x_warpcore_read_status()
5708 link_up &= 0x1; in bnx2x_warpcore_read_status()
5716 DP(NETIF_MSG_LINK, "PCS RX link status = 0x%x-->0x%x\n", in bnx2x_warpcore_read_status()
5725 DP(NETIF_MSG_LINK, "0x81d1 = 0x%x\n", gp_status1); in bnx2x_warpcore_read_status()
5798 DP(NETIF_MSG_LINK, "lane %d gp_speed 0x%x\n", lane, gp_speed); in bnx2x_warpcore_read_status()
5800 if ((lane & 1) == 0) in bnx2x_warpcore_read_status()
5802 gp_speed &= 0x3f00; in bnx2x_warpcore_read_status()
5813 DP(NETIF_MSG_LINK, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", in bnx2x_warpcore_read_status()
5835 if (lp_up2 == 0) in bnx2x_set_gmii_tx_driver()
5861 u16 mode = 0; in bnx2x_emac_program()
5864 bnx2x_bits_dis(bp, GRCBASE_EMAC0 + port*0x400 + in bnx2x_emac_program()
5888 DP(NETIF_MSG_LINK, "Invalid line_speed 0x%x\n", in bnx2x_emac_program()
5896 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, in bnx2x_emac_program()
5900 return 0; in bnx2x_emac_program()
5907 u16 bank, i = 0; in bnx2x_set_preemphasis()
5910 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; in bnx2x_set_preemphasis()
5918 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; in bnx2x_set_preemphasis()
5947 bnx2x_set_autoneg(phy, params, vars, 0); in bnx2x_xgxs_config_init()
6000 rc = bnx2x_reset_unicore(params, phy, 0); in bnx2x_prepare_xgxs()
6021 for (cnt = 0; cnt < 1000; cnt++) { in bnx2x_wait_reset_complete()
6038 DP(NETIF_MSG_LINK, "control reg 0x%x (after %d ms)\n", ctrl, cnt); in bnx2x_wait_reset_complete()
6078 DP(NETIF_MSG_LINK, "port %x, is_xgxs %x, int_status 0x%x\n", port, in bnx2x_link_int_enable()
6081 DP(NETIF_MSG_LINK, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", in bnx2x_link_int_enable()
6083 REG_RD(bp, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), in bnx2x_link_int_enable()
6084 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); in bnx2x_link_int_enable()
6086 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), in bnx2x_link_int_enable()
6087 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); in bnx2x_link_int_enable()
6093 u32 latch_status = 0; in bnx2x_rearm_latch_signal()
6102 DP(NETIF_MSG_LINK, "latch_status = 0x%x\n", latch_status); in bnx2x_rearm_latch_signal()
6119 (latch_status & 0xfffe) | (latch_status & 1)); in bnx2x_rearm_latch_signal()
6156 DP(NETIF_MSG_LINK, "Ack link up interrupt with mask 0x%x\n", in bnx2x_link_int_ack()
6167 str[0] = '\0'; in bnx2x_null_format_ver()
6168 return 0; in bnx2x_null_format_ver()
6181 ret = scnprintf(str, *len, "%x.%x", (num >> 16) & 0xFFFF, in bnx2x_format_ver()
6182 num & 0xFFFF); in bnx2x_format_ver()
6184 return 0; in bnx2x_format_ver()
6197 ret = scnprintf(str, *len, "%x.%x.%x", (num >> 16) & 0xFF, in bnx2x_3_seq_format_ver()
6198 (num >> 8) & 0xFF, num & 0xFF); in bnx2x_3_seq_format_ver()
6200 return 0; in bnx2x_3_seq_format_ver()
6207 u32 spirom_ver = 0; in bnx2x_get_ext_phy_fw_version()
6208 int status = 0; in bnx2x_get_ext_phy_fw_version()
6211 if (version == NULL || params == NULL || len == 0) in bnx2x_get_ext_phy_fw_version()
6216 version[0] = '\0'; in bnx2x_get_ext_phy_fw_version()
6226 (params->phy[EXT_PHY2].ver_addr != 0)) { in bnx2x_get_ext_phy_fw_version()
6239 *ver_p = '\0'; in bnx2x_get_ext_phy_fw_version()
6250 u32 md_devad = 0; in bnx2x_set_xgxs_loopback()
6257 port*0x18)); in bnx2x_set_xgxs_loopback()
6259 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6260 0x5); in bnx2x_set_xgxs_loopback()
6266 (MDIO_AER_BLOCK_AER_REG & 0xf)), in bnx2x_set_xgxs_loopback()
6267 0x2800); in bnx2x_set_xgxs_loopback()
6272 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), in bnx2x_set_xgxs_loopback()
6273 0x6041); in bnx2x_set_xgxs_loopback()
6280 REG_WR(bp, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, in bnx2x_set_xgxs_loopback()
6288 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), in bnx2x_set_xgxs_loopback()
6292 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), in bnx2x_set_xgxs_loopback()
6303 int rc = 0; in bnx2x_set_led()
6309 DP(NETIF_MSG_LINK, "speed 0x%x, hw_led_mode 0x%x\n", in bnx2x_set_led()
6322 REG_WR(bp, NIG_REG_LED_10G_P0 + port*4, 0); in bnx2x_set_led()
6354 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6380 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6387 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0); in bnx2x_set_led()
6405 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); in bnx2x_set_led()
6428 port*4, 0); in bnx2x_set_led()
6451 u16 gp_status = 0, phy_index = 0; in bnx2x_test_link()
6452 u8 ext_phy_link_up = 0, serdes_phy_type; in bnx2x_test_link()
6472 gp_status = ((gp_status >> 8) & 0xf) | in bnx2x_test_link()
6473 ((gp_status >> 12) & 0xf); in bnx2x_test_link()
6489 return 0; in bnx2x_test_link()
6494 return 0; in bnx2x_test_link()
6524 return 0; in bnx2x_test_link()
6603 return 0; in bnx2x_link_initialize()
6611 (0x1ff << (params->port*16))); in bnx2x_int_link_reset()
6640 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); in bnx2x_update_link_down()
6647 vars->line_speed = 0; in bnx2x_update_link_down()
6655 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_update_link_down()
6661 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); in bnx2x_update_link_down()
6666 0); in bnx2x_update_link_down()
6668 0); in bnx2x_update_link_down()
6673 bnx2x_set_xmac_rxtx(params, 0); in bnx2x_update_link_down()
6674 bnx2x_set_umac_rxtx(params, 0); in bnx2x_update_link_down()
6677 return 0; in bnx2x_update_link_down()
6686 int rc = 0; in bnx2x_update_link_up()
6701 if (bnx2x_xmac_enable(params, vars, 0) == in bnx2x_update_link_up()
6704 vars->link_up = 0; in bnx2x_update_link_up()
6709 bnx2x_umac_enable(params, vars, 0); in bnx2x_update_link_up()
6720 (params->port << 2), 0xfc20); in bnx2x_update_link_up()
6726 if (bnx2x_bmac_enable(params, vars, 0, 1) == in bnx2x_update_link_up()
6729 vars->link_up = 0; in bnx2x_update_link_up()
6738 bnx2x_emac_enable(params, vars, 0); in bnx2x_update_link_up()
6755 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); in bnx2x_update_link_up()
6763 bnx2x_check_half_open_conn(params, vars, 0); in bnx2x_update_link_up()
6783 val = 0; in bnx2x_chng_link_count()
6808 u8 ext_phy_link_up = 0, cur_link_up; in bnx2x_link_update()
6809 int rc = 0; in bnx2x_link_update()
6810 u8 is_mi_int = 0; in bnx2x_link_update()
6811 u16 ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; in bnx2x_link_update()
6817 phy_vars[phy_index].flow_ctrl = 0; in bnx2x_link_update()
6818 phy_vars[phy_index].link_status = 0; in bnx2x_link_update()
6819 phy_vars[phy_index].line_speed = 0; in bnx2x_link_update()
6821 phy_vars[phy_index].phy_link_up = 0; in bnx2x_link_update()
6822 phy_vars[phy_index].link_up = 0; in bnx2x_link_update()
6823 phy_vars[phy_index].fault_detected = 0; in bnx2x_link_update()
6831 DP(NETIF_MSG_LINK, "port %x, XGXS?%x, int_status 0x%x\n", in bnx2x_link_update()
6836 port*0x18) > 0); in bnx2x_link_update()
6837 DP(NETIF_MSG_LINK, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", in bnx2x_link_update()
6840 REG_RD(bp, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); in bnx2x_link_update()
6843 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), in bnx2x_link_update()
6844 REG_RD(bp, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); in bnx2x_link_update()
6848 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_update()
6904 "mpc=0x%x. DISABLING LINK !!!\n", in bnx2x_link_update()
6906 ext_phy_link_up = 0; in bnx2x_link_update()
6973 DP(NETIF_MSG_LINK, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," in bnx2x_link_update()
6988 vars->phy_link_up = 0; in bnx2x_link_update()
6991 0); in bnx2x_link_update()
7035 (phy_vars[active_external_phy].fault_detected == 0)); in bnx2x_link_update()
7053 bnx2x_fw_command(bp, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); in bnx2x_link_update()
7073 DP(NETIF_MSG_LINK, "FW version 0x%x:0x%x for port %d\n", in bnx2x_save_spirom_version()
7107 if ((val & (1<<0)) == 0) in bnx2x_ext_phy_10G_an_resolve()
7143 DP(NETIF_MSG_LINK, "Ext PHY CL37 pause result 0x%x\n", in bnx2x_8073_resolve_fc()
7151 u32 count = 0; in bnx2x_8073_8727_external_rom_boot()
7153 int rc = 0; in bnx2x_8073_8727_external_rom_boot()
7160 0x0001); in bnx2x_8073_8727_external_rom_boot()
7166 0x008c); in bnx2x_8073_8727_external_rom_boot()
7170 MDIO_PMA_REG_MISC_CTRL1, 0x0001); in bnx2x_8073_8727_external_rom_boot()
7193 "Download failed. fw version = 0x%x\n", in bnx2x_8073_8727_external_rom_boot()
7207 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || in bnx2x_8073_8727_external_rom_boot()
7208 ((fw_msgout & 0xff) != 0x03 && (phy->type == in bnx2x_8073_8727_external_rom_boot()
7214 MDIO_PMA_REG_MISC_CTRL1, 0x0000); in bnx2x_8073_8727_external_rom_boot()
7219 "Download complete. fw version = 0x%x\n", in bnx2x_8073_8727_external_rom_boot()
7240 return 0; in bnx2x_8073_is_snr_needed()
7247 /* SNR should be applied only for version 0x102 */ in bnx2x_8073_is_snr_needed()
7248 if (val != 0x102) in bnx2x_8073_is_snr_needed()
7249 return 0; in bnx2x_8073_is_snr_needed()
7262 if (val > 0) { in bnx2x_8073_xaui_wa()
7264 return 0; in bnx2x_8073_xaui_wa()
7272 for (cnt = 0; cnt < 1000; cnt++) { in bnx2x_8073_xaui_wa()
7277 /* If bit [14] = 0 or bit [13] = 0, continue on with in bnx2x_8073_xaui_wa()
7283 return 0; in bnx2x_8073_xaui_wa()
7286 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's in bnx2x_8073_xaui_wa()
7291 for (cnt1 = 0; cnt1 < 1000; cnt1++) { in bnx2x_8073_xaui_wa()
7298 return 0; in bnx2x_8073_xaui_wa()
7314 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); in bnx2x_807x_force_10G()
7316 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); in bnx2x_807x_force_10G()
7318 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); in bnx2x_807x_force_10G()
7320 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); in bnx2x_807x_force_10G()
7351 "Ext phy AN advertize cl37 0x%x\n", cl37_val); in bnx2x_8073_set_pause_cl37()
7369 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); in bnx2x_8073_specific_func()
7379 u16 val = 0, tmp1; in bnx2x_8073_config_init()
7403 DP(NETIF_MSG_LINK, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); in bnx2x_8073_config_init()
7440 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); in bnx2x_8073_config_init()
7453 val = 0; in bnx2x_8073_config_init()
7463 DP(NETIF_MSG_LINK, "807x autoneg val = 0x%x\n", val); in bnx2x_8073_config_init()
7478 if (phy_ver > 0) in bnx2x_8073_config_init()
7481 tmp1 &= 0xfffe; in bnx2x_8073_config_init()
7484 tmp1 &= 0xfffe; in bnx2x_8073_config_init()
7493 0x20 : 0x40))); in bnx2x_8073_config_init()
7496 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); in bnx2x_8073_config_init()
7505 0xFB0C); in bnx2x_8073_config_init()
7516 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in bnx2x_8073_config_init()
7518 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); in bnx2x_8073_config_init()
7526 u8 link_up = 0; in bnx2x_8073_read_status()
7528 u16 link_status = 0; in bnx2x_8073_read_status()
7529 u16 an1000_status = 0; in bnx2x_8073_read_status()
7534 DP(NETIF_MSG_LINK, "8703 LASI status 0x%x\n", val1); in bnx2x_8073_read_status()
7541 DP(NETIF_MSG_LINK, "807x PCS status 0x%x->0x%x\n", val2, val1); in bnx2x_8073_read_status()
7550 DP(NETIF_MSG_LINK, "KR 0x9003 0x%x\n", val2); in bnx2x_8073_read_status()
7555 DP(NETIF_MSG_LINK, "KR PCS status 0x%x\n", val2); in bnx2x_8073_read_status()
7562 DP(NETIF_MSG_LINK, "PMA_REG_STATUS=0x%x\n", val1); in bnx2x_8073_read_status()
7566 if (bnx2x_8073_xaui_wa(bp, phy) != 0) in bnx2x_8073_read_status()
7567 return 0; in bnx2x_8073_read_status()
7579 DP(NETIF_MSG_LINK, "KR PMA status 0x%x->0x%x," in bnx2x_8073_read_status()
7580 "an_link_status=0x%x\n", val2, val1, an1000_status); in bnx2x_8073_read_status()
7590 0x26BC); in bnx2x_8073_read_status()
7595 0x0333); in bnx2x_8073_read_status()
7601 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ in bnx2x_8073_read_status()
7612 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { in bnx2x_8073_read_status()
7618 link_up = 0; in bnx2x_8073_read_status()
7696 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8705_config_init()
7700 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); in bnx2x_8705_config_init()
7702 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); in bnx2x_8705_config_init()
7704 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); in bnx2x_8705_config_init()
7706 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); in bnx2x_8705_config_init()
7707 /* BCM8705 doesn't have microcode, hence the 0 */ in bnx2x_8705_config_init()
7708 bnx2x_save_spirom_version(bp, params->port, params->shmem_base, 0); in bnx2x_8705_config_init()
7715 u8 link_up = 0; in bnx2x_8705_read_status()
7721 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); in bnx2x_8705_read_status()
7725 DP(NETIF_MSG_LINK, "8705 LASI status 0x%x\n", val1); in bnx2x_8705_read_status()
7731 MDIO_PMA_DEVAD, 0xc809, &val1); in bnx2x_8705_read_status()
7733 MDIO_PMA_DEVAD, 0xc809, &val1); in bnx2x_8705_read_status()
7735 DP(NETIF_MSG_LINK, "8705 1.c809 val=0x%x\n", val1); in bnx2x_8705_read_status()
7736 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); in bnx2x_8705_read_status()
7836 DP(NETIF_MSG_LINK, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); in bnx2x_sfp_e1e2_set_transmitter()
7859 u16 val = 0; in bnx2x_8726_read_sfp_module_eeprom()
7863 "Reading from eeprom is limited to 0xf\n"); in bnx2x_8726_read_sfp_module_eeprom()
7879 0x2c0f); in bnx2x_8726_read_sfp_module_eeprom()
7882 for (i = 0; i < 100; i++) { in bnx2x_8726_read_sfp_module_eeprom()
7895 "Got bad status 0x%x when reading from SFP+ EEPROM\n", in bnx2x_8726_read_sfp_module_eeprom()
7901 for (i = 0; i < byte_cnt; i++) { in bnx2x_8726_read_sfp_module_eeprom()
7908 for (i = 0; i < 100; i++) { in bnx2x_8726_read_sfp_module_eeprom()
7914 return 0; in bnx2x_8726_read_sfp_module_eeprom()
7947 int rc = 0; in bnx2x_warpcore_read_sfp_module_eeprom()
7948 u8 i, j = 0, cnt = 0; in bnx2x_warpcore_read_sfp_module_eeprom()
7960 addr32 = addr & (~0x3); in bnx2x_warpcore_read_sfp_module_eeprom()
7963 bnx2x_warpcore_power_module(params, 0); in bnx2x_warpcore_read_sfp_module_eeprom()
7968 rc = bnx2x_bsc_read(params, bp, dev_addr, addr32, 0, byte_cnt, in bnx2x_warpcore_read_sfp_module_eeprom()
7970 } while ((rc != 0) && (++cnt < I2C_WA_RETRY_CNT)); in bnx2x_warpcore_read_sfp_module_eeprom()
7972 if (rc == 0) { in bnx2x_warpcore_read_sfp_module_eeprom()
7992 "Reading from eeprom is limited to 0xf\n"); in bnx2x_8727_read_sfp_module_eeprom()
8025 0x8004, in bnx2x_8727_read_sfp_module_eeprom()
8032 0x8002); in bnx2x_8727_read_sfp_module_eeprom()
8039 for (i = 0; i < 100; i++) { in bnx2x_8727_read_sfp_module_eeprom()
8052 "Got bad status 0x%x when reading from SFP+ EEPROM\n", in bnx2x_8727_read_sfp_module_eeprom()
8058 for (i = 0; i < byte_cnt; i++) { in bnx2x_8727_read_sfp_module_eeprom()
8065 for (i = 0; i < 100; i++) { in bnx2x_8727_read_sfp_module_eeprom()
8071 return 0; in bnx2x_8727_read_sfp_module_eeprom()
8081 int rc = 0; in bnx2x_read_sfp_module_eeprom()
8087 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { in bnx2x_read_sfp_module_eeprom()
8088 DP(NETIF_MSG_LINK, "invalid dev_addr 0x%x\n", dev_addr); in bnx2x_read_sfp_module_eeprom()
8107 while (!rc && (byte_cnt > 0)) { in bnx2x_read_sfp_module_eeprom()
8111 user_data, 0); in bnx2x_read_sfp_module_eeprom()
8124 u32 sync_offset = 0, phy_idx, media_types; in bnx2x_get_edc_mode()
8125 u8 val[SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0; in bnx2x_get_edc_mode()
8132 0, in bnx2x_get_edc_mode()
8134 (u8 *)val) != 0) { in bnx2x_get_edc_mode()
8183 SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) && in bnx2x_get_edc_mode()
8184 (val[SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) { in bnx2x_get_edc_mode()
8200 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_get_edc_mode()
8205 int idx, cfg_idx = 0; in bnx2x_get_edc_mode()
8218 DP(NETIF_MSG_LINK, "Unable to determine module type 0x%x !!!\n", in bnx2x_get_edc_mode()
8245 options) != 0) { in bnx2x_get_edc_mode()
8250 if ((options[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) in bnx2x_get_edc_mode()
8255 DP(NETIF_MSG_LINK, "EDC mode is set to 0x%x\n", *edc_mode); in bnx2x_get_edc_mode()
8256 return 0; in bnx2x_get_edc_mode()
8276 return 0; in bnx2x_verify_sfp_module()
8303 return 0; in bnx2x_verify_sfp_module()
8313 vendor_name[0] = '\0'; in bnx2x_verify_sfp_module()
8315 vendor_name[SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; in bnx2x_verify_sfp_module()
8322 vendor_pn[0] = '\0'; in bnx2x_verify_sfp_module()
8324 vendor_pn[SFP_EEPROM_PART_NO_SIZE] = '\0'; in bnx2x_verify_sfp_module()
8347 for (timeout = 0; timeout < 60; timeout++) { in bnx2x_wait_for_sfp_module_initialized()
8356 if (rc == 0) { in bnx2x_wait_for_sfp_module_initialized()
8360 return 0; in bnx2x_wait_for_sfp_module_initialized()
8375 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for in bnx2x_8727_power_module()
8377 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 in bnx2x_8727_power_module()
8411 DP(NETIF_MSG_LINK, "Current Limiting mode is 0x%x\n", in bnx2x_8726_set_limiting_mode()
8428 return 0; in bnx2x_8726_set_limiting_mode()
8433 0); in bnx2x_8726_set_limiting_mode()
8437 0x128); in bnx2x_8726_set_limiting_mode()
8441 0x4008); in bnx2x_8726_set_limiting_mode()
8445 0xaaaa); in bnx2x_8726_set_limiting_mode()
8447 return 0; in bnx2x_8726_set_limiting_mode()
8474 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); in bnx2x_8727_set_limiting_mode()
8481 return 0; in bnx2x_8727_set_limiting_mode()
8492 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_8727_specific_func()
8504 0); in bnx2x_8727_specific_func()
8506 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); in bnx2x_8727_specific_func()
8518 val &= 0xff8f; /* Reset bits 4-6 */ in bnx2x_8727_specific_func()
8524 DP(NETIF_MSG_LINK, "Function 0x%x not supported by 8727\n", in bnx2x_8727_specific_func()
8557 DP(NETIF_MSG_LINK, "Error: Invalid fault led mode 0x%x\n", in bnx2x_set_e1e2_module_fault_led()
8596 bnx2x_warpcore_power_module(params, 0); in bnx2x_warpcore_hw_reset()
8598 REG_WR(bp, MISC_REG_WC0_RESET, 0x0c0e); in bnx2x_warpcore_hw_reset()
8602 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_ANA, 0); in bnx2x_warpcore_hw_reset()
8603 REG_WR(bp, MISC_REG_LCPLL_E40_RESETB_DIG, 0); in bnx2x_warpcore_hw_reset()
8629 u16 val = 0; in bnx2x_warpcore_set_limiting_mode()
8637 val &= ~(0xf << (lane << 2)); in bnx2x_warpcore_set_limiting_mode()
8661 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_warpcore_set_limiting_mode()
8688 int rc = 0; in bnx2x_sfp_module_detection()
8699 if (bnx2x_get_edc_mode(phy, params, &edc_mode) != 0) { in bnx2x_sfp_module_detection()
8702 } else if (bnx2x_verify_sfp_module(phy, params) != 0) { in bnx2x_sfp_module_detection()
8714 bnx2x_power_sfp_module(params, phy, 0); in bnx2x_sfp_module_detection()
8733 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_sfp_module_detection()
8765 if (gpio_val == 0) { in bnx2x_handle_module_detect_int()
8773 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) { in bnx2x_handle_module_detect_int()
8790 bnx2x_warpcore_reset_lane(bp, phy, 0); in bnx2x_handle_module_detect_int()
8824 if (alarm_status & (1<<0)) in bnx2x_sfp_mask_fault()
8825 val &= ~(1<<0); in bnx2x_sfp_mask_fault()
8827 val |= (1<<0); in bnx2x_sfp_mask_fault()
8837 u8 link_up = 0; in bnx2x_8706_8726_read_status()
8853 DP(NETIF_MSG_LINK, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); in bnx2x_8706_8726_read_status()
8864 DP(NETIF_MSG_LINK, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" in bnx2x_8706_8726_read_status()
8865 " link_status 0x%x\n", rx_sd, pcs_status, val2); in bnx2x_8706_8726_read_status()
8866 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status in bnx2x_8706_8726_read_status()
8869 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); in bnx2x_8706_8726_read_status()
8885 if (val1 & (1<<0)) in bnx2x_8706_8726_read_status()
8907 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); in bnx2x_8706_config_init()
8911 for (cnt = 0; cnt < 100; cnt++) { in bnx2x_8706_config_init()
8923 for (i = 0; i < 4; i++) { in bnx2x_8706_config_init()
8929 val &= ~0x7; in bnx2x_8706_config_init()
8931 val |= (phy->rx_preemphasis[i] & 0x7); in bnx2x_8706_config_init()
8933 " reg 0x%x <-- val 0x%x\n", reg, val); in bnx2x_8706_config_init()
8943 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); in bnx2x_8706_config_init()
8946 0); in bnx2x_8706_config_init()
8956 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); in bnx2x_8706_config_init()
8960 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); in bnx2x_8706_config_init()
8963 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); in bnx2x_8706_config_init()
8970 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in bnx2x_8706_config_init()
8973 0x0400); in bnx2x_8706_config_init()
8976 0x0004); in bnx2x_8706_config_init()
8993 tmp1 |= 0x1; in bnx2x_8706_config_init()
9014 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); in bnx2x_8726_config_loopback()
9026 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); in bnx2x_8726_external_rom_boot()
9036 MDIO_PMA_REG_MISC_CTRL1, 0x0001); in bnx2x_8726_external_rom_boot()
9049 MDIO_PMA_REG_MISC_CTRL1, 0x0000); in bnx2x_8726_external_rom_boot()
9068 link_up = 0; in bnx2x_8726_read_status()
9069 vars->line_speed = 0; in bnx2x_8726_read_status()
9098 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); in bnx2x_8726_config_init()
9100 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); in bnx2x_8726_config_init()
9102 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); in bnx2x_8726_config_init()
9105 0x400); in bnx2x_8726_config_init()
9116 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); in bnx2x_8726_config_init()
9118 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); in bnx2x_8726_config_init()
9120 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); in bnx2x_8726_config_init()
9122 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); in bnx2x_8726_config_init()
9124 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); in bnx2x_8726_config_init()
9129 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); in bnx2x_8726_config_init()
9132 0x400); in bnx2x_8726_config_init()
9143 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", in bnx2x_8726_config_init()
9144 phy->tx_preemphasis[0], in bnx2x_8726_config_init()
9149 phy->tx_preemphasis[0]); in bnx2x_8726_config_init()
9166 MDIO_PMA_REG_GEN_CTRL, 0x0001); in bnx2x_8726_link_reset()
9177 u16 led_mode_bitmask = 0; in bnx2x_8727_set_link_led()
9178 u16 gpio_pins_bitmask = 0; in bnx2x_8727_set_link_led()
9186 led_mode_bitmask = 0; in bnx2x_8727_set_link_led()
9187 gpio_pins_bitmask = 0x03; in bnx2x_8727_set_link_led()
9190 led_mode_bitmask = 0; in bnx2x_8727_set_link_led()
9191 gpio_pins_bitmask = 0x02; in bnx2x_8727_set_link_led()
9194 led_mode_bitmask = 0x60; in bnx2x_8727_set_link_led()
9195 gpio_pins_bitmask = 0x11; in bnx2x_8727_set_link_led()
9202 val &= 0xff8f; in bnx2x_8727_set_link_led()
9212 val &= 0xffe0; in bnx2x_8727_set_link_led()
9244 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); in bnx2x_8727_config_speed()
9246 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); in bnx2x_8727_config_speed()
9249 DP(NETIF_MSG_LINK, "1.7 = 0x%x\n", tmp1); in bnx2x_8727_config_speed()
9271 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); in bnx2x_8727_config_speed()
9273 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); in bnx2x_8727_config_speed()
9280 0x0020); in bnx2x_8727_config_speed()
9282 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); in bnx2x_8727_config_speed()
9284 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); in bnx2x_8727_config_speed()
9287 0x0008); in bnx2x_8727_config_speed()
9321 bnx2x_set_disable_pmd_transmit(params, phy, 0); in bnx2x_8727_config_init()
9337 DP(NETIF_MSG_LINK, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", in bnx2x_8727_config_init()
9338 phy->tx_preemphasis[0], in bnx2x_8727_config_init()
9342 phy->tx_preemphasis[0]); in bnx2x_8727_config_init()
9362 tmp2 |= 0x1000; in bnx2x_8727_config_init()
9363 tmp2 &= 0xFFEF; in bnx2x_8727_config_init()
9371 (tmp2 & 0x7fff)); in bnx2x_8727_config_init()
9444 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_8727_handle_mod_abs()
9446 if (bnx2x_wait_for_sfp_module_initialized(phy, params) == 0) in bnx2x_8727_handle_mod_abs()
9455 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", in bnx2x_8727_handle_mod_abs()
9466 u8 link_up = 0, oc_port = params->port; in bnx2x_8727_read_status()
9467 u16 link_status = 0; in bnx2x_8727_read_status()
9475 return 0; in bnx2x_8727_read_status()
9481 vars->line_speed = 0; in bnx2x_8727_read_status()
9482 DP(NETIF_MSG_LINK, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); in bnx2x_8727_read_status()
9490 DP(NETIF_MSG_LINK, "8727 LASI status 0x%x\n", val1); in bnx2x_8727_read_status()
9505 if ((val1 & (1<<8)) == 0) { in bnx2x_8727_read_status()
9536 bnx2x_8727_power_module(params->bp, phy, 0); in bnx2x_8727_read_status()
9537 return 0; in bnx2x_8727_read_status()
9555 return 0; in bnx2x_8727_read_status()
9562 /* Bits 0..2 --> speed detected, in bnx2x_8727_read_status()
9570 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { in bnx2x_8727_read_status()
9576 link_up = 0; in bnx2x_8727_read_status()
9589 if (val1 & (1<<0)) { in bnx2x_8727_read_status()
9597 DP(NETIF_MSG_LINK, "duplex = 0x%x\n", vars->duplex); in bnx2x_8727_read_status()
9628 bnx2x_sfp_set_transmitter(params, phy, 0); in bnx2x_8727_link_reset()
9630 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); in bnx2x_8727_link_reset()
9650 {MDIO_PMA_DEVAD, 0xA819, 0x0014}, in bnx2x_save_848xx_spirom_version()
9651 {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, in bnx2x_save_848xx_spirom_version()
9652 {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, in bnx2x_save_848xx_spirom_version()
9653 {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, in bnx2x_save_848xx_spirom_version()
9654 {MDIO_PMA_DEVAD, 0xA817, 0x0009} in bnx2x_save_848xx_spirom_version()
9659 bnx2x_cl45_read(bp, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9661 fw_ver1 &= 0xfff; in bnx2x_save_848xx_spirom_version()
9665 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ in bnx2x_save_848xx_spirom_version()
9666 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in bnx2x_save_848xx_spirom_version()
9670 for (cnt = 0; cnt < 100; cnt++) { in bnx2x_save_848xx_spirom_version()
9671 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9679 bnx2x_save_spirom_version(bp, port, 0, in bnx2x_save_848xx_spirom_version()
9685 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ in bnx2x_save_848xx_spirom_version()
9686 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); in bnx2x_save_848xx_spirom_version()
9687 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); in bnx2x_save_848xx_spirom_version()
9688 bnx2x_cl45_write(bp, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); in bnx2x_save_848xx_spirom_version()
9689 for (cnt = 0; cnt < 100; cnt++) { in bnx2x_save_848xx_spirom_version()
9690 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA818, &val); in bnx2x_save_848xx_spirom_version()
9698 bnx2x_save_spirom_version(bp, port, 0, in bnx2x_save_848xx_spirom_version()
9704 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); in bnx2x_save_848xx_spirom_version()
9706 bnx2x_cl45_read(bp, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); in bnx2x_save_848xx_spirom_version()
9718 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, in bnx2x_848xx_set_led()
9719 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, in bnx2x_848xx_set_led()
9720 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, in bnx2x_848xx_set_led()
9723 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} in bnx2x_848xx_set_led()
9731 0x90); in bnx2x_848xx_set_led()
9732 led3_blink_rate = 0x000f; in bnx2x_848xx_set_led()
9734 led3_blink_rate = 0x0000; in bnx2x_848xx_set_led()
9746 val &= 0xFE00; in bnx2x_848xx_set_led()
9747 val |= 0x0092; in bnx2x_848xx_set_led()
9756 for (i = 0; i < ARRAY_SIZE(reg_set); i++) in bnx2x_848xx_set_led()
9810 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); in bnx2x_848xx_cmn_config_init()
9891 (1<<15 | 1<<9 | 7<<0)); in bnx2x_848xx_cmn_config_init()
9903 (1<<15 | 1<<9 | 7<<0)); in bnx2x_848xx_cmn_config_init()
9918 ((autoneg_val & (1<<12)) == 0)) in bnx2x_848xx_cmn_config_init()
9934 0x1000); in bnx2x_848xx_cmn_config_init()
9937 0x3200); in bnx2x_848xx_cmn_config_init()
9944 return 0; in bnx2x_848xx_cmn_config_init()
9983 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { in bnx2x_84858_cmd_hdlr()
10000 for (idx = 0; idx < argc; idx++) { in bnx2x_84858_cmd_hdlr()
10017 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { in bnx2x_84858_cmd_hdlr()
10035 for (idx = 0; idx < argc; idx++) { in bnx2x_84858_cmd_hdlr()
10041 return 0; in bnx2x_84858_cmd_hdlr()
10051 int rc = 0; in bnx2x_84833_cmd_hdlr()
10060 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { in bnx2x_84833_cmd_hdlr()
10083 for (idx = 0; idx < argc; idx++) { in bnx2x_84833_cmd_hdlr()
10092 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) { in bnx2x_84833_cmd_hdlr()
10105 if (process == PHY84833_MB_PROCESS3 && rc == 0) { in bnx2x_84833_cmd_hdlr()
10107 for (idx = 0; idx < argc; idx++) { in bnx2x_84833_cmd_hdlr()
10158 if (pair_swap == 0) in bnx2x_848xx_pair_swap_cfg()
10159 return 0; in bnx2x_848xx_pair_swap_cfg()
10167 if (status == 0) in bnx2x_848xx_pair_swap_cfg()
10168 DP(NETIF_MSG_LINK, "Pairswap OK, val=0x%x\n", data[1]); in bnx2x_848xx_pair_swap_cfg()
10182 for (idx = 0; idx < 2; idx++) { in bnx2x_84833_get_reset_gpios()
10186 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); in bnx2x_84833_get_reset_gpios()
10193 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); in bnx2x_84833_get_reset_gpios()
10196 for (idx = 0; idx < 2; idx++) { in bnx2x_84833_get_reset_gpios()
10199 dev_info.port_hw_config[0].default_cfg)); in bnx2x_84833_get_reset_gpios()
10205 reset_gpios = (u8)(reset_pin[0] | reset_pin[1]); in bnx2x_84833_get_reset_gpios()
10230 shmem_base_path[0] = params->shmem_base; in bnx2x_84833_hw_reset_phy()
10238 DP(NETIF_MSG_LINK, "84833 hw reset on pin values 0x%x\n", in bnx2x_84833_hw_reset_phy()
10248 u16 cmd_args = 0; in bnx2x_8483x_disable_eee()
10291 int rc = 0; in bnx2x_848x3_config_init()
10308 MDIO_PMA_REG_CTRL, 0x8000); in bnx2x_848x3_config_init()
10322 bnx2x_set_autoneg(¶ms->phy[INT_PHY], params, vars, 0); in bnx2x_848x3_config_init()
10372 initialize = 0; in bnx2x_848x3_config_init()
10380 DP(NETIF_MSG_LINK, "Multi_phy config = 0x%x, Media control = 0x%x\n", in bnx2x_848x3_config_init()
10387 cmd_args[0] = 0x0; in bnx2x_848x3_config_init()
10388 cmd_args[1] = 0x0; in bnx2x_848x3_config_init()
10452 val |= 0x4000; in bnx2x_848x3_config_init()
10458 val |= 0x1; in bnx2x_848x3_config_init()
10462 /* Enable expansion register 0x46 (Pattern Generator status) */ in bnx2x_848x3_config_init()
10464 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf46); in bnx2x_848x3_config_init()
10468 val |= 0x4000; in bnx2x_848x3_config_init()
10488 u8 link_up = 0; in bnx2x_848xx_read_status()
10494 MDIO_AN_DEVAD, 0xFFFA, &val1); in bnx2x_848xx_read_status()
10498 DP(NETIF_MSG_LINK, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); in bnx2x_848xx_read_status()
10509 /* Enable expansion register 0x42 (Operation mode status) */ in bnx2x_848xx_read_status()
10512 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); in bnx2x_848xx_read_status()
10520 DP(NETIF_MSG_LINK, "Legacy speed status = 0x%x\n", in bnx2x_848xx_read_status()
10524 if (legacy_speed == (0<<9)) in bnx2x_848xx_read_status()
10531 vars->line_speed = 0; in bnx2x_848xx_read_status()
10532 link_up = 0; in bnx2x_848xx_read_status()
10557 if ((val & (1<<0)) == 0) in bnx2x_848xx_read_status()
10615 num = ((raw_ver & 0xF80) >> 7) << 16 | ((raw_ver & 0x7F) << 8) | in bnx2x_8485x_format_ver()
10616 ((raw_ver & 0xF000) >> 12); in bnx2x_8485x_format_ver()
10624 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); in bnx2x_848xx_format_ver()
10632 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); in bnx2x_8481_hw_reset()
10641 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); in bnx2x_8481_link_reset()
10688 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OFF\n", port); in bnx2x_848xx_set_link_led()
10697 0x0); in bnx2x_848xx_set_link_led()
10702 0x0); in bnx2x_848xx_set_link_led()
10707 0x0); in bnx2x_848xx_set_link_led()
10712 0x0); in bnx2x_848xx_set_link_led()
10719 0x0); in bnx2x_848xx_set_link_led()
10727 0x0); in bnx2x_848xx_set_link_led()
10732 0x0); in bnx2x_848xx_set_link_led()
10738 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE FRONT PANEL OFF\n", in bnx2x_848xx_set_link_led()
10748 0x0); in bnx2x_848xx_set_link_led()
10753 0x0); in bnx2x_848xx_set_link_led()
10758 0x0); in bnx2x_848xx_set_link_led()
10763 0x20); in bnx2x_848xx_set_link_led()
10769 0x0); in bnx2x_848xx_set_link_led()
10790 0x0); in bnx2x_848xx_set_link_led()
10798 0x0); in bnx2x_848xx_set_link_led()
10803 0x0); in bnx2x_848xx_set_link_led()
10809 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE ON\n", port); in bnx2x_848xx_set_link_led()
10818 val &= 0x8000; in bnx2x_848xx_set_link_led()
10819 val |= 0x2492; in bnx2x_848xx_set_link_led()
10830 0x0); in bnx2x_848xx_set_link_led()
10835 0x20); in bnx2x_848xx_set_link_led()
10840 0x20); in bnx2x_848xx_set_link_led()
10845 0x0); in bnx2x_848xx_set_link_led()
10850 0x20); in bnx2x_848xx_set_link_led()
10885 0x20); in bnx2x_848xx_set_link_led()
10890 0x20); in bnx2x_848xx_set_link_led()
10897 DP(NETIF_MSG_LINK, "Port 0x%x: LED MODE OPER\n", port); in bnx2x_848xx_set_link_led()
10915 0xa492); in bnx2x_848xx_set_link_led()
10922 0x10); in bnx2x_848xx_set_link_led()
10927 0x80); in bnx2x_848xx_set_link_led()
10932 0x98); in bnx2x_848xx_set_link_led()
10937 0x40); in bnx2x_848xx_set_link_led()
10946 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; in bnx2x_848xx_set_link_led()
10969 0x18); in bnx2x_848xx_set_link_led()
10973 0x06); in bnx2x_848xx_set_link_led()
10983 0x40); in bnx2x_848xx_set_link_led()
11015 /* Configure LED4: set to INTR (0x6). */ in bnx2x_54618se_specific_func()
11016 /* Accessing shadow register 0xe. */ in bnx2x_54618se_specific_func()
11023 temp &= ~(0xf << 4); in bnx2x_54618se_specific_func()
11024 temp |= (0x6 << 4); in bnx2x_54618se_specific_func()
11067 MDIO_PMA_REG_CTRL, 0x8000); in bnx2x_54618se_config_init()
11075 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ in bnx2x_54618se_config_init()
11090 fc_val = 0; in bnx2x_54618se_config_init()
11101 0x09, in bnx2x_54618se_config_init()
11105 0x04, in bnx2x_54618se_config_init()
11130 0x09, in bnx2x_54618se_config_init()
11133 0x09, in bnx2x_54618se_config_init()
11169 0x18, in bnx2x_54618se_config_init()
11170 (1<<15 | 1<<9 | 7<<0)); in bnx2x_54618se_config_init()
11176 0x18, in bnx2x_54618se_config_init()
11177 (1<<15 | 1<<9 | 7<<0)); in bnx2x_54618se_config_init()
11188 temp &= 0xfffe; in bnx2x_54618se_config_init()
11221 temp = 0; in bnx2x_54618se_config_init()
11230 0x04, in bnx2x_54618se_config_init()
11253 temp &= 0xff00; in bnx2x_5461x_set_link_led()
11259 temp |= 0x00ee; in bnx2x_5461x_set_link_led()
11262 temp |= 0x0001; in bnx2x_5461x_set_link_led()
11265 temp |= 0x00ff; in bnx2x_5461x_set_link_led()
11287 bnx2x_cl22_write(bp, phy, MDIO_PMA_REG_CTRL, 0x800); in bnx2x_54618se_link_reset()
11299 bnx2x_set_cfg_pin(bp, cfg_pin, 0); in bnx2x_54618se_link_reset()
11308 u8 link_up = 0; in bnx2x_54618se_read_status()
11315 DP(NETIF_MSG_LINK, "54618SE read_status: 0x%x\n", legacy_status); in bnx2x_54618se_read_status()
11347 vars->line_speed = 0; in bnx2x_54618se_read_status()
11356 0x01, in bnx2x_54618se_read_status()
11362 0x06, in bnx2x_54618se_read_status()
11364 if ((val & (1<<0)) == 0) in bnx2x_54618se_read_status()
11375 bnx2x_cl22_read(bp, phy, 0x5, &val); in bnx2x_54618se_read_status()
11393 bnx2x_cl22_read(bp, phy, 0xa, &val); in bnx2x_54618se_read_status()
11420 bnx2x_cl22_write(bp, phy, 0x09, 3<<11); in bnx2x_54618se_config_loopback()
11423 /* set val [mii read 0] */ in bnx2x_54618se_config_loopback()
11426 /* mii write 0 $val */ in bnx2x_54618se_config_loopback()
11427 bnx2x_cl22_read(bp, phy, 0x00, &val); in bnx2x_54618se_config_loopback()
11430 bnx2x_cl22_write(bp, phy, 0x00, val); in bnx2x_54618se_config_loopback()
11433 /* mii write 0x18 7 */ in bnx2x_54618se_config_loopback()
11434 /* set val [mii read 0x18] */ in bnx2x_54618se_config_loopback()
11435 /* mii write 0x18 [expr $val | [bits set 10 15]] */ in bnx2x_54618se_config_loopback()
11436 bnx2x_cl22_write(bp, phy, 0x18, 7); in bnx2x_54618se_config_loopback()
11437 bnx2x_cl22_read(bp, phy, 0x18, &val); in bnx2x_54618se_config_loopback()
11438 bnx2x_cl22_write(bp, phy, 0x18, val | (1<<10) | (1<<15)); in bnx2x_54618se_config_loopback()
11446 REG_WR(bp, umac_base + UMAC_REG_MAXFR, 0x2710); in bnx2x_54618se_config_loopback()
11458 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); in bnx2x_7101_config_loopback()
11477 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); in bnx2x_7101_config_init()
11486 val |= 0x200; in bnx2x_7101_config_init()
11511 DP(NETIF_MSG_LINK, "10G-base-T LASI status 0x%x->0x%x\n", in bnx2x_7101_read_status()
11517 DP(NETIF_MSG_LINK, "10G-base-T PMA status 0x%x->0x%x\n", in bnx2x_7101_read_status()
11527 DP(NETIF_MSG_LINK, "SFX7101 AN status 0x%x->Master=%x\n", in bnx2x_7101_read_status()
11544 str[0] = (spirom_ver & 0xFF); in bnx2x_7101_format_ver()
11545 str[1] = (spirom_ver & 0xFF00) >> 8; in bnx2x_7101_format_ver()
11546 str[2] = (spirom_ver & 0xFF0000) >> 16; in bnx2x_7101_format_ver()
11547 str[3] = (spirom_ver & 0xFF000000) >> 24; in bnx2x_7101_format_ver()
11548 str[4] = '\0'; in bnx2x_7101_format_ver()
11550 return 0; in bnx2x_7101_format_ver()
11561 for (cnt = 0; cnt < 10; cnt++) { in bnx2x_sfx7101_sp_sw_reset()
11573 if ((val & (1<<15)) == 0) in bnx2x_sfx7101_sp_sw_reset()
11591 u16 val = 0; in bnx2x_7101_set_link_led()
11602 val = 0; in bnx2x_7101_set_link_led()
11617 .addr = 0,
11618 .def_md_devad = 0,
11620 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11621 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11622 .mdio_ctrl = 0,
11623 .supported = 0,
11625 .ver_addr = 0,
11626 .req_flow_ctrl = 0,
11627 .req_line_speed = 0,
11628 .speed_cap_mask = 0,
11629 .req_duplex = 0,
11630 .rsrv = 0,
11643 .addr = 0xff,
11644 .def_md_devad = 0,
11645 .flags = 0,
11646 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11647 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11648 .mdio_ctrl = 0,
11660 .ver_addr = 0,
11661 .req_flow_ctrl = 0,
11662 .req_line_speed = 0,
11663 .speed_cap_mask = 0,
11664 .req_duplex = 0,
11665 .rsrv = 0,
11678 .addr = 0xff,
11679 .def_md_devad = 0,
11680 .flags = 0,
11681 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11682 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11683 .mdio_ctrl = 0,
11696 .ver_addr = 0,
11697 .req_flow_ctrl = 0,
11698 .req_line_speed = 0,
11699 .speed_cap_mask = 0,
11700 .req_duplex = 0,
11701 .rsrv = 0,
11713 .addr = 0xff,
11714 .def_md_devad = 0,
11716 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11717 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11718 .mdio_ctrl = 0,
11734 .ver_addr = 0,
11735 .req_flow_ctrl = 0,
11736 .req_line_speed = 0,
11737 .speed_cap_mask = 0,
11738 /* req_duplex = */0,
11739 /* rsrv = */0,
11753 .addr = 0xff,
11754 .def_md_devad = 0,
11756 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11757 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11758 .mdio_ctrl = 0,
11765 .ver_addr = 0,
11766 .req_flow_ctrl = 0,
11767 .req_line_speed = 0,
11768 .speed_cap_mask = 0,
11769 .req_duplex = 0,
11770 .rsrv = 0,
11782 .addr = 0xff,
11783 .def_md_devad = 0,
11784 .flags = 0,
11785 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11786 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11787 .mdio_ctrl = 0,
11796 .ver_addr = 0,
11797 .req_flow_ctrl = 0,
11798 .req_line_speed = 0,
11799 .speed_cap_mask = 0,
11800 .req_duplex = 0,
11801 .rsrv = 0,
11813 .addr = 0xff,
11814 .def_md_devad = 0,
11816 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11817 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11818 .mdio_ctrl = 0,
11824 .ver_addr = 0,
11825 .req_flow_ctrl = 0,
11826 .req_line_speed = 0,
11827 .speed_cap_mask = 0,
11828 .req_duplex = 0,
11829 .rsrv = 0,
11841 .addr = 0xff,
11842 .def_md_devad = 0,
11844 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11845 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11846 .mdio_ctrl = 0,
11853 .ver_addr = 0,
11854 .req_flow_ctrl = 0,
11855 .req_line_speed = 0,
11856 .speed_cap_mask = 0,
11857 .req_duplex = 0,
11858 .rsrv = 0,
11871 .addr = 0xff,
11872 .def_md_devad = 0,
11875 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11876 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11877 .mdio_ctrl = 0,
11885 .ver_addr = 0,
11886 .req_flow_ctrl = 0,
11887 .req_line_speed = 0,
11888 .speed_cap_mask = 0,
11889 .req_duplex = 0,
11890 .rsrv = 0,
11903 .addr = 0xff,
11904 .def_md_devad = 0,
11907 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11908 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11909 .mdio_ctrl = 0,
11916 .ver_addr = 0,
11917 .req_flow_ctrl = 0,
11918 .req_line_speed = 0,
11919 .speed_cap_mask = 0,
11920 .req_duplex = 0,
11921 .rsrv = 0,
11933 .addr = 0xff,
11934 .def_md_devad = 0,
11937 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11938 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11939 .mdio_ctrl = 0,
11951 .ver_addr = 0,
11952 .req_flow_ctrl = 0,
11953 .req_line_speed = 0,
11954 .speed_cap_mask = 0,
11955 .req_duplex = 0,
11956 .rsrv = 0,
11969 .addr = 0xff,
11970 .def_md_devad = 0,
11974 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11975 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
11976 .mdio_ctrl = 0,
11988 .ver_addr = 0,
11989 .req_flow_ctrl = 0,
11990 .req_line_speed = 0,
11991 .speed_cap_mask = 0,
11992 .req_duplex = 0,
11993 .rsrv = 0,
12006 .addr = 0xff,
12007 .def_md_devad = 0,
12011 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12012 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12013 .mdio_ctrl = 0,
12023 .ver_addr = 0,
12024 .req_flow_ctrl = 0,
12025 .req_line_speed = 0,
12026 .speed_cap_mask = 0,
12027 .req_duplex = 0,
12028 .rsrv = 0,
12041 .addr = 0xff,
12042 .def_md_devad = 0,
12045 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12046 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12047 .mdio_ctrl = 0,
12057 .ver_addr = 0,
12058 .req_flow_ctrl = 0,
12059 .req_line_speed = 0,
12060 .speed_cap_mask = 0,
12061 .req_duplex = 0,
12062 .rsrv = 0,
12075 .addr = 0xff,
12076 .def_md_devad = 0,
12079 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12080 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12081 .mdio_ctrl = 0,
12091 .ver_addr = 0,
12092 .req_flow_ctrl = 0,
12093 .req_line_speed = 0,
12094 .speed_cap_mask = 0,
12095 .req_duplex = 0,
12096 .rsrv = 0,
12109 .addr = 0xff,
12110 .def_md_devad = 0,
12112 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12113 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12114 .mdio_ctrl = 0,
12125 .ver_addr = 0,
12126 .req_flow_ctrl = 0,
12127 .req_line_speed = 0,
12128 .speed_cap_mask = 0,
12129 /* req_duplex = */0,
12130 /* rsrv = */0,
12151 u32 rx = 0, tx = 0, i; in bnx2x_populate_preemphasis()
12152 for (i = 0; i < 2; i++) { in bnx2x_populate_preemphasis()
12175 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); in bnx2x_populate_preemphasis()
12176 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); in bnx2x_populate_preemphasis()
12178 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); in bnx2x_populate_preemphasis()
12179 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); in bnx2x_populate_preemphasis()
12186 u32 ext_phy_config = 0; in bnx2x_get_ext_phy_config()
12215 ((REG_RD(bp, MISC_REG_CHIP_REV) & 0xf) << 12); in bnx2x_populate_int_phy()
12217 DP(NETIF_MSG_LINK, ":chip_id = 0x%x\n", chip_id); in bnx2x_populate_int_phy()
12223 if (REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) in bnx2x_populate_int_phy()
12294 DP(NETIF_MSG_LINK, "Unknown WC interface type 0x%x\n", in bnx2x_populate_int_phy()
12312 port * 0x10); in bnx2x_populate_int_phy()
12318 port * 0x18); in bnx2x_populate_int_phy()
12335 DP(NETIF_MSG_LINK, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", in bnx2x_populate_int_phy()
12339 return 0; in bnx2x_populate_int_phy()
12414 return 0; in bnx2x_populate_ext_phy()
12457 if (((raw_ver & 0x7F) <= 39) && in bnx2x_populate_ext_phy()
12458 (((raw_ver & 0xF80) >> 7) <= 1)) in bnx2x_populate_ext_phy()
12463 DP(NETIF_MSG_LINK, "phy_type 0x%x port %d found in index %d\n", in bnx2x_populate_ext_phy()
12465 DP(NETIF_MSG_LINK, " addr=0x%x, mdio_ctl=0x%x\n", in bnx2x_populate_ext_phy()
12467 return 0; in bnx2x_populate_ext_phy()
12506 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", in bnx2x_phy_def_cfg()
12594 params->num_phys = 0; in bnx2x_phy_probe()
12614 phy) != 0) { in bnx2x_phy_probe()
12615 params->num_phys = 0; in bnx2x_phy_probe()
12646 actual_phy_idx))) == 0) { in bnx2x_phy_probe()
12659 return 0; in bnx2x_phy_probe()
12679 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); in bnx2x_init_bmac_loopback()
12698 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port * 4, 0); in bnx2x_init_emac_loopback()
12706 if (!params->req_line_speed[0]) in bnx2x_init_xmac_loopback()
12709 vars->line_speed = params->req_line_speed[0]; in bnx2x_init_xmac_loopback()
12717 bnx2x_set_aer_mmd(params, ¶ms->phy[0]); in bnx2x_init_xmac_loopback()
12718 bnx2x_warpcore_reset_lane(bp, ¶ms->phy[0], 0); in bnx2x_init_xmac_loopback()
12724 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xmac_loopback()
12739 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_umac_loopback()
12750 if (params->req_line_speed[0] == SPEED_1000) in bnx2x_init_xgxs_loopback()
12752 else if ((params->req_line_speed[0] == SPEED_20000) || in bnx2x_init_xgxs_loopback()
12762 if (params->req_line_speed[0] == SPEED_1000) { in bnx2x_init_xgxs_loopback()
12764 bnx2x_umac_enable(params, vars, 0); in bnx2x_init_xgxs_loopback()
12767 bnx2x_emac_enable(params, vars, 0); in bnx2x_init_xgxs_loopback()
12771 bnx2x_xmac_enable(params, vars, 0); in bnx2x_init_xgxs_loopback()
12773 bnx2x_bmac_enable(params, vars, 0, 1); in bnx2x_init_xgxs_loopback()
12789 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_init_xgxs_loopback()
12797 u8 val = en * 0x1F; in bnx2x_set_rx_filter()
12801 val |= en * 0x20; in bnx2x_set_rx_filter()
12806 en*0x3); in bnx2x_set_rx_filter()
12858 bnx2x_umac_enable(params, vars, 0); in bnx2x_avoid_link_flap()
12860 bnx2x_xmac_enable(params, vars, 0); in bnx2x_avoid_link_flap()
12863 bnx2x_emac_enable(params, vars, 0); in bnx2x_avoid_link_flap()
12865 bnx2x_bmac_enable(params, vars, 0, !dont_clear_stat); in bnx2x_avoid_link_flap()
12871 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) in bnx2x_avoid_link_flap()
12880 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_avoid_link_flap()
12884 return 0; in bnx2x_avoid_link_flap()
12901 params->req_duplex[0] | (params->req_duplex[1] << 16)); in bnx2x_cannot_avoid_link_flap()
12905 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); in bnx2x_cannot_avoid_link_flap()
12909 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); in bnx2x_cannot_avoid_link_flap()
12911 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { in bnx2x_cannot_avoid_link_flap()
12940 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) in bnx2x_cannot_avoid_link_flap()
12953 params->req_line_speed[0], params->req_flow_ctrl[0]); in bnx2x_phy_init()
12956 DP(NETIF_MSG_LINK, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); in bnx2x_phy_init()
12957 vars->link_status = 0; in bnx2x_phy_init()
12958 vars->phy_link_up = 0; in bnx2x_phy_init()
12959 vars->link_up = 0; in bnx2x_phy_init()
12960 vars->line_speed = 0; in bnx2x_phy_init()
12964 vars->phy_flags = 0; in bnx2x_phy_init()
12965 vars->check_kr2_recovery_cnt = 0; in bnx2x_phy_init()
12973 if (lfa_status == 0) { in bnx2x_phy_init()
12978 DP(NETIF_MSG_LINK, "Cannot avoid link flap lfa_sta=0x%x\n", in bnx2x_phy_init()
12994 if (params->num_phys == 0) { in bnx2x_phy_init()
13033 return 0; in bnx2x_phy_init()
13040 u8 phy_index, port = params->port, clear_latch_ind = 0; in bnx2x_link_reset()
13043 vars->link_status = 0; in bnx2x_link_reset()
13060 REG_WR(bp, NIG_REG_BMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
13061 REG_WR(bp, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); in bnx2x_link_reset()
13065 bnx2x_set_bmac_rx(bp, params->chip_id, port, 0); in bnx2x_link_reset()
13067 bnx2x_set_xmac_rxtx(params, 0); in bnx2x_link_reset()
13068 bnx2x_set_umac_rxtx(params, 0); in bnx2x_link_reset()
13072 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); in bnx2x_link_reset()
13080 bnx2x_set_led(params, vars, LED_MODE_OFF, 0); in bnx2x_link_reset()
13100 bnx2x_rearm_latch_signal(bp, port, 0); in bnx2x_link_reset()
13113 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
13114 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); in bnx2x_link_reset()
13117 bnx2x_set_xumac_nig(params, 0, 0); in bnx2x_link_reset()
13123 vars->link_up = 0; in bnx2x_link_reset()
13124 vars->phy_flags = 0; in bnx2x_link_reset()
13125 return 0; in bnx2x_link_reset()
13131 vars->link_up = 0; in bnx2x_lfa_reset()
13132 vars->phy_flags = 0; in bnx2x_lfa_reset()
13147 bnx2x_set_bmac_rx(bp, params->chip_id, params->port, 0); in bnx2x_lfa_reset()
13150 bnx2x_set_xmac_rxtx(params, 0); in bnx2x_lfa_reset()
13151 bnx2x_set_umac_rxtx(params, 0); in bnx2x_lfa_reset()
13159 bnx2x_set_rx_filter(params, 0); in bnx2x_lfa_reset()
13175 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_lfa_reset()
13176 return 0; in bnx2x_lfa_reset()
13190 s8 port = 0; in bnx2x_8073_common_init_phy()
13191 s8 port_of_path = 0; in bnx2x_8073_common_init_phy()
13202 shmem_base = shmem_base_path[0]; in bnx2x_8073_common_init_phy()
13203 shmem2_base = shmem2_base_path[0]; in bnx2x_8073_common_init_phy()
13208 port_of_path = 0; in bnx2x_8073_common_init_phy()
13214 0) { in bnx2x_8073_common_init_phy()
13243 if (phy[PORT_0].addr & 0x1) { in bnx2x_8073_common_init_phy()
13256 port_of_path = 0; in bnx2x_8073_common_init_phy()
13258 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", in bnx2x_8073_common_init_phy()
13306 return 0; in bnx2x_8073_common_init_phy()
13323 bnx2x_ext_phy_hw_reset(bp, 0); in bnx2x_8726_common_init_phy()
13325 for (port = 0; port < PORT_MAX; port++) { in bnx2x_8726_common_init_phy()
13330 shmem_base = shmem_base_path[0]; in bnx2x_8726_common_init_phy()
13331 shmem2_base = shmem2_base_path[0]; in bnx2x_8726_common_init_phy()
13339 0) { in bnx2x_8726_common_init_phy()
13346 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); in bnx2x_8726_common_init_phy()
13355 return 0; in bnx2x_8726_common_init_phy()
13366 *io_gpio = 0; in bnx2x_get_ext_phy_reset_gpio()
13367 *io_port = 0; in bnx2x_get_ext_phy_reset_gpio()
13371 *io_port = 0; in bnx2x_get_ext_phy_reset_gpio()
13375 *io_port = 0; in bnx2x_get_ext_phy_reset_gpio()
13379 *io_port = 0; in bnx2x_get_ext_phy_reset_gpio()
13382 *io_gpio = 0; in bnx2x_get_ext_phy_reset_gpio()
13422 bnx2x_get_ext_phy_reset_gpio(bp, shmem_base_path[0], in bnx2x_8727_common_init_phy()
13443 shmem_base = shmem_base_path[0]; in bnx2x_8727_common_init_phy()
13444 shmem2_base = shmem2_base_path[0]; in bnx2x_8727_common_init_phy()
13449 port_of_path = 0; in bnx2x_8727_common_init_phy()
13455 0) { in bnx2x_8727_common_init_phy()
13475 if (phy[PORT_0].addr & 0x1) { in bnx2x_8727_common_init_phy()
13487 port_of_path = 0; in bnx2x_8727_common_init_phy()
13488 DP(NETIF_MSG_LINK, "Loading spirom for phy address 0x%x\n", in bnx2x_8727_common_init_phy()
13499 return 0; in bnx2x_8727_common_init_phy()
13513 DP(NETIF_MSG_LINK, "84833 reset pulse on pin values 0x%x\n", in bnx2x_84833_common_init_phy()
13515 return 0; in bnx2x_84833_common_init_phy()
13522 int rc = 0; in bnx2x_ext_phy_common_init()
13561 "ext_phy 0x%x common init not required\n", in bnx2x_ext_phy_common_init()
13569 0); in bnx2x_ext_phy_common_init()
13576 int rc = 0; in bnx2x_common_init_phy()
13578 u8 phy_index = 0; in bnx2x_common_init_phy()
13590 phy_ver = REG_RD(bp, shmem_base_path[0] + in bnx2x_common_init_phy()
13594 DP(NETIF_MSG_LINK, "Not doing common init; phy ver is 0x%x\n", in bnx2x_common_init_phy()
13596 return 0; in bnx2x_common_init_phy()
13599 /* Read the ext_phy_type for arbitrary port(0) */ in bnx2x_common_init_phy()
13603 shmem_base_path[0], in bnx2x_common_init_phy()
13604 phy_index, 0); in bnx2x_common_init_phy()
13629 if (bnx2x_get_cfg_pin(bp, cfg_pin, &pin_val) != 0) in bnx2x_check_over_curr()
13633 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { in bnx2x_check_over_curr()
13643 bnx2x_warpcore_power_module(params, 0); in bnx2x_check_over_curr()
13649 /* Returns 0 if no change occurred since last check; 1 otherwise. */
13657 u32 old_status = (vars->phy_flags & phy_flag) ? 1 : 0; in bnx2x_analyze_link_error()
13659 if ((status ^ old_status) == 0) in bnx2x_analyze_link_error()
13660 return 0; in bnx2x_analyze_link_error()
13677 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) in bnx2x_analyze_link_error()
13686 vars->link_up = 0; in bnx2x_analyze_link_error()
13703 REG_WR(bp, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); in bnx2x_analyze_link_error()
13734 u32 lss_status = 0; in bnx2x_check_half_open_conn()
13737 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || in bnx2x_check_half_open_conn()
13739 return 0; in bnx2x_check_half_open_conn()
13752 REG_WR(bp, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); in bnx2x_check_half_open_conn()
13776 lss_status = (wb_data[0] > 0); in bnx2x_check_half_open_conn()
13782 return 0; in bnx2x_check_half_open_conn()
13789 u32 cfg_pin, value = 0; in bnx2x_sfp_tx_fault_detection()
13799 DP(NETIF_MSG_LINK, "Failed to read pin 0x%02x\n", cfg_pin); in bnx2x_sfp_tx_fault_detection()
13850 if (vars->check_kr2_recovery_cnt > 0) { in bnx2x_check_kr2_wa()
13874 if (base_page == 0) { in bnx2x_check_kr2_wa()
13886 not_kr2_device = (((base_page & 0x8000) == 0) || in bnx2x_check_kr2_wa()
13887 (((base_page & 0x8000) && in bnx2x_check_kr2_wa()
13888 ((next_page & 0xe0) == 0x20)))); in bnx2x_check_kr2_wa()
13893 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, in bnx2x_check_kr2_wa()
13902 DP(NETIF_MSG_LINK, "BP=0x%x, NP=0x%x\n", base_page, next_page); in bnx2x_check_kr2_wa()
13918 0) in bnx2x_period_func()
13960 u8 phy_index, fan_failure_det_req = 0; in bnx2x_fan_failure_det_req()
13966 != 0) { in bnx2x_fan_failure_det_req()
13968 return 0; in bnx2x_fan_failure_det_req()
13980 bnx2x_update_mng(params, 0); in bnx2x_hw_reset_phy()
14002 u8 gpio_num = 0xff, gpio_port = 0xff, phy_index; in bnx2x_init_mod_abs_int()
14010 &gpio_port) != 0) in bnx2x_init_mod_abs_int()
14018 != 0) { in bnx2x_init_mod_abs_int()
14030 if (gpio_num == 0xff) in bnx2x_init_mod_abs_int()
14048 DP(NETIF_MSG_LINK, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", in bnx2x_init_mod_abs_int()
14051 if (port == 0) in bnx2x_init_mod_abs_int()