Lines Matching +full:0 +full:x61c
19 #define DESC_ADDR_HI_STATUS_LEN 0x00
20 #define DESC_ADDR_HI_SHIFT 0
21 #define DESC_ADDR_HI_MASK 0xff
23 #define DESC_STATUS_MASK 0x3ff
25 #define DESC_LEN_MASK 0x7fff
26 #define DESC_ADDR_LO 0x04
45 #define PCP_DEI_MASK 0xf
47 #define VID_MASK 0xfff
49 #define L4_CSUM_PTR_MASK 0x1ff
51 #define L4_PTR_MASK 0x1ff
55 #define DEST_MAP_MASK 0x1ff
72 #define RX_STATUS_UCAST 0
73 #define RX_STATUS_BCAST 0x04
74 #define RX_STATUS_MCAST 0x08
75 #define RX_STATUS_L2_MCAST 0x0c
81 #define TX_STATUS_VLAN_NO_ACT 0x00
82 #define TX_STATUS_VLAN_PCP_TSB 0x01
83 #define TX_STATUS_VLAN_QUEUE 0x02
84 #define TX_STATUS_VLAN_VID_TSB 0x03
87 #define TX_STATUS_BRCM_TAG_NO_ACT 0
88 #define TX_STATUS_BRCM_TAG_ZERO 0x10
89 #define TX_STATUS_BRCM_TAG_ONE_QUEUE 0x20
90 #define TX_STATUS_BRCM_TAG_ONE_TSB 0x30
94 #define SYS_PORT_TOPCTRL_OFFSET 0
95 #define REV_CNTL 0x00
96 #define REV_MASK 0xffff
98 #define RX_FLUSH_CNTL 0x04
99 #define RX_FLUSH (1 << 0)
101 #define TX_FLUSH_CNTL 0x08
102 #define TX_FLUSH (1 << 0)
104 #define MISC_CNTL 0x0c
105 #define SYS_CLK_SEL (1 << 0)
109 #define SYS_PORT_INTRL2_0_OFFSET 0x200
110 #define SYS_PORT_INTRL2_1_OFFSET 0x240
111 #define INTRL2_CPU_STATUS 0x00
112 #define INTRL2_CPU_SET 0x04
113 #define INTRL2_CPU_CLEAR 0x08
114 #define INTRL2_CPU_MASK_STATUS 0x0c
115 #define INTRL2_CPU_MASK_SET 0x10
116 #define INTRL2_CPU_MASK_CLEAR 0x14
118 /* Level-2 instance 0 interrupt bits */
119 #define INTRL2_0_GISB_ERR (1 << 0)
132 /* SYSTEMPORT Lite groups the TX queues interrupts on instance 0 */
134 #define INTRL2_0_TDMA_MBDONE_MASK (0xffff << INTRL2_0_TDMA_MBDONE_SHIFT)
137 #define SYS_PORT_RXCHK_OFFSET 0x300
139 #define RXCHK_CONTROL 0x00
140 #define RXCHK_EN (1 << 0)
145 #define RXCHK_BRCM_TAG_MATCH_MASK 0xff
158 #define RXCHK_BRCM_TAG0 0x04
159 #define RXCHK_BRCM_TAG(i) ((i) * 0x4 + RXCHK_BRCM_TAG0)
160 #define RXCHK_BRCM_TAG0_MASK 0x24
161 #define RXCHK_BRCM_TAG_MASK(i) ((i) * 0x4 + RXCHK_BRCM_TAG0_MASK)
162 #define RXCHK_BRCM_TAG_MATCH_STATUS 0x44
163 #define RXCHK_ETHERTYPE 0x48
164 #define RXCHK_BAD_CSUM_CNTR 0x4C
165 #define RXCHK_OTHER_DISC_CNTR 0x50
169 #define RXCHK_BRCM_TAG_CID_MASK 0xff
172 #define SYS_PORT_TXCHK_OFFSET 0x380
173 #define TXCHK_PKT_RDY_THRESH 0x00
176 #define SYS_PORT_RBUF_OFFSET 0x400
178 #define RBUF_CONTROL 0x00
179 #define RBUF_RSB_EN (1 << 0)
184 #define RBUF_RESUME_THRESH_MASK 0xff
186 #define RBUF_OK_TO_SEND_MASK 0xff
195 #define RBUF_PKT_RDY_THRESH 0x04
197 #define RBUF_STATUS 0x08
198 #define RBUF_WOL_MODE (1 << 0)
202 #define RBUF_OVFL_DISC_CNTR 0x0c
203 #define RBUF_ERR_PKT_CNTR 0x10
206 #define SYS_PORT_TBUF_OFFSET 0x600
208 #define TBUF_CONTROL 0x00
209 #define TBUF_BP_EN (1 << 0)
211 #define TBUF_MAX_PKT_THRESH_MASK 0x1f
213 #define TBUF_FULL_THRESH_MASK 0x1f
216 #define SYS_PORT_UMAC_OFFSET 0x800
218 #define UMAC_MIB_START 0x400
220 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
223 #define UMAC_MIB_STAT_OFFSET 0xc
225 #define UMAC_MIB_CTRL 0x580
226 #define MIB_RX_CNT_RST (1 << 0)
231 #define UMAC_MPD_CTRL 0x620
232 #define MPD_EN (1 << 0)
234 #define MSEQ_LEN_MASK 0xff
237 #define UMAC_PSW_MS 0x624
238 #define UMAC_PSW_LS 0x628
239 #define UMAC_MDF_CTRL 0x650
240 #define UMAC_MDF_ADDR 0x654
243 #define SYS_PORT_GIB_OFFSET 0x1000
245 #define GIB_CONTROL 0x00
246 #define GIB_TX_EN (1 << 0)
251 #define GIB_GTX_CLK_EXT_CLK (0 << GIB_GTX_CLK_SEL_SHIFT)
262 #define GIB_PREAMBLE_LEN_MASK 0xf
264 #define GIB_IPG_LEN_MASK 0x3f
266 #define GIB_PAD_EXTENSION_MASK 0x3f
268 #define GIB_MAC1 0x08
269 #define GIB_MAC0 0x0c
272 #define SYS_PORT_RDMA_OFFSET 0x2000
274 #define RDMA_CONTROL 0x1000
275 #define RDMA_EN (1 << 0)
279 #define RDMA_BUF_DATA_OFFSET_MASK 0x3ff
281 #define RDMA_STATUS 0x1004
282 #define RDMA_DISABLED (1 << 0)
286 #define RDMA_SCB_BURST_SIZE 0x1008
288 #define RDMA_RING_BUF_SIZE 0x100c
291 #define RDMA_WRITE_PTR_HI 0x1010
292 #define RDMA_WRITE_PTR_LO 0x1014
293 #define RDMA_OVFL_DISC_CNTR 0x1018
294 #define RDMA_PROD_INDEX 0x1018
295 #define RDMA_PROD_INDEX_MASK 0xffff
297 #define RDMA_CONS_INDEX 0x101c
298 #define RDMA_CONS_INDEX_MASK 0xffff
300 #define RDMA_START_ADDR_HI 0x1020
301 #define RDMA_START_ADDR_LO 0x1024
302 #define RDMA_END_ADDR_HI 0x1028
303 #define RDMA_END_ADDR_LO 0x102c
305 #define RDMA_MBDONE_INTR 0x1030
306 #define RDMA_INTR_THRESH_MASK 0x1ff
308 #define RDMA_TIMEOUT_MASK 0xffff
310 #define RDMA_XON_XOFF_THRESH 0x1034
311 #define RDMA_XON_XOFF_THRESH_MASK 0xffff
314 #define RDMA_READ_PTR_HI 0x1038
315 #define RDMA_READ_PTR_LO 0x103c
317 #define RDMA_OVERRIDE 0x1040
318 #define RDMA_LE_MODE (1 << 0)
321 #define RDMA_TEST 0x1044
322 #define RDMA_TP_OUT_SEL (1 << 0)
325 #define RDMA_DEBUG 0x1048
331 #define SYS_PORT_TDMA_OFFSET 0x4000
332 #define TDMA_WRITE_PORT_OFFSET 0x0000
354 #define RING_HEAD_TAIL_PTR 0x00
355 #define RING_HEAD_MASK 0x7ff
357 #define RING_TAIL_MASK 0x7ff
361 #define RING_COUNT 0x04
362 #define RING_COUNT_MASK 0x7ff
364 #define RING_BUFF_DONE_MASK 0x7ff
366 #define RING_MAX_HYST 0x08
367 #define RING_MAX_THRESH_MASK 0x7ff
369 #define RING_HYST_THRESH_MASK 0x7ff
371 #define RING_INTR_CONTROL 0x0c
372 #define RING_INTR_THRESH_MASK 0x7ff
375 #define RING_TIMEOUT_MASK 0xffff
377 #define RING_PROD_CONS_INDEX 0x10
378 #define RING_PROD_INDEX_MASK 0xffff
380 #define RING_CONS_INDEX_MASK 0xffff
382 #define RING_MAPPING 0x14
383 #define RING_QID_MASK 0x7
385 #define RING_PORT_ID_MASK 0x7
389 #define RING_CREDIT_MASK 0xffff
391 #define RING_PCP_DEI_VID 0x18
392 #define RING_VID_MASK 0x7ff
395 #define RING_PCP_MASK 0x7
397 #define RING_PKT_SIZE_ADJ_MASK 0xf
422 #define TDMA_CONTROL 0x600
423 #define TDMA_EN 0
432 #define BUF_DATA_OFFSET_MASK 0x3ff
438 #define ACH_TXDONE_DELAY_MASK 0xff
440 #define TDMA_STATUS 0x604
441 #define TDMA_DISABLED (1 << 0)
444 #define TDMA_SCB_BURST_SIZE 0x608
445 #define TDMA_OVER_MAX_THRESH_STATUS 0x60c
446 #define TDMA_OVER_HYST_THRESH_STATUS 0x610
447 #define TDMA_TPID 0x614
449 #define TDMA_FREE_LIST_HEAD_TAIL_PTR 0x618
450 #define TDMA_FREE_HEAD_MASK 0x7ff
452 #define TDMA_FREE_TAIL_MASK 0x7ff
454 #define TDMA_FREE_LIST_COUNT 0x61c
455 #define TDMA_FREE_LIST_COUNT_MASK 0x7ff
457 #define TDMA_TIER2_ARB_CTRL 0x620
458 #define TDMA_ARB_MODE_RR 0
459 #define TDMA_ARB_MODE_WEIGHT_RR 0x1
460 #define TDMA_ARB_MODE_STRICT 0x2
461 #define TDMA_ARB_MODE_DEFICIT_RR 0x3
463 #define TDMA_CREDIT_MASK 0xffff
465 #define TDMA_TIER1_ARB_0_CTRL 0x624
466 #define TDMA_ARB_EN (1 << 0)
468 #define TDMA_TIER1_ARB_0_QUEUE_EN 0x628
469 #define TDMA_TIER1_ARB_1_CTRL 0x62c
470 #define TDMA_TIER1_ARB_1_QUEUE_EN 0x630
471 #define TDMA_TIER1_ARB_2_CTRL 0x634
472 #define TDMA_TIER1_ARB_2_QUEUE_EN 0x638
473 #define TDMA_TIER1_ARB_3_CTRL 0x63c
474 #define TDMA_TIER1_ARB_3_QUEUE_EN 0x640
476 #define TDMA_SCB_ENDIAN_OVERRIDE 0x644
477 #define TDMA_LE_MODE (1 << 0)
480 #define TDMA_TEST 0x648
481 #define TDMA_TP_OUT_SEL (1 << 0)
484 #define TDMA_DEBUG 0x64c
513 u32 pkt; /* RO (0x428) Received pkt count*/
531 u32 rcrc; /* RO (0x470),# of CRC match pkt */
537 u32 pkts; /* RO (0x4a8) Transmited pkt */
555 u32 uc; /* RO (0x4f0) # of xmited unicast pkt */
593 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
600 .stat_sizeof = sizeof(((struct bcm_sysport_stats64 *)0)->m), \
607 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
619 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
627 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
635 .stat_sizeof = sizeof(((struct bcm_sysport_priv *)0)->m), \
671 SYSTEMPORT = 0,