98 static void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value)  in enet_write()  function
111 	enet_write(enet, offset, val);  in enet_maskset()
126 	enet_write(enet, ENET_UNIMAC + offset, value);  in enet_umac_write()
150 	enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);  in bcm4908_enet_dma_ring_intrs_on()
156 	enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);  in bcm4908_enet_dma_ring_intrs_off()
162 	enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);  in bcm4908_enet_dma_ring_intrs_ack()
252 		enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0);  in bcm4908_enet_dma_reset()
259 		enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);  in bcm4908_enet_dma_reset()
260 		enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);  in bcm4908_enet_dma_reset()
261 		enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);  in bcm4908_enet_dma_reset()
262 		enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);  in bcm4908_enet_dma_reset()
305 	enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch));  in bcm4908_enet_dma_ring_init()
306 	enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0);  in bcm4908_enet_dma_ring_init()
308 	enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);  in bcm4908_enet_dma_ring_init()
309 	enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);  in bcm4908_enet_dma_ring_init()
310 	enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);  in bcm4908_enet_dma_ring_init()
312 	enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,  in bcm4908_enet_dma_ring_init()
361 	enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);  in bcm4908_enet_dma_tx_ring_enable()
367 	enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);  in bcm4908_enet_dma_tx_ring_disable()