atheros/atlx/atl1.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4  * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5  * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
8  * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
82 /* Wake-On-Lan control register */
215 /* RX/TX count-down timer to trigger CMB-write. 2us resolution. */
302 #define AUTONEG_ADVERTISE_SPEED_DEFAULT		0x002F	/* All but 1000-Half */
431  * The L1 transmit packet descriptor is comprised of four 32-bit words.
434  *	+---------------------------------------+
436  *      +---------------------------------------+
438  *      +---------------------------------------+
440  *      +---------------------------------------+
442  *      +---------------------------------------+
444  * Words 0 and 1 combine to form a 64-bit buffer address.
463  *	10-+ 					10-+
465  *	12 |	(num 32-bit words)		12 |	(num 32-bit words)
466  *	13-+					13-+
467  *	14-+					14	Unused
469  *	16 |	(num 32-bit words)		16-+
470  *	17-+					17 |
472  *	19-+					19 |	Payload offset
476  *	23 |					23-+
477  *	24 |					24-+
484  *	31-+					31-+
573 #define ATL1_GET_DESC(R, i, type)	(&(((type *)((R)->desc))[i]))
600 /* transmit packet descriptor (tpd) ring */
602 	void *desc;		/* descriptor ring virtual address */
603 	dma_addr_t dma;		/* descriptor ring physical address */
604 	u16 size;		/* descriptor ring length in bytes */
605 	u16 count;		/* number of descriptors in the ring */
612 /* receive free descriptor (rfd) ring */
614 	void *desc;		/* descriptor ring virtual address */
615 	dma_addr_t dma;		/* descriptor ring physical address */
616 	u16 size;		/* descriptor ring length in bytes */
617 	u16 count;		/* number of descriptors in the ring */
623 /* receive return descriptor (rrd) ring */
625 	void *desc;		/* descriptor ring virtual address */
626 	dma_addr_t dma;		/* descriptor ring physical address */
627 	unsigned int size;	/* descriptor ring length in bytes */
628 	u16 count;		/* number of descriptors in the ring */
690 				 * control in half-duplex mode. In units of
691 				 * 8-bit time */
692 	u8 ipgt;		/* Desired back to back inter-packet gap.
693 				 * The default is 96-bit time */
697 	u8 ipgr1;		/* 64bit Carrier-Sense window */
698 	u8 ipgr2;		/* 96-bit IPG window */
699 	u8 tpd_burst;		/* Number of TPD to prefetch in cache-aligned
701 	u8 rfd_burst;		/* Number of RFD to prefetch in cache-aligned
709 	u16 txf_burst;		/* Number of data bytes to read in a cache-
711 	u16 rx_jumbo_th;	/* Jumbo packet size for non-VLAN packet. VLAN
778 	 * Use this value to check is napi handler allowed to