Lines Matching refs:value
127 static int atl1_validate_option(int *value, struct atl1_option *opt, in atl1_validate_option() argument
130 if (*value == OPTION_UNSET) { in atl1_validate_option()
131 *value = opt->def; in atl1_validate_option()
137 switch (*value) { in atl1_validate_option()
147 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) { in atl1_validate_option()
149 *value); in atl1_validate_option()
159 if (*value == ent->i) { in atl1_validate_option()
174 opt->name, *value, opt->err); in atl1_validate_option()
175 *value = opt->def; in atl1_validate_option()
296 u32 value; in atl1_check_eeprom_exist() local
297 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); in atl1_check_eeprom_exist()
298 if (value & SPI_FLASH_CTRL_EN_VPD) { in atl1_check_eeprom_exist()
299 value &= ~SPI_FLASH_CTRL_EN_VPD; in atl1_check_eeprom_exist()
300 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); in atl1_check_eeprom_exist()
303 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST); in atl1_check_eeprom_exist()
304 return ((value & 0xFF00) == 0x6C00) ? 0 : 1; in atl1_check_eeprom_exist()
373 u32 value; in atl1_spi_read() local
378 value = SPI_FLASH_CTRL_WAIT_READY | in atl1_spi_read()
391 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); in atl1_spi_read()
393 value |= SPI_FLASH_CTRL_START; in atl1_spi_read()
394 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL); in atl1_spi_read()
399 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL); in atl1_spi_read()
400 if (!(value & SPI_FLASH_CTRL_START)) in atl1_spi_read()
404 if (value & SPI_FLASH_CTRL_START) in atl1_spi_read()
545 u32 crc32, value = 0; in atl1_hash_mc_addr() local
550 value |= (((crc32 >> i) & 1) << (31 - i)); in atl1_hash_mc_addr()
552 return value; in atl1_hash_mc_addr()
905 u32 value; in atl1_set_mac_addr() local
911 value = (((u32) hw->mac_addr[2]) << 24) | in atl1_set_mac_addr()
914 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); in atl1_set_mac_addr()
916 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); in atl1_set_mac_addr()
917 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2)); in atl1_set_mac_addr()
1243 u32 value; in atl1_setup_mac_ctrl() local
1247 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN; in atl1_setup_mac_ctrl()
1250 value |= MAC_CTRL_DUPLX; in atl1_setup_mac_ctrl()
1252 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ? in atl1_setup_mac_ctrl()
1256 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW); in atl1_setup_mac_ctrl()
1258 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD); in atl1_setup_mac_ctrl()
1260 value |= (((u32) adapter->hw.preamble_len in atl1_setup_mac_ctrl()
1263 __atlx_vlan_mode(netdev->features, &value); in atl1_setup_mac_ctrl()
1269 value |= MAC_CTRL_BC_EN; in atl1_setup_mac_ctrl()
1271 value |= MAC_CTRL_PROMIS_EN; in atl1_setup_mac_ctrl()
1273 value |= MAC_CTRL_MC_ALL_EN; in atl1_setup_mac_ctrl()
1275 iowrite32(value, hw->hw_addr + REG_MAC_CTRL); in atl1_setup_mac_ctrl()
1392 u32 hi, lo, value; in set_flow_ctrl_old() local
1395 value = adapter->rfd_ring.count; in set_flow_ctrl_old()
1396 hi = value / 16; in set_flow_ctrl_old()
1399 lo = value * 7 / 8; in set_flow_ctrl_old()
1401 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | in set_flow_ctrl_old()
1403 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH); in set_flow_ctrl_old()
1406 value = adapter->rrd_ring.count; in set_flow_ctrl_old()
1407 lo = value / 16; in set_flow_ctrl_old()
1408 hi = value * 7 / 8; in set_flow_ctrl_old()
1411 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | in set_flow_ctrl_old()
1413 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH); in set_flow_ctrl_old()
1418 u32 hi, lo, value; in set_flow_ctrl_new() local
1421 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN); in set_flow_ctrl_new()
1422 lo = value / 16; in set_flow_ctrl_new()
1425 hi = value * 7 / 8; in set_flow_ctrl_new()
1428 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) | in set_flow_ctrl_new()
1430 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH); in set_flow_ctrl_new()
1433 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN); in set_flow_ctrl_new()
1434 lo = value / 8; in set_flow_ctrl_new()
1435 hi = value * 7 / 8; in set_flow_ctrl_new()
1440 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) | in set_flow_ctrl_new()
1442 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH); in set_flow_ctrl_new()
1454 u32 value; in atl1_configure() local
1460 value = (((u32) hw->mac_addr[2]) << 24) | in atl1_configure()
1464 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR); in atl1_configure()
1465 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1])); in atl1_configure()
1466 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4)); in atl1_configure()
1486 value = adapter->rrd_ring.count; in atl1_configure()
1487 value <<= 16; in atl1_configure()
1488 value += adapter->rfd_ring.count; in atl1_configure()
1489 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE); in atl1_configure()
1497 value = ((atomic_read(&adapter->tpd_ring.next_to_use) in atl1_configure()
1503 iowrite32(value, hw->hw_addr + REG_MAILBOX); in atl1_configure()
1506 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK) in atl1_configure()
1514 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG); in atl1_configure()
1517 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) | in atl1_configure()
1524 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL); in atl1_configure()
1537 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK) in atl1_configure()
1543 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM); in atl1_configure()
1559 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK) in atl1_configure()
1566 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL); in atl1_configure()
1569 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK) in atl1_configure()
1573 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG); in atl1_configure()
1576 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK) in atl1_configure()
1583 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL); in atl1_configure()
1586 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK) in atl1_configure()
1591 value |= (u32) hw->dma_ord; in atl1_configure()
1593 value |= DMA_CTRL_RCB_VALUE; in atl1_configure()
1594 iowrite32(value, hw->hw_addr + REG_DMA_CTRL); in atl1_configure()
1597 value = (hw->cmb_tpd > adapter->tpd_ring.count) ? in atl1_configure()
1599 value <<= 16; in atl1_configure()
1600 value |= hw->cmb_rrd; in atl1_configure()
1601 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH); in atl1_configure()
1602 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16); in atl1_configure()
1603 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER); in atl1_configure()
1607 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN; in atl1_configure()
1608 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL); in atl1_configure()
1610 value = ioread32(adapter->hw.hw_addr + REG_ISR); in atl1_configure()
1611 if (unlikely((value & ISR_PHY_LINKDOWN) != 0)) in atl1_configure()
1612 value = 1; /* config failed */ in atl1_configure()
1614 value = 0; in atl1_configure()
1619 return value; in atl1_configure()
1627 u32 value; in atl1_pcie_patch() local
1630 value = 0x6500; in atl1_pcie_patch()
1631 iowrite32(value, adapter->hw.hw_addr + 0x12FC); in atl1_pcie_patch()
1633 value = ioread32(adapter->hw.hw_addr + 0x1008); in atl1_pcie_patch()
1634 value |= 0x8000; in atl1_pcie_patch()
1635 iowrite32(value, adapter->hw.hw_addr + 0x1008); in atl1_pcie_patch()
1646 unsigned long value; in atl1_via_workaround() local
1648 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND); in atl1_via_workaround()
1649 if (value & PCI_COMMAND_INTX_DISABLE) in atl1_via_workaround()
1650 value &= ~PCI_COMMAND_INTX_DISABLE; in atl1_via_workaround()
1651 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND); in atl1_via_workaround()
1739 u32 value; in atl1_update_mailbox() local
1747 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << in atl1_update_mailbox()
1753 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); in atl1_update_mailbox()
1904 u32 value; in atl1_intr_rx() local
2038 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) << in atl1_intr_rx()
2044 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX); in atl1_intr_rx()
3385 static void atl1_set_msglevel(struct net_device *netdev, u32 value) in atl1_set_msglevel() argument
3388 adapter->msg_enable = value; in atl1_set_msglevel()