Lines Matching refs:alx_write_mem32

321 		alx_write_mem32(hw, ALX_IMR, alx->int_mask);  in alx_poll()
350 alx_write_mem32(hw, ALX_IMR, alx->int_mask); in alx_intr_handle_misc()
364 alx_write_mem32(hw, ALX_ISR, intr | ALX_ISR_DIS); in alx_intr_handle()
374 alx_write_mem32(hw, ALX_IMR, alx->int_mask); in alx_intr_handle()
377 alx_write_mem32(hw, ALX_ISR, 0); in alx_intr_handle()
392 alx_write_mem32(hw, ALX_ISR, np->vec_mask); in alx_intr_msix_ring()
416 alx_write_mem32(hw, ALX_ISR, intr); in alx_intr_msix_misc()
462 alx_write_mem32(hw, in alx_init_ring_ptrs()
471 alx_write_mem32(hw, ALX_RRD_ADDR_LO, np->rxq->rrd_dma); in alx_init_ring_ptrs()
472 alx_write_mem32(hw, ALX_RFD_ADDR_LO, np->rxq->rfd_dma); in alx_init_ring_ptrs()
476 alx_write_mem32(hw, ALX_TX_BASE_ADDR_HI, addr_hi); in alx_init_ring_ptrs()
477 alx_write_mem32(hw, ALX_TPD_RING_SZ, alx->tx_ringsz); in alx_init_ring_ptrs()
479 alx_write_mem32(hw, ALX_RX_BASE_ADDR_HI, addr_hi); in alx_init_ring_ptrs()
480 alx_write_mem32(hw, ALX_RRD_RING_SZ, alx->rx_ringsz); in alx_init_ring_ptrs()
481 alx_write_mem32(hw, ALX_RFD_RING_SZ, alx->rx_ringsz); in alx_init_ring_ptrs()
482 alx_write_mem32(hw, ALX_RFD_BUF_SZ, alx->rxbuf_size); in alx_init_ring_ptrs()
485 alx_write_mem32(hw, ALX_SRAM9, ALX_SRAM_LOAD_PTR); in alx_init_ring_ptrs()
579 alx_write_mem32(hw, ALX_HASH_TBL0, mc_hash[0]); in __alx_set_rx_mode()
580 alx_write_mem32(hw, ALX_HASH_TBL1, mc_hash[1]); in __alx_set_rx_mode()
589 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); in __alx_set_rx_mode()
824 alx_write_mem32(hw, ALX_MSI_MAP_TBL1, tbl[0]); in alx_config_vector_mapping()
825 alx_write_mem32(hw, ALX_MSI_MAP_TBL2, tbl[1]); in alx_config_vector_mapping()
826 alx_write_mem32(hw, ALX_MSI_ID_MAP, 0); in alx_config_vector_mapping()
921 alx_write_mem32(hw, ALX_ISR, 0); in alx_irq_enable()
922 alx_write_mem32(hw, ALX_IMR, alx->int_mask); in alx_irq_enable()
937 alx_write_mem32(hw, ALX_ISR, ALX_ISR_DIS); in alx_irq_disable()
938 alx_write_mem32(hw, ALX_IMR, 0); in alx_irq_disable()
984 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, msi_ctrl); in alx_request_irq()
996 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, in alx_request_irq()
1007 alx_write_mem32(hw, ALX_MSI_RETRANS_TIMER, 0); in alx_request_irq()
1147 alx_write_mem32(hw, ALX_MAC_CTRL, hw->rx_ctrl); in alx_configure()
1159 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS); in alx_activate()
1239 alx_write_mem32(&alx->hw, ALX_ISR, ~(u32)ALX_ISR_DIS); in __alx_open()
1310 alx_write_mem32(hw, ALX_IMR, alx->int_mask); in alx_check_link()