408 static void ag71xx_wr(struct ag71xx *ag, unsigned int reg, u32 value)  in ag71xx_wr()  function
585 	ag71xx_wr(ag, AG71XX_REG_MII_ADDR,  in ag71xx_mdio_mii_read()
588 	ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);  in ag71xx_mdio_mii_read()
596 	ag71xx_wr(ag, AG71XX_REG_MII_CMD, 0);  in ag71xx_mdio_mii_read()
612 	ag71xx_wr(ag, AG71XX_REG_MII_ADDR,  in ag71xx_mdio_mii_write()
614 	ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val);  in ag71xx_mdio_mii_write()
675 	ag71xx_wr(ag, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);  in ag71xx_mdio_reset()
678 	ag71xx_wr(ag, AG71XX_REG_MII_CFG, t);  in ag71xx_mdio_reset()
760 	ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);  in ag71xx_hw_stop()
761 	ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);  in ag71xx_hw_stop()
762 	ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);  in ag71xx_hw_stop()
838 			ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);  in ag71xx_tx_packets()
887 	ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);  in ag71xx_dma_reset()
888 	ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);  in ag71xx_dma_reset()
896 	ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);  in ag71xx_dma_reset()
897 	ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);  in ag71xx_dma_reset()
901 		ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);  in ag71xx_dma_reset()
902 		ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);  in ag71xx_dma_reset()
906 	ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);  in ag71xx_dma_reset()
907 	ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);  in ag71xx_dma_reset()
929 	ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);  in ag71xx_hw_setup()
935 	ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);  in ag71xx_hw_setup()
938 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);  in ag71xx_hw_setup()
939 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);  in ag71xx_hw_setup()
940 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);  in ag71xx_hw_setup()
941 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);  in ag71xx_hw_setup()
942 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);  in ag71xx_hw_setup()
957 	ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);  in ag71xx_hw_set_macaddr()
960 	ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);  in ag71xx_hw_set_macaddr()
988 	ag71xx_wr(ag, AG71XX_REG_MAC_MFL,  in ag71xx_fast_reset()
991 	ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);  in ag71xx_fast_reset()
992 	ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);  in ag71xx_fast_reset()
993 	ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);  in ag71xx_fast_reset()
1001 	ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);  in ag71xx_hw_start()
1004 	ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);  in ag71xx_hw_start()
1025 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);  in ag71xx_mac_config()
1073 	ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);  in ag71xx_mac_link_up()
1074 	ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);  in ag71xx_mac_link_up()
1075 	ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);  in ag71xx_mac_link_up()
1084 	ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, cfg1);  in ag71xx_mac_link_up()
1400 	ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);  in ag71xx_hw_enable()
1401 	ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);  in ag71xx_hw_enable()
1438 	ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);  in ag71xx_open()
1571 	ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);  in ag71xx_hard_start_xmit()
1650 		ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);  in ag71xx_rx_packets()
1717 		ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);  in ag71xx_poll()
1721 		ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);  in ag71xx_poll()
1769 			ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);  in ag71xx_interrupt()
1773 			ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);  in ag71xx_interrupt()
1792 	ag71xx_wr(ag, AG71XX_REG_MAC_MFL,  in ag71xx_change_mtu()
1935 	ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);  in ag71xx_probe()