105 	psc_write_word(PSC_ENETRD_CMD + set, 0x0100);  in mace_load_rxdma_base()
108 	psc_write_word(PSC_ENETRD_CMD + set, 0x9800);  in mace_load_rxdma_base()
124 	psc_write_word(PSC_ENETRD_CTL, 0x8800);  in mace_rxdma_reset()
126 	psc_write_word(PSC_ENETRD_CTL, 0x0400);  in mace_rxdma_reset()
128 	psc_write_word(PSC_ENETRD_CTL, 0x8800);  in mace_rxdma_reset()
130 	psc_write_word(PSC_ENETRD_CTL, 0x0400);  in mace_rxdma_reset()
135 	psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x9800);  in mace_rxdma_reset()
136 	psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x9800);  in mace_rxdma_reset()
149 	psc_write_word(PSC_ENETWR_CTL, 0x8800);  in mace_txdma_reset()
157 	psc_write_word(PSC_ENETWR_CTL, 0x0400);  in mace_txdma_reset()
167 	psc_write_word(PSC_ENETRD_CTL, 0x8800);  in mace_dma_off()
168 	psc_write_word(PSC_ENETRD_CTL, 0x1000);  in mace_dma_off()
169 	psc_write_word(PSC_ENETRD_CMD + PSC_SET0, 0x1100);  in mace_dma_off()
170 	psc_write_word(PSC_ENETRD_CMD + PSC_SET1, 0x1100);  in mace_dma_off()
172 	psc_write_word(PSC_ENETWR_CTL, 0x8800);  in mace_dma_off()
173 	psc_write_word(PSC_ENETWR_CTL, 0x1000);  in mace_dma_off()
174 	psc_write_word(PSC_ENETWR_CMD + PSC_SET0, 0x1100);  in mace_dma_off()
175 	psc_write_word(PSC_ENETWR_CMD + PSC_SET1, 0x1100);  in mace_dma_off()
404 	psc_write_word(PSC_ENETWR_CTL, 0x9000);  in mace_open()
405 	psc_write_word(PSC_ENETRD_CTL, 0x9000);  in mace_open()
406 	psc_write_word(PSC_ENETWR_CTL, 0x0400);  in mace_open()
407 	psc_write_word(PSC_ENETRD_CTL, 0x0400);  in mace_open()
474 	psc_write_word(PSC_ENETWR_CMD + mp->tx_slot, 0x9800);  in mace_xmit_start()
698 		psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x1100);  in mace_dma_intr()
718 			psc_write_word(PSC_ENETRD_CMD + mp->rx_slot, 0x9800);  in mace_dma_intr()
731 		psc_write_word(PSC_ENETWR_CMD + mp->tx_sloti, 0x0100);  in mace_dma_intr()