Lines Matching refs:p
14 static void xgene_enet_wr_csr(struct xgene_enet_pdata *p, u32 offset, u32 val) in xgene_enet_wr_csr() argument
16 iowrite32(val, p->eth_csr_addr + offset); in xgene_enet_wr_csr()
19 static void xgene_enet_wr_clkrst_csr(struct xgene_enet_pdata *p, u32 offset, in xgene_enet_wr_clkrst_csr() argument
22 iowrite32(val, p->base_addr + offset); in xgene_enet_wr_clkrst_csr()
25 static void xgene_enet_wr_ring_if(struct xgene_enet_pdata *p, in xgene_enet_wr_ring_if() argument
28 iowrite32(val, p->eth_ring_if_addr + offset); in xgene_enet_wr_ring_if()
31 static void xgene_enet_wr_diag_csr(struct xgene_enet_pdata *p, in xgene_enet_wr_diag_csr() argument
34 iowrite32(val, p->eth_diag_csr_addr + offset); in xgene_enet_wr_diag_csr()
45 static u32 xgene_enet_rd_csr(struct xgene_enet_pdata *p, u32 offset) in xgene_enet_rd_csr() argument
47 return ioread32(p->eth_csr_addr + offset); in xgene_enet_rd_csr()
50 static u32 xgene_enet_rd_diag_csr(struct xgene_enet_pdata *p, u32 offset) in xgene_enet_rd_diag_csr() argument
52 return ioread32(p->eth_diag_csr_addr + offset); in xgene_enet_rd_diag_csr()
55 static u32 xgene_enet_rd_mcx_csr(struct xgene_enet_pdata *p, u32 offset) in xgene_enet_rd_mcx_csr() argument
57 return ioread32(p->mcx_mac_csr_addr + offset); in xgene_enet_rd_mcx_csr()
60 static int xgene_enet_ecc_init(struct xgene_enet_pdata *p) in xgene_enet_ecc_init() argument
62 struct net_device *ndev = p->ndev; in xgene_enet_ecc_init()
66 shutdown = xgene_enet_rd_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR); in xgene_enet_ecc_init()
67 data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR); in xgene_enet_ecc_init()
74 xgene_enet_wr_diag_csr(p, ENET_CFG_MEM_RAM_SHUTDOWN_ADDR, 0); in xgene_enet_ecc_init()
77 data = xgene_enet_rd_diag_csr(p, ENET_BLOCK_MEM_RDY_ADDR); in xgene_enet_ecc_init()
104 static void xgene_enet_config_ring_if_assoc(struct xgene_enet_pdata *p) in xgene_enet_config_ring_if_assoc() argument
108 val = (p->enet_id == XGENE_ENET1) ? 0xffffffff : 0; in xgene_enet_config_ring_if_assoc()
109 xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
110 xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPQASSOC_ADDR, val); in xgene_enet_config_ring_if_assoc()
113 static void xgene_mii_phy_write(struct xgene_enet_pdata *p, u8 phy_id, in xgene_mii_phy_write() argument
120 xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); in xgene_mii_phy_write()
123 xgene_enet_wr_mac(p, MII_MGMT_CONTROL_ADDR, wr_data); in xgene_mii_phy_write()
126 done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR); in xgene_mii_phy_write()
132 netdev_err(p->ndev, "MII_MGMT write failed\n"); in xgene_mii_phy_write()
135 static u32 xgene_mii_phy_read(struct xgene_enet_pdata *p, u8 phy_id, u32 reg) in xgene_mii_phy_read() argument
141 xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); in xgene_mii_phy_read()
142 xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK); in xgene_mii_phy_read()
145 done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR); in xgene_mii_phy_read()
147 data = xgene_enet_rd_mac(p, MII_MGMT_STATUS_ADDR); in xgene_mii_phy_read()
148 xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, 0); in xgene_mii_phy_read()
155 netdev_err(p->ndev, "MII_MGMT read failed\n"); in xgene_mii_phy_read()
160 static void xgene_sgmac_reset(struct xgene_enet_pdata *p) in xgene_sgmac_reset() argument
162 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, SOFT_RESET1); in xgene_sgmac_reset()
163 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, 0); in xgene_sgmac_reset()
166 static void xgene_sgmac_set_mac_addr(struct xgene_enet_pdata *p) in xgene_sgmac_set_mac_addr() argument
168 const u8 *dev_addr = p->ndev->dev_addr; in xgene_sgmac_set_mac_addr()
173 xgene_enet_wr_mac(p, STATION_ADDR0_ADDR, addr0); in xgene_sgmac_set_mac_addr()
175 addr1 = xgene_enet_rd_mac(p, STATION_ADDR1_ADDR); in xgene_sgmac_set_mac_addr()
177 xgene_enet_wr_mac(p, STATION_ADDR1_ADDR, addr1); in xgene_sgmac_set_mac_addr()
180 static u32 xgene_enet_link_status(struct xgene_enet_pdata *p) in xgene_enet_link_status() argument
184 data = xgene_mii_phy_read(p, INT_PHY_ADDR, in xgene_enet_link_status()
188 p->phy_speed = SPEED_1000; in xgene_enet_link_status()
190 p->phy_speed = SPEED_100; in xgene_enet_link_status()
192 p->phy_speed = SPEED_10; in xgene_enet_link_status()
197 static void xgene_sgmii_configure(struct xgene_enet_pdata *p) in xgene_sgmii_configure() argument
199 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, in xgene_sgmii_configure()
201 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_CONTROL_ADDR >> 2, 0x9000); in xgene_sgmii_configure()
202 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0); in xgene_sgmii_configure()
205 static void xgene_sgmii_tbi_control_reset(struct xgene_enet_pdata *p) in xgene_sgmii_tbi_control_reset() argument
207 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, in xgene_sgmii_tbi_control_reset()
209 xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0); in xgene_sgmii_tbi_control_reset()
212 static void xgene_sgmii_reset(struct xgene_enet_pdata *p) in xgene_sgmii_reset() argument
216 if (p->phy_speed == SPEED_UNKNOWN) in xgene_sgmii_reset()
219 value = xgene_mii_phy_read(p, INT_PHY_ADDR, in xgene_sgmii_reset()
222 xgene_sgmii_tbi_control_reset(p); in xgene_sgmii_reset()
225 static void xgene_sgmac_set_speed(struct xgene_enet_pdata *p) in xgene_sgmac_set_speed() argument
231 xgene_sgmii_reset(p); in xgene_sgmac_set_speed()
233 if (p->enet_id == XGENE_ENET1) { in xgene_sgmac_set_speed()
234 icm0_addr = ICM_CONFIG0_REG_0_ADDR + p->port_id * OFFSET_8; in xgene_sgmac_set_speed()
235 icm2_addr = ICM_CONFIG2_REG_0_ADDR + p->port_id * OFFSET_4; in xgene_sgmac_set_speed()
243 icm0 = xgene_enet_rd_mcx_csr(p, icm0_addr); in xgene_sgmac_set_speed()
244 icm2 = xgene_enet_rd_mcx_csr(p, icm2_addr); in xgene_sgmac_set_speed()
245 mc2 = xgene_enet_rd_mac(p, MAC_CONFIG_2_ADDR); in xgene_sgmac_set_speed()
246 intf_ctl = xgene_enet_rd_mac(p, INTERFACE_CONTROL_ADDR); in xgene_sgmac_set_speed()
248 switch (p->phy_speed) { in xgene_sgmac_set_speed()
268 value = xgene_enet_rd_csr(p, debug_addr); in xgene_sgmac_set_speed()
270 xgene_enet_wr_csr(p, debug_addr, value); in xgene_sgmac_set_speed()
275 xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, mc2); in xgene_sgmac_set_speed()
276 xgene_enet_wr_mac(p, INTERFACE_CONTROL_ADDR, intf_ctl); in xgene_sgmac_set_speed()
277 xgene_enet_wr_mcx_csr(p, icm0_addr, icm0); in xgene_sgmac_set_speed()
278 xgene_enet_wr_mcx_csr(p, icm2_addr, icm2); in xgene_sgmac_set_speed()
286 static void xgene_sgmii_enable_autoneg(struct xgene_enet_pdata *p) in xgene_sgmii_enable_autoneg() argument
290 xgene_sgmii_configure(p); in xgene_sgmii_enable_autoneg()
293 data = xgene_mii_phy_read(p, INT_PHY_ADDR, in xgene_sgmii_enable_autoneg()
300 netdev_err(p->ndev, "Auto-negotiation failed\n"); in xgene_sgmii_enable_autoneg()
303 static void xgene_sgmac_rxtx(struct xgene_enet_pdata *p, u32 bits, bool set) in xgene_sgmac_rxtx() argument
307 data = xgene_enet_rd_mac(p, MAC_CONFIG_1_ADDR); in xgene_sgmac_rxtx()
314 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, data); in xgene_sgmac_rxtx()
317 static void xgene_sgmac_flowctl_tx(struct xgene_enet_pdata *p, bool enable) in xgene_sgmac_flowctl_tx() argument
319 xgene_sgmac_rxtx(p, TX_FLOW_EN, enable); in xgene_sgmac_flowctl_tx()
321 p->mac_ops->enable_tx_pause(p, enable); in xgene_sgmac_flowctl_tx()
329 static void xgene_sgmac_init(struct xgene_enet_pdata *p) in xgene_sgmac_init() argument
337 if (!(p->enet_id == XGENE_ENET2 && p->mdio_driver)) in xgene_sgmac_init()
338 xgene_sgmac_reset(p); in xgene_sgmac_init()
340 xgene_sgmii_enable_autoneg(p); in xgene_sgmac_init()
341 xgene_sgmac_set_speed(p); in xgene_sgmac_init()
342 xgene_sgmac_set_mac_addr(p); in xgene_sgmac_init()
344 if (p->enet_id == XGENE_ENET1) { in xgene_sgmac_init()
348 offset = p->port_id * OFFSET_4; in xgene_sgmac_init()
357 data = xgene_enet_rd_csr(p, enet_spare_cfg_reg); in xgene_sgmac_init()
359 xgene_enet_wr_csr(p, enet_spare_cfg_reg, data); in xgene_sgmac_init()
362 data = xgene_enet_rd_mac(p, MII_MGMT_CONFIG_ADDR); in xgene_sgmac_init()
364 xgene_enet_wr_mac(p, MII_MGMT_CONFIG_ADDR, data); in xgene_sgmac_init()
367 data = xgene_enet_rd_csr(p, rsif_config_reg); in xgene_sgmac_init()
369 xgene_enet_wr_csr(p, rsif_config_reg, data); in xgene_sgmac_init()
372 multi_dpf_reg = (p->enet_id == XGENE_ENET1) ? CSR_MULTI_DPF0_ADDR : in xgene_sgmac_init()
374 data = xgene_enet_rd_mcx_csr(p, multi_dpf_reg); in xgene_sgmac_init()
376 xgene_enet_wr_mcx_csr(p, multi_dpf_reg, data); in xgene_sgmac_init()
378 if (p->enet_id != XGENE_ENET1) { in xgene_sgmac_init()
379 data = xgene_enet_rd_mcx_csr(p, XG_MCX_MULTI_DPF1_ADDR); in xgene_sgmac_init()
381 xgene_enet_wr_mcx_csr(p, XG_MCX_MULTI_DPF1_ADDR, data); in xgene_sgmac_init()
384 pause_thres_reg = (p->enet_id == XGENE_ENET1) ? RXBUF_PAUSE_THRESH : in xgene_sgmac_init()
386 pause_off_thres_reg = (p->enet_id == XGENE_ENET1) ? in xgene_sgmac_init()
389 if (p->enet_id == XGENE_ENET1) { in xgene_sgmac_init()
390 data1 = xgene_enet_rd_csr(p, pause_thres_reg); in xgene_sgmac_init()
391 data2 = xgene_enet_rd_csr(p, pause_off_thres_reg); in xgene_sgmac_init()
393 if (!(p->port_id % 2)) { in xgene_sgmac_init()
401 xgene_enet_wr_csr(p, pause_thres_reg, data1); in xgene_sgmac_init()
402 xgene_enet_wr_csr(p, pause_off_thres_reg, data2); in xgene_sgmac_init()
405 xgene_enet_wr_csr(p, pause_thres_reg, data); in xgene_sgmac_init()
408 xgene_sgmac_flowctl_tx(p, p->tx_pause); in xgene_sgmac_init()
409 xgene_sgmac_flowctl_rx(p, p->rx_pause); in xgene_sgmac_init()
412 xgene_enet_wr_csr(p, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x84); in xgene_sgmac_init()
413 xgene_enet_wr_csr(p, cfg_bypass_reg, RESUME_TX); in xgene_sgmac_init()
414 xgene_enet_wr_mcx_csr(p, rx_dv_gate_reg, RESUME_RX0); in xgene_sgmac_init()
417 static void xgene_sgmac_rx_enable(struct xgene_enet_pdata *p) in xgene_sgmac_rx_enable() argument
419 xgene_sgmac_rxtx(p, RX_EN, true); in xgene_sgmac_rx_enable()
422 static void xgene_sgmac_tx_enable(struct xgene_enet_pdata *p) in xgene_sgmac_tx_enable() argument
424 xgene_sgmac_rxtx(p, TX_EN, true); in xgene_sgmac_tx_enable()
427 static void xgene_sgmac_rx_disable(struct xgene_enet_pdata *p) in xgene_sgmac_rx_disable() argument
429 xgene_sgmac_rxtx(p, RX_EN, false); in xgene_sgmac_rx_disable()
432 static void xgene_sgmac_tx_disable(struct xgene_enet_pdata *p) in xgene_sgmac_tx_disable() argument
434 xgene_sgmac_rxtx(p, TX_EN, false); in xgene_sgmac_tx_disable()
437 static int xgene_enet_reset(struct xgene_enet_pdata *p) in xgene_enet_reset() argument
439 struct device *dev = &p->pdev->dev; in xgene_enet_reset()
441 if (!xgene_ring_mgr_init(p)) in xgene_enet_reset()
444 if (p->mdio_driver && p->enet_id == XGENE_ENET2) { in xgene_enet_reset()
445 xgene_enet_config_ring_if_assoc(p); in xgene_enet_reset()
449 if (p->enet_id == XGENE_ENET2) in xgene_enet_reset()
450 xgene_enet_wr_clkrst_csr(p, XGENET_CONFIG_REG_ADDR, SGMII_EN); in xgene_enet_reset()
453 if (!IS_ERR(p->clk)) { in xgene_enet_reset()
454 clk_prepare_enable(p->clk); in xgene_enet_reset()
456 clk_disable_unprepare(p->clk); in xgene_enet_reset()
458 clk_prepare_enable(p->clk); in xgene_enet_reset()
465 status = acpi_evaluate_object(ACPI_HANDLE(&p->pdev->dev), in xgene_enet_reset()
468 acpi_evaluate_object(ACPI_HANDLE(&p->pdev->dev), in xgene_enet_reset()
474 if (!p->port_id) { in xgene_enet_reset()
475 xgene_enet_ecc_init(p); in xgene_enet_reset()
476 xgene_enet_config_ring_if_assoc(p); in xgene_enet_reset()
482 static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p, in xgene_enet_cle_bypass() argument
487 u32 offset = p->port_id * MAC_OFFSET; in xgene_enet_cle_bypass()
490 if (p->enet_id == XGENE_ENET1) { in xgene_enet_cle_bypass()
499 xgene_enet_wr_csr(p, cle_bypass_reg0 + offset, data); in xgene_enet_cle_bypass()
505 xgene_enet_wr_csr(p, cle_bypass_reg1 + offset, data); in xgene_enet_cle_bypass()
524 static void xgene_enet_shutdown(struct xgene_enet_pdata *p) in xgene_enet_shutdown() argument
526 struct device *dev = &p->pdev->dev; in xgene_enet_shutdown()
529 if (!IS_ERR(p->clk)) in xgene_enet_shutdown()
530 clk_disable_unprepare(p->clk); in xgene_enet_shutdown()
536 struct xgene_enet_pdata *p = container_of(to_delayed_work(work), in xgene_enet_link_state() local
538 struct net_device *ndev = p->ndev; in xgene_enet_link_state()
541 link = xgene_enet_link_status(p); in xgene_enet_link_state()
545 xgene_sgmac_set_speed(p); in xgene_enet_link_state()
546 xgene_sgmac_rx_enable(p); in xgene_enet_link_state()
547 xgene_sgmac_tx_enable(p); in xgene_enet_link_state()
549 p->phy_speed); in xgene_enet_link_state()
554 xgene_sgmac_rx_disable(p); in xgene_enet_link_state()
555 xgene_sgmac_tx_disable(p); in xgene_enet_link_state()
562 schedule_delayed_work(&p->link_work, poll_interval); in xgene_enet_link_state()
565 static void xgene_sgmac_enable_tx_pause(struct xgene_enet_pdata *p, bool enable) in xgene_sgmac_enable_tx_pause() argument
569 if (p->enet_id == XGENE_ENET1) { in xgene_sgmac_enable_tx_pause()
570 ecm_cfg_addr = (!(p->port_id % 2)) ? CSR_ECM_CFG_0_ADDR : in xgene_sgmac_enable_tx_pause()
576 data = xgene_enet_rd_mcx_csr(p, ecm_cfg_addr); in xgene_sgmac_enable_tx_pause()
581 xgene_enet_wr_mcx_csr(p, ecm_cfg_addr, data); in xgene_sgmac_enable_tx_pause()