Lines Matching refs:xgene_set_bits

20 static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len)  in xgene_set_bits()  function
139 #define PHY_CONTROL_SET(dst, val)	xgene_set_bits(dst, val, 0, 16)
157 #define CFG_TXCLK_MUXSEL0_SET(dst, val)	xgene_set_bits(dst, val, 29, 3)
158 #define CFG_RXCLK_MUXSEL0_SET(dst, val)	xgene_set_bits(dst, val, 26, 3)
160 #define CFG_CLE_IP_PROTOCOL0_SET(dst, val)	xgene_set_bits(dst, val, 16, 2)
161 #define CFG_CLE_IP_HDR_LEN_SET(dst, val)	xgene_set_bits(dst, val, 8, 5)
162 #define CFG_CLE_DSTQID0_SET(dst, val)		xgene_set_bits(dst, val, 0, 12)
163 #define CFG_CLE_FPSEL0_SET(dst, val)		xgene_set_bits(dst, val, 16, 4)
164 #define CFG_CLE_NXTFPSEL0_SET(dst, val)		xgene_set_bits(dst, val, 20, 4)
165 #define CFG_MACMODE_SET(dst, val)		xgene_set_bits(dst, val, 18, 2)
166 #define CFG_WAITASYNCRD_SET(dst, val)		xgene_set_bits(dst, val, 0, 16)
205 #define PHY_ADDR_SET(dst, val)			xgene_set_bits(dst, val, 8, 5)
206 #define REG_ADDR_SET(dst, val)			xgene_set_bits(dst, val, 0, 5)
207 #define ENET_INTERFACE_MODE2_SET(dst, val)	xgene_set_bits(dst, val, 8, 2)
208 #define MGMT_CLOCK_SEL_SET(dst, val)		xgene_set_bits(dst, val, 0, 3)