Lines Matching refs:pdata
222 static void xgbe_phy_kr_training_pre(struct xgbe_prv_data *pdata) in xgbe_phy_kr_training_pre() argument
224 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 1); in xgbe_phy_kr_training_pre()
227 static void xgbe_phy_kr_training_post(struct xgbe_prv_data *pdata) in xgbe_phy_kr_training_post() argument
229 XSIR0_IOWRITE_BITS(pdata, SIR0_KR_RT_1, RESET, 0); in xgbe_phy_kr_training_post()
232 static enum xgbe_mode xgbe_phy_an_outcome(struct xgbe_prv_data *pdata) in xgbe_phy_an_outcome() argument
234 struct ethtool_link_ksettings *lks = &pdata->phy.lks; in xgbe_phy_an_outcome()
235 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_an_outcome()
243 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); in xgbe_phy_an_outcome()
244 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); in xgbe_phy_an_outcome()
250 if (pdata->phy.pause_autoneg) { in xgbe_phy_an_outcome()
252 pdata->phy.tx_pause = 0; in xgbe_phy_an_outcome()
253 pdata->phy.rx_pause = 0; in xgbe_phy_an_outcome()
256 pdata->phy.tx_pause = 1; in xgbe_phy_an_outcome()
257 pdata->phy.rx_pause = 1; in xgbe_phy_an_outcome()
260 pdata->phy.rx_pause = 1; in xgbe_phy_an_outcome()
262 pdata->phy.tx_pause = 1; in xgbe_phy_an_outcome()
267 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); in xgbe_phy_an_outcome()
268 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); in xgbe_phy_an_outcome()
291 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); in xgbe_phy_an_outcome()
292 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); in xgbe_phy_an_outcome()
299 static void xgbe_phy_an_advertising(struct xgbe_prv_data *pdata, in xgbe_phy_an_advertising() argument
302 struct ethtool_link_ksettings *slks = &pdata->phy.lks; in xgbe_phy_an_advertising()
307 static int xgbe_phy_an_config(struct xgbe_prv_data *pdata) in xgbe_phy_an_config() argument
313 static enum xgbe_an_mode xgbe_phy_an_mode(struct xgbe_prv_data *pdata) in xgbe_phy_an_mode() argument
318 static void xgbe_phy_pcs_power_cycle(struct xgbe_prv_data *pdata) in xgbe_phy_pcs_power_cycle() argument
322 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_pcs_power_cycle()
325 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_pcs_power_cycle()
330 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_pcs_power_cycle()
333 static void xgbe_phy_start_ratechange(struct xgbe_prv_data *pdata) in xgbe_phy_start_ratechange() argument
336 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 1); in xgbe_phy_start_ratechange()
339 static void xgbe_phy_complete_ratechange(struct xgbe_prv_data *pdata) in xgbe_phy_complete_ratechange() argument
345 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, RATECHANGE, 0); in xgbe_phy_complete_ratechange()
352 status = XSIR0_IOREAD(pdata, SIR0_STATUS); in xgbe_phy_complete_ratechange()
358 netif_dbg(pdata, link, pdata->netdev, "SerDes rx/tx not ready (%#hx)\n", in xgbe_phy_complete_ratechange()
363 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 0); in xgbe_phy_complete_ratechange()
364 XRXTX_IOWRITE_BITS(pdata, RXTX_REG6, RESETB_RXD, 1); in xgbe_phy_complete_ratechange()
367 static void xgbe_phy_kr_mode(struct xgbe_prv_data *pdata) in xgbe_phy_kr_mode() argument
369 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_kr_mode()
373 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); in xgbe_phy_kr_mode()
376 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); in xgbe_phy_kr_mode()
378 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_kr_mode()
381 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_kr_mode()
383 xgbe_phy_pcs_power_cycle(pdata); in xgbe_phy_kr_mode()
386 xgbe_phy_start_ratechange(pdata); in xgbe_phy_kr_mode()
388 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_10000_RATE); in xgbe_phy_kr_mode()
389 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_10000_WORD); in xgbe_phy_kr_mode()
390 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_10000_PLL); in xgbe_phy_kr_mode()
392 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, in xgbe_phy_kr_mode()
394 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, in xgbe_phy_kr_mode()
396 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, in xgbe_phy_kr_mode()
398 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, in xgbe_phy_kr_mode()
400 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, in xgbe_phy_kr_mode()
402 XRXTX_IOWRITE(pdata, RXTX_REG22, in xgbe_phy_kr_mode()
405 xgbe_phy_complete_ratechange(pdata); in xgbe_phy_kr_mode()
407 netif_dbg(pdata, link, pdata->netdev, "10GbE KR mode set\n"); in xgbe_phy_kr_mode()
410 static void xgbe_phy_kx_2500_mode(struct xgbe_prv_data *pdata) in xgbe_phy_kx_2500_mode() argument
412 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_kx_2500_mode()
416 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); in xgbe_phy_kx_2500_mode()
419 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); in xgbe_phy_kx_2500_mode()
421 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_kx_2500_mode()
424 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_kx_2500_mode()
426 xgbe_phy_pcs_power_cycle(pdata); in xgbe_phy_kx_2500_mode()
429 xgbe_phy_start_ratechange(pdata); in xgbe_phy_kx_2500_mode()
431 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_2500_RATE); in xgbe_phy_kx_2500_mode()
432 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_2500_WORD); in xgbe_phy_kx_2500_mode()
433 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_2500_PLL); in xgbe_phy_kx_2500_mode()
435 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, in xgbe_phy_kx_2500_mode()
437 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, in xgbe_phy_kx_2500_mode()
439 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, in xgbe_phy_kx_2500_mode()
441 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, in xgbe_phy_kx_2500_mode()
443 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, in xgbe_phy_kx_2500_mode()
445 XRXTX_IOWRITE(pdata, RXTX_REG22, in xgbe_phy_kx_2500_mode()
448 xgbe_phy_complete_ratechange(pdata); in xgbe_phy_kx_2500_mode()
450 netif_dbg(pdata, link, pdata->netdev, "2.5GbE KX mode set\n"); in xgbe_phy_kx_2500_mode()
453 static void xgbe_phy_kx_1000_mode(struct xgbe_prv_data *pdata) in xgbe_phy_kx_1000_mode() argument
455 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_kx_1000_mode()
459 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); in xgbe_phy_kx_1000_mode()
462 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL2, reg); in xgbe_phy_kx_1000_mode()
464 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_kx_1000_mode()
467 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_kx_1000_mode()
469 xgbe_phy_pcs_power_cycle(pdata); in xgbe_phy_kx_1000_mode()
472 xgbe_phy_start_ratechange(pdata); in xgbe_phy_kx_1000_mode()
474 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, DATARATE, XGBE_SPEED_1000_RATE); in xgbe_phy_kx_1000_mode()
475 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, WORDMODE, XGBE_SPEED_1000_WORD); in xgbe_phy_kx_1000_mode()
476 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, PLLSEL, XGBE_SPEED_1000_PLL); in xgbe_phy_kx_1000_mode()
478 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, CDR_RATE, in xgbe_phy_kx_1000_mode()
480 XSIR1_IOWRITE_BITS(pdata, SIR1_SPEED, TXAMP, in xgbe_phy_kx_1000_mode()
482 XRXTX_IOWRITE_BITS(pdata, RXTX_REG20, BLWC_ENA, in xgbe_phy_kx_1000_mode()
484 XRXTX_IOWRITE_BITS(pdata, RXTX_REG114, PQ_REG, in xgbe_phy_kx_1000_mode()
486 XRXTX_IOWRITE_BITS(pdata, RXTX_REG129, RXDFE_CONFIG, in xgbe_phy_kx_1000_mode()
488 XRXTX_IOWRITE(pdata, RXTX_REG22, in xgbe_phy_kx_1000_mode()
491 xgbe_phy_complete_ratechange(pdata); in xgbe_phy_kx_1000_mode()
493 netif_dbg(pdata, link, pdata->netdev, "1GbE KX mode set\n"); in xgbe_phy_kx_1000_mode()
496 static enum xgbe_mode xgbe_phy_cur_mode(struct xgbe_prv_data *pdata) in xgbe_phy_cur_mode() argument
498 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_cur_mode()
502 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL2); in xgbe_phy_cur_mode()
517 static enum xgbe_mode xgbe_phy_switch_mode(struct xgbe_prv_data *pdata) in xgbe_phy_switch_mode() argument
519 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_switch_mode()
523 if (xgbe_phy_cur_mode(pdata) == XGBE_MODE_KR) { in xgbe_phy_switch_mode()
535 static enum xgbe_mode xgbe_phy_get_mode(struct xgbe_prv_data *pdata, in xgbe_phy_get_mode() argument
538 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_get_mode()
554 static void xgbe_phy_set_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) in xgbe_phy_set_mode() argument
558 xgbe_phy_kx_1000_mode(pdata); in xgbe_phy_set_mode()
561 xgbe_phy_kx_2500_mode(pdata); in xgbe_phy_set_mode()
564 xgbe_phy_kr_mode(pdata); in xgbe_phy_set_mode()
571 static bool xgbe_phy_check_mode(struct xgbe_prv_data *pdata, in xgbe_phy_check_mode() argument
574 if (pdata->phy.autoneg == AUTONEG_ENABLE) { in xgbe_phy_check_mode()
579 cur_mode = xgbe_phy_get_mode(pdata, pdata->phy.speed); in xgbe_phy_check_mode()
587 static bool xgbe_phy_use_mode(struct xgbe_prv_data *pdata, enum xgbe_mode mode) in xgbe_phy_use_mode() argument
589 struct ethtool_link_ksettings *lks = &pdata->phy.lks; in xgbe_phy_use_mode()
593 return xgbe_phy_check_mode(pdata, mode, in xgbe_phy_use_mode()
596 return xgbe_phy_check_mode(pdata, mode, in xgbe_phy_use_mode()
599 return xgbe_phy_check_mode(pdata, mode, in xgbe_phy_use_mode()
606 static bool xgbe_phy_valid_speed(struct xgbe_prv_data *pdata, int speed) in xgbe_phy_valid_speed() argument
608 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_valid_speed()
626 static int xgbe_phy_link_status(struct xgbe_prv_data *pdata, int *an_restart) in xgbe_phy_link_status() argument
635 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); in xgbe_phy_link_status()
636 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); in xgbe_phy_link_status()
641 static void xgbe_phy_stop(struct xgbe_prv_data *pdata) in xgbe_phy_stop() argument
646 static int xgbe_phy_start(struct xgbe_prv_data *pdata) in xgbe_phy_start() argument
652 static int xgbe_phy_reset(struct xgbe_prv_data *pdata) in xgbe_phy_reset() argument
657 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_reset()
659 XMDIO_WRITE(pdata, MDIO_MMD_PCS, MDIO_CTRL1, reg); in xgbe_phy_reset()
664 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1); in xgbe_phy_reset()
673 static void xgbe_phy_exit(struct xgbe_prv_data *pdata) in xgbe_phy_exit() argument
678 static int xgbe_phy_init(struct xgbe_prv_data *pdata) in xgbe_phy_init() argument
680 struct ethtool_link_ksettings *lks = &pdata->phy.lks; in xgbe_phy_init()
684 phy_data = devm_kzalloc(pdata->dev, sizeof(*phy_data), GFP_KERNEL); in xgbe_phy_init()
689 ret = device_property_read_u32(pdata->phy_dev, XGBE_SPEEDSET_PROPERTY, in xgbe_phy_init()
692 dev_err(pdata->dev, "invalid %s property\n", in xgbe_phy_init()
702 dev_err(pdata->dev, "invalid %s property\n", in xgbe_phy_init()
708 if (device_property_present(pdata->phy_dev, XGBE_BLWC_PROPERTY)) { in xgbe_phy_init()
709 ret = device_property_read_u32_array(pdata->phy_dev, in xgbe_phy_init()
714 dev_err(pdata->dev, "invalid %s property\n", in xgbe_phy_init()
723 if (device_property_present(pdata->phy_dev, XGBE_CDR_RATE_PROPERTY)) { in xgbe_phy_init()
724 ret = device_property_read_u32_array(pdata->phy_dev, in xgbe_phy_init()
729 dev_err(pdata->dev, "invalid %s property\n", in xgbe_phy_init()
738 if (device_property_present(pdata->phy_dev, XGBE_PQ_SKEW_PROPERTY)) { in xgbe_phy_init()
739 ret = device_property_read_u32_array(pdata->phy_dev, in xgbe_phy_init()
744 dev_err(pdata->dev, "invalid %s property\n", in xgbe_phy_init()
753 if (device_property_present(pdata->phy_dev, XGBE_TX_AMP_PROPERTY)) { in xgbe_phy_init()
754 ret = device_property_read_u32_array(pdata->phy_dev, in xgbe_phy_init()
759 dev_err(pdata->dev, "invalid %s property\n", in xgbe_phy_init()
768 if (device_property_present(pdata->phy_dev, XGBE_DFE_CFG_PROPERTY)) { in xgbe_phy_init()
769 ret = device_property_read_u32_array(pdata->phy_dev, in xgbe_phy_init()
774 dev_err(pdata->dev, "invalid %s property\n", in xgbe_phy_init()
783 if (device_property_present(pdata->phy_dev, XGBE_DFE_ENA_PROPERTY)) { in xgbe_phy_init()
784 ret = device_property_read_u32_array(pdata->phy_dev, in xgbe_phy_init()
789 dev_err(pdata->dev, "invalid %s property\n", in xgbe_phy_init()
814 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) in xgbe_phy_init()
817 pdata->phy_data = phy_data; in xgbe_phy_init()