ethernet/amd/ariadne.h

353     volatile u_char PGCR;	/* Port General Control Register */
354     u_char Pad1[1];
355     volatile u_char PSRR;	/* Port Service Request Register */
356     u_char Pad2[1];
357     volatile u_char PADDR;	/* Port A Data Direction Register */
358     u_char Pad3[1];
359     volatile u_char PBDDR;	/* Port B Data Direction Register */
360     u_char Pad4[1];
361     volatile u_char PCDDR;	/* Port C Data Direction Register */
362     u_char Pad5[1];
363     volatile u_char PIVR;	/* Port Interrupt Vector Register */
364     u_char Pad6[1];
365     volatile u_char PACR;	/* Port A Control Register */
366     u_char Pad7[1];
367     volatile u_char PBCR;	/* Port B Control Register */
368     u_char Pad8[1];
369     volatile u_char PADR;	/* Port A Data Register */
370     u_char Pad9[1];
371     volatile u_char PBDR;	/* Port B Data Register */
372     u_char Pad10[1];
373     volatile u_char PAAR;	/* Port A Alternate Register */
374     u_char Pad11[1];
375     volatile u_char PBAR;	/* Port B Alternate Register */
376     u_char Pad12[1];
377     volatile u_char PCDR;	/* Port C Data Register */
378     u_char Pad13[1];
379     volatile u_char PSR;	/* Port Status Register */
380     u_char Pad14[5];
381     volatile u_char TCR;	/* Timer Control Register */
382     u_char Pad15[1];
383     volatile u_char TIVR;	/* Timer Interrupt Vector Register */
384     u_char Pad16[3];
385     volatile u_char CPRH;	/* Counter Preload Register (High) */
386     u_char Pad17[1];
387     volatile u_char CPRM;	/* Counter Preload Register (Mid) */
388     u_char Pad18[1];
389     volatile u_char CPRL;	/* Counter Preload Register (Low) */
390     u_char Pad19[3];
391     volatile u_char CNTRH;	/* Count Register (High) */
392     u_char Pad20[1];
393     volatile u_char CNTRM;	/* Count Register (Mid) */
394     u_char Pad21[1];
395     volatile u_char CNTRL;	/* Count Register (Low) */
396     u_char Pad22[1];
397     volatile u_char TSR;	/* Timer Status Register */
398     u_char Pad23[11];