Lines Matching full:receive
78 #define CSR18 0x1200 /* Current Receive Buffer Address */
79 #define CSR19 0x1300 /* Current Receive Buffer Address */
82 #define CSR22 0x1600 /* Next Receive Buffer Address */
83 #define CSR23 0x1700 /* Next Receive Buffer Address */
84 #define CSR24 0x1800 /* - Base Address of Receive Ring */
85 #define CSR25 0x1900 /* - Base Address of Receive Ring */
86 #define CSR26 0x1a00 /* Next Receive Descriptor Address */
87 #define CSR27 0x1b00 /* Next Receive Descriptor Address */
88 #define CSR28 0x1c00 /* Current Receive Descriptor Address */
89 #define CSR29 0x1d00 /* Current Receive Descriptor Address */
96 #define CSR36 0x2400 /* Next Next Receive Descriptor Address */
97 #define CSR37 0x2500 /* Next Next Receive Descriptor Address */
100 #define CSR40 0x2800 /* Current Receive Status and Byte Count */
101 #define CSR41 0x2900 /* Current Receive Status and Byte Count */
104 #define CSR44 0x2c00 /* Next Receive Status and Byte Count */
105 #define CSR45 0x2d00 /* Next Receive Status and Byte Count */
132 #define CSR72 0x4800 /* Receive Ring Counter */
134 #define CSR76 0x4c00 /* - Receive Ring Length */
154 #define CSR114 0x7200 /* - Receive Collision Count */
184 #define RINT 0x0004 /* Receive Interrupt */
189 #define RXON 0x2000 /* Receive On */
206 #define RINTM 0x0004 /* Receive Interrupt Mask */
227 #define RCVCCO 0x2000 /* Receive Collision Counter Overflow Interrupt */
228 #define RCVCCOM 0x1000 /* Receive Collision Counter Overflow Mask */
242 #define DRCVBC 0x0040 /* Disable Receive Broadcast */
243 #define DRCVPA 0x0020 /* Disable Receive Physical Address */
247 #define LRTTSEL 0x0002 /* Low Receive Threshold/Transmit Mode Select */
277 #define RVPOLE 0x0800 /* Enable Receive Polarity Signal */
278 #define RCVE 0x0400 /* Enable Receive Status Signal */
284 * Receive Descriptor Ring Entry
289 volatile u_short RMD1; /* HADR[23:16] | Receive Flags */
308 * Receive Flags