150 	writel(addr_low, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_LO_OFF);  in ena_com_admin_init_aenq()
151 	writel(addr_high, ena_dev->reg_bar + ENA_REGS_AENQ_BASE_HI_OFF);  in ena_com_admin_init_aenq()
158 	writel(aenq_caps, ena_dev->reg_bar + ENA_REGS_AENQ_CAPS_OFF);  in ena_com_admin_init_aenq()
813 		return readl(ena_dev->reg_bar + offset);  in ena_com_reg_bar_read32()
824 	writel(mmio_read_reg, ena_dev->reg_bar + ENA_REGS_MMIO_REG_READ_OFF);  in ena_com_reg_bar_read32()
1233 	io_sq->db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_create_io_sq()
1378 	io_cq->unmask_reg = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_create_io_cq()
1383 			(u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_create_io_cq()
1388 			(u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_create_io_cq()
1496 	writel(depth, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);  in ena_com_admin_aenq_enable()
1657 	writel(mask_value, ena_dev->reg_bar + ENA_REGS_INTR_MASK_OFF);  in ena_com_set_admin_polling_mode()
1701 	writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);  in ena_com_mmio_reg_read_request_destroy()
1702 	writel(0x0, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);  in ena_com_mmio_reg_read_request_destroy()
1718 	writel(addr_low, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_LO_OFF);  in ena_com_mmio_reg_read_request_write_dev_addr()
1719 	writel(addr_high, ena_dev->reg_bar + ENA_REGS_MMIO_RESP_HI_OFF);  in ena_com_mmio_reg_read_request_write_dev_addr()
1763 	admin_queue->sq.db_addr = (u32 __iomem *)((uintptr_t)ena_dev->reg_bar +  in ena_com_admin_init()
1769 	writel(addr_low, ena_dev->reg_bar + ENA_REGS_AQ_BASE_LO_OFF);  in ena_com_admin_init()
1770 	writel(addr_high, ena_dev->reg_bar + ENA_REGS_AQ_BASE_HI_OFF);  in ena_com_admin_init()
1775 	writel(addr_low, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_LO_OFF);  in ena_com_admin_init()
1776 	writel(addr_high, ena_dev->reg_bar + ENA_REGS_ACQ_BASE_HI_OFF);  in ena_com_admin_init()
1790 	writel(aq_caps, ena_dev->reg_bar + ENA_REGS_AQ_CAPS_OFF);  in ena_com_admin_init()
1791 	writel(acq_caps, ena_dev->reg_bar + ENA_REGS_ACQ_CAPS_OFF);  in ena_com_admin_init()
2051 	writel_relaxed((u32)aenq->head, ena_dev->reg_bar + ENA_REGS_AENQ_HEAD_DB_OFF);  in ena_com_aenq_intr_handler()
2084 	writel(reset_val, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);  in ena_com_dev_reset()
2097 	writel(0, ena_dev->reg_bar + ENA_REGS_DEV_CTL_OFF);  in ena_com_dev_reset()