Lines Matching full:address
78 /* START OF GLOBAL REGISTER ADDRESS MAP */
81 * Tx queue start address reg in global address map at address 0x0000
82 * tx queue end address reg in global address map at address 0x0004
83 * rx queue start address reg in global address map at address 0x0008
84 * rx queue end address reg in global address map at address 0x000C
87 /* structure for power management control status reg in global address map
88 * located at address 0x0010
103 /* Interrupt status reg at address 0x0018
120 /* Interrupt mask register at address 0x001C
121 * Interrupt alias clear mask reg at address 0x0020
122 * Interrupt status alias reg at address 0x0024
127 /* Software reset reg at address 0x0028
139 /* SLV Timer reg at address 0x002C (low 24 bits)
142 /* MSI Configuration reg at address 0x0030
147 /* Loopback reg located at address 0x0034
152 /* GLOBAL Module of JAGCore Address Mapping
153 * Located at address 0x0000
173 /* START OF TXDMA REGISTER ADDRESS MAP */
174 /* txdma control status reg at address 0x1000
183 /* structure for txdma packet ring base address hi reg in txdma address map
184 * located at address 0x1004
188 /* structure for txdma packet ring base address low reg in txdma address map
189 * located at address 0x1008
193 /* structure for txdma packet ring number of descriptor reg in txdma address
194 * map. Located at address 0x100C
211 * txdma tx queue write address reg in txdma address map at 0x1010
212 * txdma tx queue write address external reg in txdma address map at 0x1014
213 * txdma tx queue read address reg in txdma address map at 0x1018
216 * txdma status writeback address hi reg in txdma address map at0x101C
217 * txdma status writeback address lo reg in txdma address map at 0x1020
220 * txdma service request reg in txdma address map at 0x1024
221 * structure for txdma service complete reg in txdma address map at 0x1028
224 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
225 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
227 * txdma error reg in txdma address map at address 0x1034
236 /* Tx DMA Module of JAGCore Address Mapping
237 * Located at address 0x1000
268 /* END OF TXDMA REGISTER ADDRESS MAP */
270 /* START OF RXDMA REGISTER ADDRESS MAP */
271 /* structure for control status reg in rxdma address map
272 * Located at address 0x2000
300 /* structure for dma writeback lo reg in rxdma address map
301 * located at address 0x2004
305 /* structure for dma writeback hi reg in rxdma address map
306 * located at address 0x2008
310 /* structure for number of packets done reg in rxdma address map
311 * located at address 0x200C
317 /* structure for max packet time reg in rxdma address map
318 * located at address 0x2010
324 /* structure for rx queue read address reg in rxdma address map
325 * located at address 0x2014
329 /* structure for rx queue read address external reg in rxdma address map
330 * located at address 0x2018
334 /* structure for rx queue write address reg in rxdma address map
335 * located at address 0x201C
339 /* structure for packet status ring base address lo reg in rxdma address map
340 * located at address 0x2020
344 /* structure for packet status ring base address hi reg in rxdma address map
345 * located at address 0x2024
349 /* structure for packet status ring number of descriptors reg in rxdma address
350 * map. Located at address 0x2028
357 /* structure for packet status ring available offset reg in rxdma address map
358 * located at address 0x202C
365 /* structure for packet status ring full offset reg in rxdma address map
366 * located at address 0x2030
373 /* structure for packet status ring access index reg in rxdma address map
374 * located at address 0x2034
380 /* structure for packet status ring minimum descriptors reg in rxdma address
381 * map. Located at address 0x2038
387 /* structure for free buffer ring base lo address reg in rxdma address map
388 * located at address 0x203C
392 /* structure for free buffer ring base hi address reg in rxdma address map
393 * located at address 0x2040
397 /* structure for free buffer ring number of descriptors reg in rxdma address
398 * map. Located at address 0x2044
404 /* structure for free buffer ring 0 available offset reg in rxdma address map
405 * located at address 0x2048
409 /* structure for free buffer ring 0 full offset reg in rxdma address map
410 * located at address 0x204C
414 /* structure for free buffer cache 0 full offset reg in rxdma address map
415 * located at address 0x2050
421 /* structure for free buffer ring 0 minimum descriptor reg in rxdma address map
422 * located at address 0x2054
428 /* structure for free buffer ring 1 base address lo reg in rxdma address map
429 * located at address 0x2058 - 0x205C
433 /* structure for free buffer ring 1 number of descriptors reg in rxdma address
434 * map. Located at address 0x2060
438 /* structure for free buffer ring 1 available offset reg in rxdma address map
439 * located at address 0x2064
443 /* structure for free buffer ring 1 full offset reg in rxdma address map
444 * located at address 0x2068
448 /* structure for free buffer cache 1 read index reg in rxdma address map
449 * located at address 0x206C
453 /* structure for free buffer ring 1 minimum descriptor reg in rxdma address map
454 * located at address 0x2070
458 /* Rx DMA Module of JAGCore Address Mapping
459 * Located at address 0x2000
493 /* END OF RXDMA REGISTER ADDRESS MAP */
495 /* START OF TXMAC REGISTER ADDRESS MAP */
496 /* structure for control reg in txmac address map
497 * located at address 0x3000
513 /* structure for shadow pointer reg in txmac address map
514 * located at address 0x3004
521 /* structure for error count reg in txmac address map
522 * located at address 0x3008
530 /* structure for max fill reg in txmac address map
531 * located at address 0x300C
536 /* structure for cf parameter reg in txmac address map
537 * located at address 0x3010
542 /* structure for tx test reg in txmac address map
543 * located at address 0x3014
551 /* structure for error reg in txmac address map
552 * located at address 0x3018
565 /* structure for error interrupt reg in txmac address map
566 * located at address 0x301C
579 /* structure for error interrupt reg in txmac address map
580 * located at address 0x3020
587 /* Tx MAC Module of JAGCore Address Mapping
601 /* END OF TXMAC REGISTER ADDRESS MAP */
603 /* START OF RXMAC REGISTER ADDRESS MAP */
605 /* structure for rxmac control reg in rxmac address map
606 * located at address 0x4000
620 /* structure for Wake On Lan Control and CRC 0 reg in rxmac address map
621 * located at address 0x4004
634 /* structure for CRC 1 and CRC 2 reg in rxmac address map
635 * located at address 0x4008
641 /* structure for CRC 3 and CRC 4 reg in rxmac address map
642 * located at address 0x400C
648 /* structure for Wake On Lan Source Address Lo reg in rxmac address map
649 * located at address 0x4010
660 /* structure for Wake On Lan Source Address Hi reg in rxmac address map
661 * located at address 0x4014
669 /* structure for Wake On Lan mask reg in rxmac address map
670 * located at address 0x4018 - 0x4064
674 /* structure for Unicast Packet Filter Address 1 reg in rxmac address map
675 * located at address 0x4068
686 /* structure for Unicast Packet Filter Address 2 reg in rxmac address map
687 * located at address 0x406C
698 /* structure for Unicast Packet Filter Address 1 & 2 reg in rxmac address map
699 * located at address 0x4070
710 /* structure for Multicast Hash reg in rxmac address map
711 * located at address 0x4074 - 0x4080
715 /* structure for Packet Filter Control reg in rxmac address map
716 * located at address 0x4084
733 * address map. Located at address 0x4088
744 /* structure for Memory Controller Interface Water Mark reg in rxmac address
745 * map. Located at address 0x408C
753 /* structure for Rx Queue Dialog reg in rxmac address map.
754 * located at address 0x4090
762 /* structure for space available reg in rxmac address map.
763 * located at address 0x4094
771 /* structure for management interface reg in rxmac address map.
772 * located at address 0x4098
779 /* structure for Error reg in rxmac address map.
780 * located at address 0x409C
789 /* Rx MAC Module of JAGCore Address Mapping
835 /* END OF RXMAC REGISTER ADDRESS MAP */
837 /* START OF MAC REGISTER ADDRESS MAP */
838 /* structure for configuration #1 reg in mac address map.
839 * located at address 0x5000
871 /* structure for configuration #2 reg in mac address map.
872 * located at address 0x5004
895 /* structure for Interpacket gap reg in mac address map.
896 * located at address 0x5008
905 * structure for half duplex reg in mac address map.
906 * located at address 0x500C
918 /* structure for Maximum Frame Length reg in mac address map.
919 * located at address 0x5010: bits 0-15 hold the length.
922 /* structure for Reserve 1 reg in mac address map.
923 * located at address 0x5014 - 0x5018
927 /* structure for Test reg in mac address map.
928 * located at address 0x501C
932 /* structure for MII Management Configuration reg in mac address map.
933 * located at address 0x5020
944 /* structure for MII Management Command reg in mac address map.
945 * located at address 0x5024
950 /* structure for MII Management Address reg in mac address map.
951 * located at address 0x5028
959 /* structure for MII Management Control reg in mac address map.
960 * located at address 0x502C
965 /* structure for MII Management Status reg in mac address map.
966 * located at address 0x5030
972 /* structure for MII Management Indicators reg in mac address map.
973 * located at address 0x5034
982 /* structure for Interface Control reg in mac address map.
983 * located at address 0x5038
1006 /* structure for Interface Status reg in mac address map.
1007 * located at address 0x503C
1022 /* structure for Mac Station Address, Part 1 reg in mac address map.
1023 * located at address 0x5040
1034 /* structure for Mac Station Address, Part 2 reg in mac address map.
1035 * located at address 0x5044
1044 /* MAC Module of JAGCore Address Mapping
1067 /* END OF MAC REGISTER ADDRESS MAP */
1069 /* START OF MAC STAT REGISTER ADDRESS MAP */
1071 * stat address map address 0x6130 and 0x6138.
1100 /* structure for Carry Register Two Mask Register reg in mac stat address map.
1101 * located at address 0x613C
1126 /* MAC STATS Module of JAGCore Address Mapping
1182 /* END OF MAC STAT REGISTER ADDRESS MAP */
1184 /* START OF MMC REGISTER ADDRESS MAP */
1185 /* Main Memory Controller Control reg in mmc address map.
1186 * located at address 0x7000
1196 /* Main Memory Controller Host Memory Access Address reg in mmc
1197 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1204 * address map. Located at address 0x7008 - 0x7014
1208 /* Memory Control Module of JAGCore Address Mapping
1219 /* END OF MMC REGISTER ADDRESS MAP */
1221 /* JAGCore Address Mapping
1225 /* unused section of global address map */
1228 /* unused section of txdma address map */
1231 /* unused section of rxdma address map */
1234 /* unused section of txmac address map */
1237 /* unused section of rxmac address map */
1240 /* unused section of mac address map */
1243 /* unused section of mac stat address map */
1246 /* unused section of mmc address map */
1248 /* unused section of address map */
1251 u8 unused__[524288]; /* unused section of address map */