243 static int adin1110_write_reg(struct adin1110_priv *priv, u16 reg, u32 val)  in adin1110_write_reg()  function
278 	return adin1110_write_reg(priv, reg, write_val);  in adin1110_set_bits()
394 	ret = adin1110_write_reg(priv, ADIN1110_TX_FSIZE, padded_len);  in adin1110_write_fifo()
456 	ret = adin1110_write_reg(priv, ADIN1110_MDIOACC, val);  in adin1110_mdio_read()
493 	ret = adin1110_write_reg(priv, ADIN1110_MDIOACC, val);  in adin1110_mdio_write()
612 	adin1110_write_reg(priv, ADIN1110_STATUS0, ADIN1110_CLEAR_STATUS0);  in adin1110_irq()
613 	adin1110_write_reg(priv, ADIN1110_STATUS1, priv->irq_mask);  in adin1110_irq()
651 	ret =  adin1110_write_reg(priv,  in adin1110_write_mac_address()
659 		ret = adin1110_write_reg(priv,  in adin1110_write_mac_address()
666 		return adin1110_write_reg(priv,  in adin1110_write_mac_address()
679 	ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_FILTER_UPR + offset, 0);  in adin1110_clear_mac_address()
683 	ret =  adin1110_write_reg(priv, ADIN1110_MAC_ADDR_FILTER_LWR + offset, 0);  in adin1110_clear_mac_address()
689 		ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_MASK_UPR + offset, 0);  in adin1110_clear_mac_address()
693 		ret = adin1110_write_reg(priv, ADIN1110_MAC_ADDR_MASK_LWR + offset, 0);  in adin1110_clear_mac_address()
892 	ret = adin1110_write_reg(priv, ADIN1110_CONFIG2, ADIN1110_CRC_APPEND);  in adin1110_net_open()
901 	ret = adin1110_write_reg(priv, ADIN1110_IMASK1, ~val);  in adin1110_net_open()
1672 	ret = adin1110_write_reg(priv, ADIN1110_RESET, ADIN1110_SWRESET);  in adin1110_probe()