442 	retval = (retval << 1) | ((inb_p(addr) & MDIO_DATA_READ) != 0);  in mdio_read()
531 	if ((inb_p(nic_base+EN0_ISR) & ENISR_RESET) != 0)  in axnet_reset_8390()
563     if (info->stale++ && (inb_p(nic_base + EN0_ISR) & ENISR_ALL)) {  in ei_watchdog()
1116 			    inb_p(e8390_base + EN0_ISR),  in ax_interrupt()
1117 			    inb_p(e8390_base + EN0_IMR));  in ax_interrupt()
1124 		  inb_p(e8390_base + EN0_ISR));  in ax_interrupt()
1130 	while ((interrupts = inb_p(e8390_base + EN0_ISR)) != 0 &&  in ax_interrupt()
1165 			dev->stats.rx_frame_errors += inb_p(e8390_base + EN0_COUNTER0);  in ax_interrupt()
1166 			dev->stats.rx_crc_errors   += inb_p(e8390_base + EN0_COUNTER1);  in ax_interrupt()
1167 			dev->stats.rx_missed_errors+= inb_p(e8390_base + EN0_COUNTER2);  in ax_interrupt()
1214 	unsigned char txsr = inb_p(e8390_base+EN0_TSR);  in ei_tx_err()
1352 		rxing_page = inb_p(e8390_base + EN1_CURPAG -1);  in ei_receive()
1355 		this_frame = inb_p(e8390_base + EN0_BOUNDARY) + 1;  in ei_receive()
1465 	was_txing = inb_p(e8390_base+E8390_CMD) & E8390_TRANS;  in ei_rx_overrun()
1491 		unsigned char tx_completed = inb_p(e8390_base+EN0_ISR) & (ENISR_TX+ENISR_TX_ERR);  in ei_rx_overrun()
1532 	dev->stats.rx_frame_errors += inb_p(ioaddr + EN0_COUNTER0);  in get_stats()
1533 	dev->stats.rx_crc_errors   += inb_p(ioaddr + EN0_COUNTER1);  in get_stats()
1534 	dev->stats.rx_missed_errors+= inb_p(ioaddr + EN0_COUNTER2);  in get_stats()
1662 		if(inb_p(e8390_base + EN1_PHYS_SHIFT(i))!=dev->dev_addr[i])  in AX88190_init()
1698 	if (inb_p(e8390_base) & E8390_TRANS)   in NS8390_trigger_send()