465 	IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,  enumerator
1702 	vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |  in vortex_up()
1708 	iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,  in vortex_up()
1899 	if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {  in vortex_tx_timeout()
2270 	if ((status & IntLatch) == 0)  in _vortex_interrupt()
2345 			} while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);  in _vortex_interrupt()
2351 		iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);  in _vortex_interrupt()
2352 	} while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));  in _vortex_interrupt()
2388 	if ((status & IntLatch) == 0)  in _boomerang_interrupt()
2481 			} while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);  in _boomerang_interrupt()
2487 		iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);  in _boomerang_interrupt()
2491 	} while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);  in _boomerang_interrupt()