Lines Matching +full:0 +full:x8c8
18 #define A5PSW_REVISION 0x0
19 #define A5PSW_PORT_OFFSET(port) (0x400 * (port))
21 #define A5PSW_PORT_ENA 0x8
26 #define A5PSW_UCAST_DEF_MASK 0xC
28 #define A5PSW_VLAN_VERIFY 0x10
29 #define A5PSW_VLAN_VERI_SHIFT 0
32 #define A5PSW_BCAST_DEF_MASK 0x14
33 #define A5PSW_MCAST_DEF_MASK 0x18
35 #define A5PSW_INPUT_LEARN 0x1C
39 #define A5PSW_MGMT_CFG 0x20
42 #define A5PSW_MODE_CFG 0x24
45 #define A5PSW_VLAN_IN_MODE 0x28
47 #define A5PSW_VLAN_IN_MODE_PORT(port) (GENMASK(1, 0) << \
49 #define A5PSW_VLAN_IN_MODE_SINGLE_PASSTHROUGH 0x0
50 #define A5PSW_VLAN_IN_MODE_SINGLE_REPLACE 0x1
51 #define A5PSW_VLAN_IN_MODE_TAG_ALWAYS 0x2
53 #define A5PSW_VLAN_OUT_MODE 0x2C
55 #define A5PSW_VLAN_OUT_MODE_PORT(port) (GENMASK(1, 0) << \
57 #define A5PSW_VLAN_OUT_MODE_DIS 0x0
58 #define A5PSW_VLAN_OUT_MODE_STRIP 0x1
59 #define A5PSW_VLAN_OUT_MODE_TAG_THROUGH 0x2
60 #define A5PSW_VLAN_OUT_MODE_TRANSPARENT 0x3
62 #define A5PSW_VLAN_IN_MODE_ENA 0x30
63 #define A5PSW_VLAN_TAG_ID 0x34
65 #define A5PSW_SYSTEM_TAGINFO(port) (0x200 + 4 * (port))
67 #define A5PSW_AUTH_PORT(port) (0x240 + 4 * (port))
68 #define A5PSW_AUTH_PORT_AUTHORIZED BIT(0)
70 #define A5PSW_VLAN_RES(entry) (0x280 + 4 * (entry))
75 #define A5PSW_VLAN_RES_PORTMASK GENMASK(4, 0)
77 #define A5PSW_RXMATCH_CONFIG(port) (0x3e80 + 4 * (port))
80 #define A5PSW_PATTERN_CTRL(p) (0x3eb0 + 4 * (p))
83 #define A5PSW_LK_CTRL 0x400
84 #define A5PSW_LK_ADDR_CTRL_BLOCKING BIT(0)
90 #define A5PSW_LK_ADDR_CTRL 0x408
98 #define A5PSW_LK_ADDR_CTRL_ADDRESS GENMASK(12, 0)
100 #define A5PSW_LK_DATA_LO 0x40C
101 #define A5PSW_LK_DATA_HI 0x410
105 #define A5PSW_LK_LEARNCOUNT 0x418
106 #define A5PSW_LK_LEARNCOUNT_COUNT GENMASK(13, 0)
108 #define A5PSW_LK_LEARNCOUNT_MODE_SET 0x0
109 #define A5PSW_LK_LEARNCOUNT_MODE_INC 0x1
110 #define A5PSW_LK_LEARNCOUNT_MODE_DEC 0x2
112 #define A5PSW_MGMT_TAG_CFG 0x480
115 #define A5PSW_MGMT_TAG_CFG_ENABLE BIT(0)
117 #define A5PSW_LK_AGETIME 0x41C
118 #define A5PSW_LK_AGETIME_MASK GENMASK(23, 0)
120 #define A5PSW_MDIO_CFG_STATUS 0x700
123 #define A5PSW_MDIO_CFG_STATUS_BUSY BIT(0)
125 #define A5PSW_MDIO_COMMAND 0x704
129 #define A5PSW_MDIO_COMMAND_REG_ADDR GENMASK(4, 0)
131 #define A5PSW_MDIO_DATA 0x708
132 #define A5PSW_MDIO_DATA_MASK GENMASK(15, 0)
134 #define A5PSW_CMD_CFG(port) (0x808 + A5PSW_PORT_OFFSET(port))
143 #define A5PSW_CMD_CFG_TX_ENA BIT(0)
145 #define A5PSW_FRM_LENGTH(port) (0x814 + A5PSW_PORT_OFFSET(port))
146 #define A5PSW_FRM_LENGTH_MASK GENMASK(13, 0)
148 #define A5PSW_STATUS(port) (0x840 + A5PSW_PORT_OFFSET(port))
150 #define A5PSW_STATS_HIWORD 0x900
153 #define A5PSW_aFramesTransmittedOK 0x868
154 #define A5PSW_aFramesReceivedOK 0x86C
155 #define A5PSW_aFrameCheckSequenceErrors 0x870
156 #define A5PSW_aAlignmentErrors 0x874
157 #define A5PSW_aOctetsTransmittedOK 0x878
158 #define A5PSW_aOctetsReceivedOK 0x87C
159 #define A5PSW_aTxPAUSEMACCtrlFrames 0x880
160 #define A5PSW_aRxPAUSEMACCtrlFrames 0x884
162 #define A5PSW_ifInErrors 0x888
163 #define A5PSW_ifOutErrors 0x88C
164 #define A5PSW_ifInUcastPkts 0x890
165 #define A5PSW_ifInMulticastPkts 0x894
166 #define A5PSW_ifInBroadcastPkts 0x898
167 #define A5PSW_ifOutDiscards 0x89C
168 #define A5PSW_ifOutUcastPkts 0x8A0
169 #define A5PSW_ifOutMulticastPkts 0x8A4
170 #define A5PSW_ifOutBroadcastPkts 0x8A8
172 #define A5PSW_etherStatsDropEvents 0x8AC
173 #define A5PSW_etherStatsOctets 0x8B0
174 #define A5PSW_etherStatsPkts 0x8B4
175 #define A5PSW_etherStatsUndersizePkts 0x8B8
176 #define A5PSW_etherStatsOversizePkts 0x8BC
177 #define A5PSW_etherStatsPkts64Octets 0x8C0
178 #define A5PSW_etherStatsPkts65to127Octets 0x8C4
179 #define A5PSW_etherStatsPkts128to255Octets 0x8C8
180 #define A5PSW_etherStatsPkts256to511Octets 0x8CC
181 #define A5PSW_etherStatsPkts512to1023Octets 0x8D0
182 #define A5PSW_etherStatsPkts1024to1518Octets 0x8D4
183 #define A5PSW_etherStatsPkts1519toXOctets 0x8D8
184 #define A5PSW_etherStatsJabbers 0x8DC
185 #define A5PSW_etherStatsFragments 0x8E0
187 #define A5PSW_VLANReceived 0x8E8
188 #define A5PSW_VLANTransmitted 0x8EC
190 #define A5PSW_aDeferred 0x910
191 #define A5PSW_aMultipleCollisions 0x914
192 #define A5PSW_aSingleCollisions 0x918
193 #define A5PSW_aLateCollisions 0x91C
194 #define A5PSW_aExcessiveCollisions 0x920
195 #define A5PSW_aCarrierSenseErrors 0x924
211 #define A5PSW_PATTERN_MGMTFWD 0