Lines Matching refs:a5psw_reg_rmw
81 static void a5psw_reg_rmw(struct a5psw *a5psw, int offset, u32 mask, u32 val) in a5psw_reg_rmw() function
110 a5psw_reg_rmw(a5psw, A5PSW_RXMATCH_CONFIG(port), in a5psw_port_pattern_set()
136 a5psw_reg_rmw(a5psw, A5PSW_PORT_ENA, mask, reg); in a5psw_port_tx_enable()
146 a5psw_reg_rmw(a5psw, A5PSW_PORT_ENA, A5PSW_PORT_ENA_TX_RX(port), in a5psw_port_enable_set()
316 a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN, mask, reg); in a5psw_port_learning_set()
324 a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN, mask, reg); in a5psw_port_rx_block_set()
335 a5psw_reg_rmw(a5psw, offsets[i], BIT(port), in a5psw_flooding_set_resolution()
414 a5psw_reg_rmw(a5psw, A5PSW_INPUT_LEARN, in a5psw_port_bridge_flags()
420 a5psw_reg_rmw(a5psw, A5PSW_UCAST_DEF_MASK, BIT(port), val); in a5psw_port_bridge_flags()
425 a5psw_reg_rmw(a5psw, A5PSW_MCAST_DEF_MASK, BIT(port), val); in a5psw_port_bridge_flags()
430 a5psw_reg_rmw(a5psw, A5PSW_BCAST_DEF_MASK, BIT(port), val); in a5psw_port_bridge_flags()
652 a5psw_reg_rmw(a5psw, A5PSW_VLAN_IN_MODE_ENA, BIT(port), in a5psw_port_vlan_filtering()
656 a5psw_reg_rmw(a5psw, A5PSW_VLAN_VERIFY, mask, val); in a5psw_port_vlan_filtering()
725 a5psw_reg_rmw(a5psw, A5PSW_VLAN_RES(vlan_res_id), mask, reg); in a5psw_port_vlan_cfg()
902 a5psw_reg_rmw(a5psw, A5PSW_VLAN_IN_MODE, A5PSW_VLAN_IN_MODE_PORT(port), in a5psw_vlan_setup()
910 a5psw_reg_rmw(a5psw, A5PSW_VLAN_OUT_MODE, in a5psw_vlan_setup()