Lines Matching +full:realtek +full:- +full:smi
1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8366RB ethernet switch
9 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
24 #include "realtek.h"
46 /* Switch per-port learning disablement register */
164 * VID such as untagged or priority-tagged frames for respective
167 * a C-tag with VID != 0 for respective port.
364 * struct rtl8366rb - RTL8366RB-specific data
365 * @max_mtu: per-port max MTU setting
420 mib->offset; in rtl8366rb_get_mib_counter()
425 ret = regmap_write(priv->map, addr, 0); /* Write whatever */ in rtl8366rb_get_mib_counter()
430 ret = regmap_read(priv->map, RTL8366RB_MIB_CTRL_REG, &val); in rtl8366rb_get_mib_counter()
432 return -EIO; in rtl8366rb_get_mib_counter()
435 return -EBUSY; in rtl8366rb_get_mib_counter()
438 return -EIO; in rtl8366rb_get_mib_counter()
442 for (i = mib->length; i > 0; i--) { in rtl8366rb_get_mib_counter()
443 ret = regmap_read(priv->map, addr + (i - 1), &val); in rtl8366rb_get_mib_counter()
471 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG, in rtl8366rb_mask_irq()
474 dev_err(priv->dev, "could not mask IRQ\n"); in rtl8366rb_mask_irq()
482 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_MASK_REG, in rtl8366rb_unmask_irq()
486 dev_err(priv->dev, "could not unmask IRQ\n"); in rtl8366rb_unmask_irq()
496 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG, in rtl8366rb_irq()
499 dev_err(priv->dev, "can't read interrupt status\n"); in rtl8366rb_irq()
514 line -= 5; in rtl8366rb_irq()
515 child_irq = irq_find_mapping(priv->irqdomain, line); in rtl8366rb_irq()
530 irq_set_chip_data(irq, domain->host_data); in rtl8366rb_irq_map()
560 intc = of_get_child_by_name(priv->dev->of_node, "interrupt-controller"); in rtl8366rb_setup_cascaded_irq()
562 dev_err(priv->dev, "missing child interrupt-controller node\n"); in rtl8366rb_setup_cascaded_irq()
563 return -EINVAL; in rtl8366rb_setup_cascaded_irq()
568 dev_err(priv->dev, "failed to get parent IRQ\n"); in rtl8366rb_setup_cascaded_irq()
569 ret = irq ? irq : -EINVAL; in rtl8366rb_setup_cascaded_irq()
574 ret = regmap_read(priv->map, RTL8366RB_INTERRUPT_STATUS_REG, in rtl8366rb_setup_cascaded_irq()
577 dev_err(priv->dev, "can't read interrupt status\n"); in rtl8366rb_setup_cascaded_irq()
586 dev_info(priv->dev, "active high/rising IRQ\n"); in rtl8366rb_setup_cascaded_irq()
591 dev_info(priv->dev, "active low/falling IRQ\n"); in rtl8366rb_setup_cascaded_irq()
595 ret = regmap_update_bits(priv->map, RTL8366RB_INTERRUPT_CONTROL_REG, in rtl8366rb_setup_cascaded_irq()
599 dev_err(priv->dev, "could not configure IRQ polarity\n"); in rtl8366rb_setup_cascaded_irq()
603 ret = devm_request_threaded_irq(priv->dev, irq, NULL, in rtl8366rb_setup_cascaded_irq()
607 dev_err(priv->dev, "unable to request irq: %d\n", ret); in rtl8366rb_setup_cascaded_irq()
610 priv->irqdomain = irq_domain_add_linear(intc, in rtl8366rb_setup_cascaded_irq()
614 if (!priv->irqdomain) { in rtl8366rb_setup_cascaded_irq()
615 dev_err(priv->dev, "failed to create IRQ domain\n"); in rtl8366rb_setup_cascaded_irq()
616 ret = -EINVAL; in rtl8366rb_setup_cascaded_irq()
619 for (i = 0; i < priv->num_ports; i++) in rtl8366rb_setup_cascaded_irq()
620 irq_set_parent(irq_create_mapping(priv->irqdomain, i), irq); in rtl8366rb_setup_cascaded_irq()
635 dev_info(priv->dev, "set MAC: %02X:%02X:%02X:%02X:%02X:%02X\n", in rtl8366rb_set_addr()
638 ret = regmap_write(priv->map, RTL8366RB_SMAR0, val); in rtl8366rb_set_addr()
642 ret = regmap_write(priv->map, RTL8366RB_SMAR1, val); in rtl8366rb_set_addr()
646 ret = regmap_write(priv->map, RTL8366RB_SMAR2, val); in rtl8366rb_set_addr()
694 /* This v1 init sequence is from Belkin F5D8235 U-Boot release */
709 /* This v2 init sequence is from Belkin F5D8235 U-Boot release */
745 /* Belkin F5D8235 v1, "belkin,f5d8235-v1" */
787 ret = regmap_read(priv->map, in rtl8366rb_jam_table()
793 ret = regmap_write(priv->map, in rtl8366rb_jam_table()
801 dev_dbg(priv->dev, "jam %04x into register %04x\n", in rtl8366rb_jam_table()
804 ret = regmap_write(priv->map, in rtl8366rb_jam_table()
815 struct realtek_priv *priv = ds->priv; in rtl8366rb_setup()
825 rb = priv->chip_data; in rtl8366rb_setup()
827 ret = regmap_read(priv->map, RTL8366RB_CHIP_ID_REG, &chip_id); in rtl8366rb_setup()
829 dev_err(priv->dev, "unable to read chip id\n"); in rtl8366rb_setup()
837 dev_err(priv->dev, "unknown chip id (%04x)\n", chip_id); in rtl8366rb_setup()
838 return -ENODEV; in rtl8366rb_setup()
841 ret = regmap_read(priv->map, RTL8366RB_CHIP_VERSION_CTRL_REG, in rtl8366rb_setup()
844 dev_err(priv->dev, "unable to read chip version\n"); in rtl8366rb_setup()
848 dev_info(priv->dev, "RTL%04x ver %u chip found\n", in rtl8366rb_setup()
873 * without them, using just the off-the-shelf tables. in rtl8366rb_setup()
875 if (of_machine_is_compatible("belkin,f5d8235-v1")) { in rtl8366rb_setup()
891 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(i), in rtl8366rb_setup()
898 ret = regmap_write(priv->map, RTL8366RB_PORT_ISO(RTL8366RB_PORT_NUM_CPU), in rtl8366rb_setup()
910 ret = regmap_write(priv->map, in rtl8366rb_setup()
917 ret = regmap_write(priv->map, 0x0c, 0x240); in rtl8366rb_setup()
920 ret = regmap_write(priv->map, 0x0d, 0x240); in rtl8366rb_setup()
934 ret = regmap_update_bits(priv->map, RTL8368RB_CPU_CTRL_REG, in rtl8366rb_setup()
936 BIT(priv->cpu_port)); in rtl8366rb_setup()
940 /* Make sure we default-enable the fixed CPU port */ in rtl8366rb_setup()
941 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, in rtl8366rb_setup()
942 BIT(priv->cpu_port), in rtl8366rb_setup()
948 ret = regmap_update_bits(priv->map, RTL8366RB_SGCR, in rtl8366rb_setup()
955 rb->max_mtu[i] = 1532; in rtl8366rb_setup()
958 ret = regmap_write(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL, in rtl8366rb_setup()
964 ret = regmap_write(priv->map, RTL8366RB_SECURITY_CTRL, 0); in rtl8366rb_setup()
971 * IO modes in the Realtek source code, if your WAN port is in rtl8366rb_setup()
975 ret = regmap_update_bits(priv->map, RTL8366RB_PMC0, in rtl8366rb_setup()
981 /* Accept all packets by default, we enable filtering on-demand */ in rtl8366rb_setup()
982 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG, in rtl8366rb_setup()
986 ret = regmap_write(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG, in rtl8366rb_setup()
992 ret = regmap_update_bits(priv->map, RTL8366RB_SSCR2, in rtl8366rb_setup()
998 ret = regmap_update_bits(priv->map, RTL8366RB_LED_BLINKRATE_REG, in rtl8366rb_setup()
1009 if (priv->leds_disabled) { in rtl8366rb_setup()
1011 regmap_update_bits(priv->map, in rtl8366rb_setup()
1018 ret = regmap_update_bits(priv->map, in rtl8366rb_setup()
1033 dev_info(priv->dev, "no interrupt support\n"); in rtl8366rb_setup()
1035 if (priv->setup_interface) { in rtl8366rb_setup()
1036 ret = priv->setup_interface(ds); in rtl8366rb_setup()
1038 dev_err(priv->dev, "could not set up MDIO bus\n"); in rtl8366rb_setup()
1039 return -ENODEV; in rtl8366rb_setup()
1050 /* This switch uses the 4 byte protocol A Realtek DSA tag */ in rtl8366_get_tag_protocol()
1057 unsigned long *interfaces = config->supported_interfaces; in rtl8366rb_phylink_get_caps()
1058 struct realtek_priv *priv = ds->priv; in rtl8366rb_phylink_get_caps()
1060 if (port == priv->cpu_port) { in rtl8366rb_phylink_get_caps()
1068 config->mac_capabilities = MAC_1000 | MAC_100 | in rtl8366rb_phylink_get_caps()
1075 config->mac_capabilities = MAC_1000 | MAC_100 | MAC_10 | in rtl8366rb_phylink_get_caps()
1085 struct realtek_priv *priv = ds->priv; in rtl8366rb_mac_link_up()
1088 if (port != priv->cpu_port) in rtl8366rb_mac_link_up()
1091 dev_dbg(priv->dev, "MAC link up on CPU port (%d)\n", port); in rtl8366rb_mac_link_up()
1094 ret = regmap_update_bits(priv->map, RTL8366RB_MAC_FORCE_CTRL_REG, in rtl8366rb_mac_link_up()
1097 dev_err(priv->dev, "failed to force 1Gbit on CPU port\n"); in rtl8366rb_mac_link_up()
1101 ret = regmap_update_bits(priv->map, RTL8366RB_PAACR2, in rtl8366rb_mac_link_up()
1105 dev_err(priv->dev, "failed to set PAACR on CPU port\n"); in rtl8366rb_mac_link_up()
1110 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), in rtl8366rb_mac_link_up()
1113 dev_err(priv->dev, "failed to enable the CPU port\n"); in rtl8366rb_mac_link_up()
1122 struct realtek_priv *priv = ds->priv; in rtl8366rb_mac_link_down()
1125 if (port != priv->cpu_port) in rtl8366rb_mac_link_down()
1128 dev_dbg(priv->dev, "MAC link down on CPU port (%d)\n", port); in rtl8366rb_mac_link_down()
1131 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), in rtl8366rb_mac_link_down()
1134 dev_err(priv->dev, "failed to disable the CPU port\n"); in rtl8366rb_mac_link_down()
1143 struct realtek_priv *priv = ds->priv; in rtl8366rb_port_enable()
1146 dev_dbg(priv->dev, "enable port %d\n", port); in rtl8366rb_port_enable()
1147 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), in rtl8366rb_port_enable()
1158 struct realtek_priv *priv = ds->priv; in rtl8366rb_port_disable()
1161 dev_dbg(priv->dev, "disable port %d\n", port); in rtl8366rb_port_disable()
1162 ret = regmap_update_bits(priv->map, RTL8366RB_PECR, BIT(port), in rtl8366rb_port_disable()
1174 struct realtek_priv *priv = ds->priv; in rtl8366rb_port_bridge_join()
1187 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i), in rtl8366rb_port_bridge_join()
1191 dev_err(priv->dev, "failed to join port %d\n", port); in rtl8366rb_port_bridge_join()
1197 return regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port), in rtl8366rb_port_bridge_join()
1206 struct realtek_priv *priv = ds->priv; in rtl8366rb_port_bridge_leave()
1219 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(i), in rtl8366rb_port_bridge_leave()
1222 dev_err(priv->dev, "failed to leave port %d\n", port); in rtl8366rb_port_bridge_leave()
1228 regmap_update_bits(priv->map, RTL8366RB_PORT_ISO(port), in rtl8366rb_port_bridge_leave()
1233 * rtl8366rb_drop_untagged() - make the switch drop untagged and C-tagged frames
1234 * @priv: SMI state container
1235 * @port: the port to drop untagged and C-tagged frames on
1236 * @drop: whether to drop or pass untagged and C-tagged frames
1242 return regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL1_REG, in rtl8366rb_drop_untagged()
1251 struct realtek_priv *priv = ds->priv; in rtl8366rb_vlan_filtering()
1255 rb = priv->chip_data; in rtl8366rb_vlan_filtering()
1257 dev_dbg(priv->dev, "port %d: %s VLAN filtering\n", port, in rtl8366rb_vlan_filtering()
1261 ret = regmap_update_bits(priv->map, RTL8366RB_VLAN_INGRESS_CTRL2_REG, in rtl8366rb_vlan_filtering()
1267 * not drop any untagged or C-tagged frames. If we turn off VLAN in rtl8366rb_vlan_filtering()
1271 ret = rtl8366rb_drop_untagged(priv, port, !rb->pvid_enabled[port]); in rtl8366rb_vlan_filtering()
1285 return -EINVAL; in rtl8366rb_port_pre_bridge_flags()
1295 struct realtek_priv *priv = ds->priv; in rtl8366rb_port_bridge_flags()
1299 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_LEARNDIS_CTRL, in rtl8366rb_port_bridge_flags()
1312 struct realtek_priv *priv = ds->priv; in rtl8366rb_port_stp_state_set()
1331 dev_err(priv->dev, "unknown bridge state requested\n"); in rtl8366rb_port_stp_state_set()
1337 regmap_update_bits(priv->map, RTL8366RB_STP_STATE_BASE + i, in rtl8366rb_port_stp_state_set()
1346 struct realtek_priv *priv = ds->priv; in rtl8366rb_port_fast_age()
1349 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL, in rtl8366rb_port_fast_age()
1352 regmap_update_bits(priv->map, RTL8366RB_SECURITY_CTRL, in rtl8366rb_port_fast_age()
1358 struct realtek_priv *priv = ds->priv; in rtl8366rb_change_mtu()
1364 /* Cache the per-port MTU setting */ in rtl8366rb_change_mtu()
1365 rb = priv->chip_data; in rtl8366rb_change_mtu()
1366 rb->max_mtu[port] = new_mtu; in rtl8366rb_change_mtu()
1381 if (rb->max_mtu[i] > max_mtu) in rtl8366rb_change_mtu()
1382 max_mtu = rb->max_mtu[i]; in rtl8366rb_change_mtu()
1393 return regmap_update_bits(priv->map, RTL8366RB_SGCR, in rtl8366rb_change_mtu()
1416 return -EINVAL; in rtl8366rb_get_vlan_4k()
1419 ret = regmap_write(priv->map, RTL8366RB_VLAN_TABLE_WRITE_BASE, in rtl8366rb_get_vlan_4k()
1425 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG, in rtl8366rb_get_vlan_4k()
1431 ret = regmap_read(priv->map, in rtl8366rb_get_vlan_4k()
1438 vlan4k->vid = vid; in rtl8366rb_get_vlan_4k()
1439 vlan4k->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) & in rtl8366rb_get_vlan_4k()
1441 vlan4k->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK; in rtl8366rb_get_vlan_4k()
1442 vlan4k->fid = data[2] & RTL8366RB_VLAN_FID_MASK; in rtl8366rb_get_vlan_4k()
1454 if (vlan4k->vid >= RTL8366RB_NUM_VIDS || in rtl8366rb_set_vlan_4k()
1455 vlan4k->member > RTL8366RB_VLAN_MEMBER_MASK || in rtl8366rb_set_vlan_4k()
1456 vlan4k->untag > RTL8366RB_VLAN_UNTAG_MASK || in rtl8366rb_set_vlan_4k()
1457 vlan4k->fid > RTL8366RB_FIDMAX) in rtl8366rb_set_vlan_4k()
1458 return -EINVAL; in rtl8366rb_set_vlan_4k()
1460 data[0] = vlan4k->vid & RTL8366RB_VLAN_VID_MASK; in rtl8366rb_set_vlan_4k()
1461 data[1] = (vlan4k->member & RTL8366RB_VLAN_MEMBER_MASK) | in rtl8366rb_set_vlan_4k()
1462 ((vlan4k->untag & RTL8366RB_VLAN_UNTAG_MASK) << in rtl8366rb_set_vlan_4k()
1464 data[2] = vlan4k->fid & RTL8366RB_VLAN_FID_MASK; in rtl8366rb_set_vlan_4k()
1467 ret = regmap_write(priv->map, in rtl8366rb_set_vlan_4k()
1475 ret = regmap_write(priv->map, RTL8366RB_TABLE_ACCESS_CTRL_REG, in rtl8366rb_set_vlan_4k()
1491 return -EINVAL; in rtl8366rb_get_vlan_mc()
1494 ret = regmap_read(priv->map, in rtl8366rb_get_vlan_mc()
1501 vlanmc->vid = data[0] & RTL8366RB_VLAN_VID_MASK; in rtl8366rb_get_vlan_mc()
1502 vlanmc->priority = (data[0] >> RTL8366RB_VLAN_PRIORITY_SHIFT) & in rtl8366rb_get_vlan_mc()
1504 vlanmc->untag = (data[1] >> RTL8366RB_VLAN_UNTAG_SHIFT) & in rtl8366rb_get_vlan_mc()
1506 vlanmc->member = data[1] & RTL8366RB_VLAN_MEMBER_MASK; in rtl8366rb_get_vlan_mc()
1507 vlanmc->fid = data[2] & RTL8366RB_VLAN_FID_MASK; in rtl8366rb_get_vlan_mc()
1520 vlanmc->vid >= RTL8366RB_NUM_VIDS || in rtl8366rb_set_vlan_mc()
1521 vlanmc->priority > RTL8366RB_PRIORITYMAX || in rtl8366rb_set_vlan_mc()
1522 vlanmc->member > RTL8366RB_VLAN_MEMBER_MASK || in rtl8366rb_set_vlan_mc()
1523 vlanmc->untag > RTL8366RB_VLAN_UNTAG_MASK || in rtl8366rb_set_vlan_mc()
1524 vlanmc->fid > RTL8366RB_FIDMAX) in rtl8366rb_set_vlan_mc()
1525 return -EINVAL; in rtl8366rb_set_vlan_mc()
1527 data[0] = (vlanmc->vid & RTL8366RB_VLAN_VID_MASK) | in rtl8366rb_set_vlan_mc()
1528 ((vlanmc->priority & RTL8366RB_VLAN_PRIORITY_MASK) << in rtl8366rb_set_vlan_mc()
1530 data[1] = (vlanmc->member & RTL8366RB_VLAN_MEMBER_MASK) | in rtl8366rb_set_vlan_mc()
1531 ((vlanmc->untag & RTL8366RB_VLAN_UNTAG_MASK) << in rtl8366rb_set_vlan_mc()
1533 data[2] = vlanmc->fid & RTL8366RB_VLAN_FID_MASK; in rtl8366rb_set_vlan_mc()
1536 ret = regmap_write(priv->map, in rtl8366rb_set_vlan_mc()
1551 if (port >= priv->num_ports) in rtl8366rb_get_mc_index()
1552 return -EINVAL; in rtl8366rb_get_mc_index()
1554 ret = regmap_read(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port), in rtl8366rb_get_mc_index()
1571 rb = priv->chip_data; in rtl8366rb_set_mc_index()
1574 if (port >= priv->num_ports || index >= RTL8366RB_NUM_VLANS) in rtl8366rb_set_mc_index()
1575 return -EINVAL; in rtl8366rb_set_mc_index()
1577 ret = regmap_update_bits(priv->map, RTL8366RB_PORT_VLAN_CTRL_REG(port), in rtl8366rb_set_mc_index()
1585 rb->pvid_enabled[port] = pvid_enabled; in rtl8366rb_set_mc_index()
1588 * not drop any untagged or C-tagged frames. Make sure to update the in rtl8366rb_set_mc_index()
1591 if (dsa_port_is_vlan_filtering(dsa_to_port(priv->ds, port))) in rtl8366rb_set_mc_index()
1599 unsigned int max = RTL8366RB_NUM_VLANS - 1; in rtl8366rb_is_vlan_valid()
1601 if (priv->vlan4k_enabled) in rtl8366rb_is_vlan_valid()
1602 max = RTL8366RB_NUM_VIDS - 1; in rtl8366rb_is_vlan_valid()
1612 dev_dbg(priv->dev, "%s VLAN\n", enable ? "enable" : "disable"); in rtl8366rb_enable_vlan()
1613 return regmap_update_bits(priv->map, in rtl8366rb_enable_vlan()
1620 dev_dbg(priv->dev, "%s VLAN 4k\n", enable ? "enable" : "disable"); in rtl8366rb_enable_vlan4k()
1621 return regmap_update_bits(priv->map, RTL8366RB_SGCR, in rtl8366rb_enable_vlan4k()
1633 return -EINVAL; in rtl8366rb_phy_read()
1635 mutex_lock(&priv->map_lock); in rtl8366rb_phy_read()
1637 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG, in rtl8366rb_phy_read()
1644 ret = regmap_write(priv->map_nolock, reg, 0); in rtl8366rb_phy_read()
1646 dev_err(priv->dev, in rtl8366rb_phy_read()
1652 ret = regmap_read(priv->map_nolock, RTL8366RB_PHY_ACCESS_DATA_REG, in rtl8366rb_phy_read()
1659 dev_dbg(priv->dev, "read PHY%d register 0x%04x @ %08x, val <- %04x\n", in rtl8366rb_phy_read()
1663 mutex_unlock(&priv->map_lock); in rtl8366rb_phy_read()
1675 return -EINVAL; in rtl8366rb_phy_write()
1677 mutex_lock(&priv->map_lock); in rtl8366rb_phy_write()
1679 ret = regmap_write(priv->map_nolock, RTL8366RB_PHY_ACCESS_CTRL_REG, in rtl8366rb_phy_write()
1686 dev_dbg(priv->dev, "write PHY%d register 0x%04x @ %04x, val -> %04x\n", in rtl8366rb_phy_write()
1689 ret = regmap_write(priv->map_nolock, reg, val); in rtl8366rb_phy_write()
1694 mutex_unlock(&priv->map_lock); in rtl8366rb_phy_write()
1701 return rtl8366rb_phy_read(ds->priv, phy, regnum); in rtl8366rb_dsa_phy_read()
1707 return rtl8366rb_phy_write(ds->priv, phy, regnum, val); in rtl8366rb_dsa_phy_write()
1716 priv->write_reg_noack(priv, RTL8366RB_RESET_CTRL_REG, in rtl8366rb_reset_chip()
1720 ret = regmap_read(priv->map, RTL8366RB_RESET_CTRL_REG, &val); in rtl8366rb_reset_chip()
1726 } while (--timeout); in rtl8366rb_reset_chip()
1729 dev_err(priv->dev, "timeout waiting for the switch to reset\n"); in rtl8366rb_reset_chip()
1730 return -EIO; in rtl8366rb_reset_chip()
1738 struct device *dev = priv->dev; in rtl8366rb_detect()
1743 ret = regmap_read(priv->map, 0x5c, &val); in rtl8366rb_detect()
1753 return -ENODEV; in rtl8366rb_detect()
1756 priv->cpu_port = RTL8366RB_PORT_NUM_CPU; in rtl8366rb_detect()
1757 priv->num_ports = RTL8366RB_NUM_PORTS; in rtl8366rb_detect()
1758 priv->num_vlan_mc = RTL8366RB_NUM_VLANS; in rtl8366rb_detect()
1759 priv->mib_counters = rtl8366rb_mib_counters; in rtl8366rb_detect()
1760 priv->num_mib_counters = ARRAY_SIZE(rtl8366rb_mib_counters); in rtl8366rb_detect()
1763 dev_info(dev, "found an Unknown Realtek switch (id=0x%04x)\n", in rtl8366rb_detect()