Lines Matching +full:ignore +full:- +full:power +full:- +full:on +full:- +full:sel
1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
47 ret = bus->write(bus, phy_id, regnum, lo); in qca8k_mii_write_lo()
49 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_lo()
62 ret = bus->write(bus, phy_id, regnum, hi); in qca8k_mii_write_hi()
64 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_hi()
75 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_lo()
83 dev_err_ratelimited(&bus->dev, in qca8k_mii_read_lo()
95 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_hi()
103 dev_err_ratelimited(&bus->dev, in qca8k_mii_read_hi()
144 u16 *cached_page = &priv->mdio_cache.page; in qca8k_set_page()
145 struct mii_bus *bus = priv->bus; in qca8k_set_page()
151 ret = bus->write(bus, 0x18, 0, page); in qca8k_set_page()
153 dev_err_ratelimited(&bus->dev, in qca8k_set_page()
166 struct qca8k_priv *priv = ds->priv; in qca8k_rw_reg_ack_handler()
173 mgmt_eth_data = &priv->mgmt_eth_data; in qca8k_rw_reg_ack_handler()
175 command = get_unaligned_le32(&mgmt_ethhdr->command); in qca8k_rw_reg_ack_handler()
185 /* We can ignore odd value, we always round up them in the alloc function. */ in qca8k_rw_reg_ack_handler()
189 if (get_unaligned_le32(&mgmt_ethhdr->seq) == mgmt_eth_data->seq) in qca8k_rw_reg_ack_handler()
190 mgmt_eth_data->ack = true; in qca8k_rw_reg_ack_handler()
193 u32 *val = mgmt_eth_data->data; in qca8k_rw_reg_ack_handler()
195 *val = get_unaligned_le32(&mgmt_ethhdr->mdio_data); in qca8k_rw_reg_ack_handler()
201 __le32 *data2 = (__le32 *)skb->data; in qca8k_rw_reg_ack_handler()
203 len - QCA_HDR_MGMT_DATA1_LEN); in qca8k_rw_reg_ack_handler()
215 complete(&mgmt_eth_data->rw_done); in qca8k_rw_reg_ack_handler()
237 * Odd values will always return the next size on the ack packet. in qca8k_alloc_mdio_header()
245 * On the ack function we can skip the odd check as we already handle the in qca8k_alloc_mdio_header()
259 real_len--; in qca8k_alloc_mdio_header()
262 skb_set_network_header(skb, skb->len); in qca8k_alloc_mdio_header()
278 put_unaligned_le32(command, &mgmt_ethhdr->command); in qca8k_alloc_mdio_header()
281 put_unaligned_le32(*val, &mgmt_ethhdr->mdio_data); in qca8k_alloc_mdio_header()
283 mgmt_ethhdr->hdr = htons(hdr); in qca8k_alloc_mdio_header()
288 len - QCA_HDR_MGMT_DATA1_LEN); in qca8k_alloc_mdio_header()
308 mgmt_ethhdr = (struct qca_mgmt_ethhdr *)skb->data; in qca8k_mdio_header_fill_seq_num()
309 put_unaligned_le32(seq, &mgmt_ethhdr->seq); in qca8k_mdio_header_fill_seq_num()
314 struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data; in qca8k_read_eth()
322 return -ENOMEM; in qca8k_read_eth()
324 mutex_lock(&mgmt_eth_data->mutex); in qca8k_read_eth()
327 if (!priv->mgmt_master) { in qca8k_read_eth()
329 mutex_unlock(&mgmt_eth_data->mutex); in qca8k_read_eth()
330 return -EINVAL; in qca8k_read_eth()
333 skb->dev = priv->mgmt_master; in qca8k_read_eth()
335 reinit_completion(&mgmt_eth_data->rw_done); in qca8k_read_eth()
338 mgmt_eth_data->seq++; in qca8k_read_eth()
339 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); in qca8k_read_eth()
340 mgmt_eth_data->ack = false; in qca8k_read_eth()
344 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, in qca8k_read_eth()
347 *val = mgmt_eth_data->data[0]; in qca8k_read_eth()
349 memcpy(val + 1, mgmt_eth_data->data + 1, len - QCA_HDR_MGMT_DATA1_LEN); in qca8k_read_eth()
351 ack = mgmt_eth_data->ack; in qca8k_read_eth()
353 mutex_unlock(&mgmt_eth_data->mutex); in qca8k_read_eth()
356 return -ETIMEDOUT; in qca8k_read_eth()
359 return -EINVAL; in qca8k_read_eth()
366 struct qca8k_mgmt_eth_data *mgmt_eth_data = &priv->mgmt_eth_data; in qca8k_write_eth()
374 return -ENOMEM; in qca8k_write_eth()
376 mutex_lock(&mgmt_eth_data->mutex); in qca8k_write_eth()
379 if (!priv->mgmt_master) { in qca8k_write_eth()
381 mutex_unlock(&mgmt_eth_data->mutex); in qca8k_write_eth()
382 return -EINVAL; in qca8k_write_eth()
385 skb->dev = priv->mgmt_master; in qca8k_write_eth()
387 reinit_completion(&mgmt_eth_data->rw_done); in qca8k_write_eth()
390 mgmt_eth_data->seq++; in qca8k_write_eth()
391 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); in qca8k_write_eth()
392 mgmt_eth_data->ack = false; in qca8k_write_eth()
396 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, in qca8k_write_eth()
399 ack = mgmt_eth_data->ack; in qca8k_write_eth()
401 mutex_unlock(&mgmt_eth_data->mutex); in qca8k_write_eth()
404 return -ETIMEDOUT; in qca8k_write_eth()
407 return -EINVAL; in qca8k_write_eth()
431 struct mii_bus *bus = priv->bus; in qca8k_read_mii()
437 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_read_mii()
446 mutex_unlock(&bus->mdio_lock); in qca8k_read_mii()
453 struct mii_bus *bus = priv->bus; in qca8k_write_mii()
459 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_write_mii()
468 mutex_unlock(&bus->mdio_lock); in qca8k_write_mii()
476 struct mii_bus *bus = priv->bus; in qca8k_regmap_update_bits_mii()
483 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_regmap_update_bits_mii()
498 mutex_unlock(&bus->mdio_lock); in qca8k_regmap_update_bits_mii()
511 if (priv->mgmt_master && in qca8k_bulk_read()
534 if (priv->mgmt_master && in qca8k_bulk_gather_write()
554 bytes - sizeof(u16)); in qca8k_bulk_write()
572 .max_register = 0x16ac, /* end MIB - Port6 range */
595 return -ENOMEM; in qca8k_phy_eth_busy_wait()
597 reinit_completion(&mgmt_eth_data->rw_done); in qca8k_phy_eth_busy_wait()
600 mgmt_eth_data->seq++; in qca8k_phy_eth_busy_wait()
601 qca8k_mdio_header_fill_seq_num(skb, mgmt_eth_data->seq); in qca8k_phy_eth_busy_wait()
602 mgmt_eth_data->ack = false; in qca8k_phy_eth_busy_wait()
606 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, in qca8k_phy_eth_busy_wait()
609 ack = mgmt_eth_data->ack; in qca8k_phy_eth_busy_wait()
612 return -ETIMEDOUT; in qca8k_phy_eth_busy_wait()
615 return -EINVAL; in qca8k_phy_eth_busy_wait()
617 *val = mgmt_eth_data->data[0]; in qca8k_phy_eth_busy_wait()
634 return -EINVAL; in qca8k_phy_eth_command()
636 mgmt_eth_data = &priv->mgmt_eth_data; in qca8k_phy_eth_command()
653 return -ENOMEM; in qca8k_phy_eth_command()
658 ret = -ENOMEM; in qca8k_phy_eth_command()
665 ret = -ENOMEM; in qca8k_phy_eth_command()
672 * devices on the MDIO bus. in qca8k_phy_eth_command()
676 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_phy_eth_command()
684 mutex_lock(&mgmt_eth_data->mutex); in qca8k_phy_eth_command()
687 mgmt_master = priv->mgmt_master; in qca8k_phy_eth_command()
689 mutex_unlock(&mgmt_eth_data->mutex); in qca8k_phy_eth_command()
690 mutex_unlock(&priv->bus->mdio_lock); in qca8k_phy_eth_command()
691 ret = -EINVAL; in qca8k_phy_eth_command()
695 read_skb->dev = mgmt_master; in qca8k_phy_eth_command()
696 clear_skb->dev = mgmt_master; in qca8k_phy_eth_command()
697 write_skb->dev = mgmt_master; in qca8k_phy_eth_command()
699 reinit_completion(&mgmt_eth_data->rw_done); in qca8k_phy_eth_command()
702 mgmt_eth_data->seq++; in qca8k_phy_eth_command()
703 qca8k_mdio_header_fill_seq_num(write_skb, mgmt_eth_data->seq); in qca8k_phy_eth_command()
704 mgmt_eth_data->ack = false; in qca8k_phy_eth_command()
708 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, in qca8k_phy_eth_command()
711 ack = mgmt_eth_data->ack; in qca8k_phy_eth_command()
714 ret = -ETIMEDOUT; in qca8k_phy_eth_command()
720 ret = -EINVAL; in qca8k_phy_eth_command()
736 reinit_completion(&mgmt_eth_data->rw_done); in qca8k_phy_eth_command()
739 mgmt_eth_data->seq++; in qca8k_phy_eth_command()
740 qca8k_mdio_header_fill_seq_num(read_skb, mgmt_eth_data->seq); in qca8k_phy_eth_command()
741 mgmt_eth_data->ack = false; in qca8k_phy_eth_command()
745 ret = wait_for_completion_timeout(&mgmt_eth_data->rw_done, in qca8k_phy_eth_command()
748 ack = mgmt_eth_data->ack; in qca8k_phy_eth_command()
751 ret = -ETIMEDOUT; in qca8k_phy_eth_command()
756 ret = -EINVAL; in qca8k_phy_eth_command()
760 ret = mgmt_eth_data->data[0] & QCA8K_MDIO_MASTER_DATA_MASK; in qca8k_phy_eth_command()
765 reinit_completion(&mgmt_eth_data->rw_done); in qca8k_phy_eth_command()
768 mgmt_eth_data->seq++; in qca8k_phy_eth_command()
769 qca8k_mdio_header_fill_seq_num(clear_skb, mgmt_eth_data->seq); in qca8k_phy_eth_command()
770 mgmt_eth_data->ack = false; in qca8k_phy_eth_command()
774 wait_for_completion_timeout(&mgmt_eth_data->rw_done, in qca8k_phy_eth_command()
777 mutex_unlock(&mgmt_eth_data->mutex); in qca8k_phy_eth_command()
778 mutex_unlock(&priv->bus->mdio_lock); in qca8k_phy_eth_command()
807 * before returnting -ETIMEDOUT in qca8k_mdio_busy_wait()
818 struct mii_bus *bus = priv->bus; in qca8k_mdio_write()
824 return -EINVAL; in qca8k_mdio_write()
833 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_mdio_write()
848 mutex_unlock(&bus->mdio_lock); in qca8k_mdio_write()
856 struct mii_bus *bus = priv->bus; in qca8k_mdio_read()
862 return -EINVAL; in qca8k_mdio_read()
870 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); in qca8k_mdio_read()
889 mutex_unlock(&bus->mdio_lock); in qca8k_mdio_read()
900 struct qca8k_priv *priv = slave_bus->priv; in qca8k_internal_mdio_write()
903 /* Use mdio Ethernet when available, fallback to legacy one on error */ in qca8k_internal_mdio_write()
914 struct qca8k_priv *priv = slave_bus->priv; in qca8k_internal_mdio_read()
917 /* Use mdio Ethernet when available, fallback to legacy one on error */ in qca8k_internal_mdio_read()
949 struct dsa_switch *ds = priv->ds; in qca8k_mdio_register()
954 mdio = of_get_child_by_name(priv->dev->of_node, "mdio"); in qca8k_mdio_register()
956 bus = devm_mdiobus_alloc(ds->dev); in qca8k_mdio_register()
958 err = -ENOMEM; in qca8k_mdio_register()
962 bus->priv = (void *)priv; in qca8k_mdio_register()
963 snprintf(bus->id, MII_BUS_ID_SIZE, "qca8k-%d.%d", in qca8k_mdio_register()
964 ds->dst->index, ds->index); in qca8k_mdio_register()
965 bus->parent = ds->dev; in qca8k_mdio_register()
966 bus->phy_mask = ~ds->phys_mii_mask; in qca8k_mdio_register()
967 ds->slave_mii_bus = bus; in qca8k_mdio_register()
971 bus->name = "qca8k slave mii"; in qca8k_mdio_register()
972 bus->read = qca8k_internal_mdio_read; in qca8k_mdio_register()
973 bus->write = qca8k_internal_mdio_write; in qca8k_mdio_register()
974 err = devm_of_mdiobus_register(priv->dev, bus, mdio); in qca8k_mdio_register()
981 bus->name = "qca8k-legacy slave mii"; in qca8k_mdio_register()
982 bus->read = qca8k_legacy_mdio_read; in qca8k_mdio_register()
983 bus->write = qca8k_legacy_mdio_write; in qca8k_mdio_register()
985 err = devm_mdiobus_register(priv->dev, bus); in qca8k_mdio_register()
1001 ports = of_get_child_by_name(priv->dev->of_node, "ports"); in qca8k_setup_mdio_bus()
1003 ports = of_get_child_by_name(priv->dev->of_node, "ethernet-ports"); in qca8k_setup_mdio_bus()
1006 return -EINVAL; in qca8k_setup_mdio_bus()
1016 if (!dsa_is_user_port(priv->ds, reg)) in qca8k_setup_mdio_bus()
1021 if (of_property_read_bool(port, "phy-handle") && in qca8k_setup_mdio_bus()
1030 dev_err(priv->dev, "no PHYs are defined.\n"); in qca8k_setup_mdio_bus()
1031 return -EINVAL; in qca8k_setup_mdio_bus()
1040 * If the external mdio-bus driver is capable magically disabling in qca8k_setup_mdio_bus()
1041 * the QCA8K_MDIO_MASTER_EN and mutex/spin-locking out the qca8k's in qca8k_setup_mdio_bus()
1046 dev_err(priv->dev, "either internal or external mdio bus configuration is supported.\n"); in qca8k_setup_mdio_bus()
1047 return -EINVAL; in qca8k_setup_mdio_bus()
1052 * a dt-overlay and driver reload changed the configuration in qca8k_setup_mdio_bus()
1055 return regmap_clear_bits(priv->regmap, QCA8K_MDIO_MASTER_CTRL, in qca8k_setup_mdio_bus()
1091 struct qca8k_priv *priv = ds->priv; in qca8k_find_cpu_port()
1097 dev_dbg(priv->dev, "port 0 is not the CPU port. Checking port 6"); in qca8k_find_cpu_port()
1102 return -EINVAL; in qca8k_find_cpu_port()
1108 const struct qca8k_match_data *data = priv->info; in qca8k_setup_of_pws_reg()
1109 struct device_node *node = priv->dev->of_node; in qca8k_setup_of_pws_reg()
1117 if (priv->switch_id == QCA8K_ID_QCA8327) { in qca8k_setup_of_pws_reg()
1119 if (data->reduced_package) in qca8k_setup_of_pws_reg()
1128 if (of_property_read_bool(node, "qca,ignore-power-on-sel")) in qca8k_setup_of_pws_reg()
1131 if (of_property_read_bool(node, "qca,led-open-drain")) { in qca8k_setup_of_pws_reg()
1133 dev_err(priv->dev, "qca,led-open-drain require qca,ignore-power-on-sel to be set."); in qca8k_setup_of_pws_reg()
1134 return -EINVAL; in qca8k_setup_of_pws_reg()
1148 int port, cpu_port_index = -1, ret; in qca8k_parse_port_config()
1160 dp = dsa_to_port(priv->ds, port); in qca8k_parse_port_config()
1161 port_dn = dp->dn; in qca8k_parse_port_config()
1179 if (!of_property_read_u32(port_dn, "tx-internal-delay-ps", &delay)) in qca8k_parse_port_config()
1187 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value"); in qca8k_parse_port_config()
1191 priv->ports_config.rgmii_tx_delay[cpu_port_index] = delay; in qca8k_parse_port_config()
1195 if (!of_property_read_u32(port_dn, "rx-internal-delay-ps", &delay)) in qca8k_parse_port_config()
1203 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value"); in qca8k_parse_port_config()
1207 priv->ports_config.rgmii_rx_delay[cpu_port_index] = delay; in qca8k_parse_port_config()
1216 if (of_property_read_bool(port_dn, "qca,sgmii-txclk-falling-edge")) in qca8k_parse_port_config()
1217 priv->ports_config.sgmii_tx_clk_falling_edge = true; in qca8k_parse_port_config()
1219 if (of_property_read_bool(port_dn, "qca,sgmii-rxclk-falling-edge")) in qca8k_parse_port_config()
1220 priv->ports_config.sgmii_rx_clk_falling_edge = true; in qca8k_parse_port_config()
1222 if (of_property_read_bool(port_dn, "qca,sgmii-enable-pll")) { in qca8k_parse_port_config()
1223 priv->ports_config.sgmii_enable_pll = true; in qca8k_parse_port_config()
1225 if (priv->switch_id == QCA8K_ID_QCA8327) { in qca8k_parse_port_config()
1226 dev_err(priv->dev, "SGMII PLL should NOT be enabled for qca8327. Aborting enabling"); in qca8k_parse_port_config()
1227 priv->ports_config.sgmii_enable_pll = false; in qca8k_parse_port_config()
1230 if (priv->switch_revision < 2) in qca8k_parse_port_config()
1231 dev_warn(priv->dev, "SGMII PLL should NOT be enabled for qca8337 with revision 2 or more."); in qca8k_parse_port_config()
1251 * Mode to rgmii and internal-delay standard binding defined in qca8k_mac_config_setup_internal_delay()
1252 * rgmii-id or rgmii-tx/rx phy mode set. in qca8k_mac_config_setup_internal_delay()
1258 if (priv->ports_config.rgmii_tx_delay[cpu_port_index]) { in qca8k_mac_config_setup_internal_delay()
1259 delay = priv->ports_config.rgmii_tx_delay[cpu_port_index]; in qca8k_mac_config_setup_internal_delay()
1265 if (priv->ports_config.rgmii_rx_delay[cpu_port_index]) { in qca8k_mac_config_setup_internal_delay()
1266 delay = priv->ports_config.rgmii_rx_delay[cpu_port_index]; in qca8k_mac_config_setup_internal_delay()
1272 /* Set RGMII delay based on the selected values */ in qca8k_mac_config_setup_internal_delay()
1280 dev_err(priv->dev, "Failed to set internal delay for CPU port%d", in qca8k_mac_config_setup_internal_delay()
1288 struct qca8k_priv *priv = ds->priv; in qca8k_phylink_mac_select_pcs()
1296 pcs = &priv->pcs_port_0.pcs; in qca8k_phylink_mac_select_pcs()
1300 pcs = &priv->pcs_port_6.pcs; in qca8k_phylink_mac_select_pcs()
1316 struct qca8k_priv *priv = ds->priv; in qca8k_phylink_mac_config()
1322 if (state->interface != PHY_INTERFACE_MODE_RGMII && in qca8k_phylink_mac_config()
1323 state->interface != PHY_INTERFACE_MODE_RGMII_ID && in qca8k_phylink_mac_config()
1324 state->interface != PHY_INTERFACE_MODE_RGMII_TXID && in qca8k_phylink_mac_config()
1325 state->interface != PHY_INTERFACE_MODE_RGMII_RXID && in qca8k_phylink_mac_config()
1326 state->interface != PHY_INTERFACE_MODE_SGMII) in qca8k_phylink_mac_config()
1340 if (state->interface != PHY_INTERFACE_MODE_RGMII && in qca8k_phylink_mac_config()
1341 state->interface != PHY_INTERFACE_MODE_RGMII_ID && in qca8k_phylink_mac_config()
1342 state->interface != PHY_INTERFACE_MODE_RGMII_TXID && in qca8k_phylink_mac_config()
1343 state->interface != PHY_INTERFACE_MODE_RGMII_RXID && in qca8k_phylink_mac_config()
1344 state->interface != PHY_INTERFACE_MODE_SGMII && in qca8k_phylink_mac_config()
1345 state->interface != PHY_INTERFACE_MODE_1000BASEX) in qca8k_phylink_mac_config()
1352 dev_err(ds->dev, "%s: unsupported port: %i\n", __func__, port); in qca8k_phylink_mac_config()
1357 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", in qca8k_phylink_mac_config()
1362 switch (state->interface) { in qca8k_phylink_mac_config()
1376 if (priv->switch_id == QCA8K_ID_QCA8337) in qca8k_phylink_mac_config()
1382 /* Enable SGMII on the port */ in qca8k_phylink_mac_config()
1386 dev_err(ds->dev, "xMII mode %s not supported for port %d\n", in qca8k_phylink_mac_config()
1387 phy_modes(state->interface), port); in qca8k_phylink_mac_config()
1397 phy_interface_set_rgmii(config->supported_interfaces); in qca8k_phylink_get_caps()
1399 config->supported_interfaces); in qca8k_phylink_get_caps()
1409 config->supported_interfaces); in qca8k_phylink_get_caps()
1411 config->supported_interfaces); in qca8k_phylink_get_caps()
1415 phy_interface_set_rgmii(config->supported_interfaces); in qca8k_phylink_get_caps()
1417 config->supported_interfaces); in qca8k_phylink_get_caps()
1419 config->supported_interfaces); in qca8k_phylink_get_caps()
1423 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in qca8k_phylink_get_caps()
1431 struct qca8k_priv *priv = ds->priv; in qca8k_phylink_mac_link_down()
1441 struct qca8k_priv *priv = ds->priv; in qca8k_phylink_mac_link_up()
1485 struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv; in qca8k_pcs_get_state()
1486 int port = pcs_to_qca8k_pcs(pcs)->port; in qca8k_pcs_get_state()
1492 state->link = false; in qca8k_pcs_get_state()
1496 state->link = !!(reg & QCA8K_PORT_STATUS_LINK_UP); in qca8k_pcs_get_state()
1497 state->an_complete = state->link; in qca8k_pcs_get_state()
1498 state->duplex = (reg & QCA8K_PORT_STATUS_DUPLEX) ? DUPLEX_FULL : in qca8k_pcs_get_state()
1503 state->speed = SPEED_10; in qca8k_pcs_get_state()
1506 state->speed = SPEED_100; in qca8k_pcs_get_state()
1509 state->speed = SPEED_1000; in qca8k_pcs_get_state()
1512 state->speed = SPEED_UNKNOWN; in qca8k_pcs_get_state()
1517 state->pause |= MLO_PAUSE_RX; in qca8k_pcs_get_state()
1519 state->pause |= MLO_PAUSE_TX; in qca8k_pcs_get_state()
1527 struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv; in qca8k_pcs_config()
1531 port = pcs_to_qca8k_pcs(pcs)->port; in qca8k_pcs_config()
1545 return -EINVAL; in qca8k_pcs_config()
1548 /* Enable/disable SerDes auto-negotiation as necessary */ in qca8k_pcs_config()
1563 if (priv->ports_config.sgmii_enable_pll) in qca8k_pcs_config()
1567 if (dsa_is_cpu_port(priv->ds, port)) { in qca8k_pcs_config()
1589 if (priv->switch_id == QCA8K_ID_QCA8327 || in qca8k_pcs_config()
1590 priv->switch_id == QCA8K_ID_QCA8337) in qca8k_pcs_config()
1596 if (priv->ports_config.sgmii_rx_clk_falling_edge) in qca8k_pcs_config()
1599 if (priv->ports_config.sgmii_tx_clk_falling_edge) in qca8k_pcs_config()
1624 qpcs->pcs.ops = &qca8k_pcs_ops; in qca8k_setup_pcs()
1625 qpcs->pcs.neg_mode = true; in qca8k_setup_pcs()
1628 qpcs->pcs.poll = true; in qca8k_setup_pcs()
1629 qpcs->priv = priv; in qca8k_setup_pcs()
1630 qpcs->port = port; in qca8k_setup_pcs()
1636 struct qca8k_priv *priv = ds->priv; in qca8k_mib_autocast_handler()
1644 mib_eth_data = &priv->mib_eth_data; in qca8k_mib_autocast_handler()
1646 /* The switch autocast every port. Ignore other packet and in qca8k_mib_autocast_handler()
1649 port = FIELD_GET(QCA_HDR_RECV_SOURCE_PORT, ntohs(mib_ethhdr->hdr)); in qca8k_mib_autocast_handler()
1650 if (port != mib_eth_data->req_port) in qca8k_mib_autocast_handler()
1653 data2 = (__le32 *)skb->data; in qca8k_mib_autocast_handler()
1655 for (i = 0; i < priv->info->mib_count; i++) { in qca8k_mib_autocast_handler()
1660 mib_eth_data->data[i] = get_unaligned_le32(mib_ethhdr->data + i); in qca8k_mib_autocast_handler()
1665 if (mib->size == 2) in qca8k_mib_autocast_handler()
1666 mib_eth_data->data[i] = get_unaligned_le64((__le64 *)data2); in qca8k_mib_autocast_handler()
1668 mib_eth_data->data[i] = get_unaligned_le32(data2); in qca8k_mib_autocast_handler()
1670 data2 += mib->size; in qca8k_mib_autocast_handler()
1674 /* Complete on receiving all the mib packet */ in qca8k_mib_autocast_handler()
1675 if (refcount_dec_and_test(&mib_eth_data->port_parsed)) in qca8k_mib_autocast_handler()
1676 complete(&mib_eth_data->rw_done); in qca8k_mib_autocast_handler()
1684 struct qca8k_priv *priv = ds->priv; in qca8k_get_ethtool_stats_eth()
1687 mib_eth_data = &priv->mib_eth_data; in qca8k_get_ethtool_stats_eth()
1689 mutex_lock(&mib_eth_data->mutex); in qca8k_get_ethtool_stats_eth()
1691 reinit_completion(&mib_eth_data->rw_done); in qca8k_get_ethtool_stats_eth()
1693 mib_eth_data->req_port = dp->index; in qca8k_get_ethtool_stats_eth()
1694 mib_eth_data->data = data; in qca8k_get_ethtool_stats_eth()
1695 refcount_set(&mib_eth_data->port_parsed, QCA8K_NUM_PORTS); in qca8k_get_ethtool_stats_eth()
1697 mutex_lock(&priv->reg_mutex); in qca8k_get_ethtool_stats_eth()
1700 ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB, in qca8k_get_ethtool_stats_eth()
1705 mutex_unlock(&priv->reg_mutex); in qca8k_get_ethtool_stats_eth()
1710 ret = wait_for_completion_timeout(&mib_eth_data->rw_done, QCA8K_ETHERNET_TIMEOUT); in qca8k_get_ethtool_stats_eth()
1713 mutex_unlock(&mib_eth_data->mutex); in qca8k_get_ethtool_stats_eth()
1720 struct qca8k_priv *priv = ds->priv; in qca8k_get_phy_flags()
1723 * Based on the switch revision different values needs to be in qca8k_get_phy_flags()
1724 * set to the dbg and mmd reg on the phy. in qca8k_get_phy_flags()
1729 return priv->switch_revision; in qca8k_get_phy_flags()
1745 struct dsa_port *dp = master->dsa_ptr; in qca8k_master_change()
1746 struct qca8k_priv *priv = ds->priv; in qca8k_master_change()
1749 if (dp->index != 0) in qca8k_master_change()
1752 mutex_lock(&priv->mgmt_eth_data.mutex); in qca8k_master_change()
1753 mutex_lock(&priv->mib_eth_data.mutex); in qca8k_master_change()
1755 priv->mgmt_master = operational ? (struct net_device *)master : NULL; in qca8k_master_change()
1757 mutex_unlock(&priv->mib_eth_data.mutex); in qca8k_master_change()
1758 mutex_unlock(&priv->mgmt_eth_data.mutex); in qca8k_master_change()
1768 tagger_data = ds->tagger_data; in qca8k_connect_tag_protocol()
1770 tagger_data->rw_reg_ack_handler = qca8k_rw_reg_ack_handler; in qca8k_connect_tag_protocol()
1771 tagger_data->mib_autocast_handler = qca8k_mib_autocast_handler; in qca8k_connect_tag_protocol()
1775 return -EOPNOTSUPP; in qca8k_connect_tag_protocol()
1807 regmap_write(priv->regmap, QCA8K_REG_PORT_HOL_CTRL0(port), mask); in qca8k_setup_hol_fixup()
1813 regmap_update_bits(priv->regmap, QCA8K_REG_PORT_HOL_CTRL1(port), in qca8k_setup_hol_fixup()
1824 struct qca8k_priv *priv = ds->priv; in qca8k_setup()
1831 dev_err(priv->dev, "No cpu port configured in both cpu port0 and port6"); in qca8k_setup()
1856 qca8k_setup_pcs(priv, &priv->pcs_port_0, 0); in qca8k_setup()
1857 qca8k_setup_pcs(priv, &priv->pcs_port_6, 6); in qca8k_setup()
1860 ret = regmap_clear_bits(priv->regmap, QCA8K_REG_PORT0_PAD_CTRL, in qca8k_setup()
1863 dev_err(priv->dev, "failed disabling MAC06 exchange"); in qca8k_setup()
1868 ret = regmap_set_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, in qca8k_setup()
1871 dev_err(priv->dev, "failed enabling CPU port"); in qca8k_setup()
1878 dev_warn(priv->dev, "mib init failed"); in qca8k_setup()
1882 /* Disable forwarding by default on all ports */ in qca8k_setup()
1883 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(dp->index), in qca8k_setup()
1889 /* Disable MAC by default on all user ports */ in qca8k_setup()
1891 qca8k_port_set_status(priv, dp->index, 0); in qca8k_setup()
1893 /* Enable QCA header mode on all cpu ports */ in qca8k_setup()
1895 ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(dp->index), in qca8k_setup()
1899 dev_err(priv->dev, "failed enabling QCA header mode on port %d", dp->index); in qca8k_setup()
1905 * Notice that in multi-cpu config only one port should be set in qca8k_setup()
1926 u8 port = dp->index; in qca8k_setup()
1934 ret = regmap_clear_bits(priv->regmap, QCA8K_PORT_LOOKUP_CTRL(port), in qca8k_setup()
1961 if (priv->switch_id == QCA8K_ID_QCA8337) in qca8k_setup()
1963 qca8k_setup_hol_fixup(priv, dp->index); in qca8k_setup()
1966 if (priv->switch_id == QCA8K_ID_QCA8327) { in qca8k_setup()
1975 /* Setup our port MTUs to match power on defaults */ in qca8k_setup()
1978 dev_warn(priv->dev, "failed setting MTU settings"); in qca8k_setup()
1984 ds->ageing_time_min = 7000; in qca8k_setup()
1985 ds->ageing_time_max = 458745000; in qca8k_setup()
1988 ds->num_lag_ids = QCA8K_NUM_LAGS; in qca8k_setup()
2043 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); in qca8k_sw_probe()
2045 return -ENOMEM; in qca8k_sw_probe()
2047 priv->bus = mdiodev->bus; in qca8k_sw_probe()
2048 priv->dev = &mdiodev->dev; in qca8k_sw_probe()
2049 priv->info = of_device_get_match_data(priv->dev); in qca8k_sw_probe()
2051 priv->reset_gpio = devm_gpiod_get_optional(priv->dev, "reset", in qca8k_sw_probe()
2053 if (IS_ERR(priv->reset_gpio)) in qca8k_sw_probe()
2054 return PTR_ERR(priv->reset_gpio); in qca8k_sw_probe()
2056 if (priv->reset_gpio) { in qca8k_sw_probe()
2061 gpiod_set_value_cansleep(priv->reset_gpio, 0); in qca8k_sw_probe()
2065 priv->regmap = devm_regmap_init(&mdiodev->dev, NULL, priv, in qca8k_sw_probe()
2067 if (IS_ERR(priv->regmap)) { in qca8k_sw_probe()
2068 dev_err(priv->dev, "regmap initialization failed"); in qca8k_sw_probe()
2069 return PTR_ERR(priv->regmap); in qca8k_sw_probe()
2072 priv->mdio_cache.page = 0xffff; in qca8k_sw_probe()
2079 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); in qca8k_sw_probe()
2080 if (!priv->ds) in qca8k_sw_probe()
2081 return -ENOMEM; in qca8k_sw_probe()
2083 mutex_init(&priv->mgmt_eth_data.mutex); in qca8k_sw_probe()
2084 init_completion(&priv->mgmt_eth_data.rw_done); in qca8k_sw_probe()
2086 mutex_init(&priv->mib_eth_data.mutex); in qca8k_sw_probe()
2087 init_completion(&priv->mib_eth_data.rw_done); in qca8k_sw_probe()
2089 priv->ds->dev = &mdiodev->dev; in qca8k_sw_probe()
2090 priv->ds->num_ports = QCA8K_NUM_PORTS; in qca8k_sw_probe()
2091 priv->ds->priv = priv; in qca8k_sw_probe()
2092 priv->ds->ops = &qca8k_switch_ops; in qca8k_sw_probe()
2093 mutex_init(&priv->reg_mutex); in qca8k_sw_probe()
2094 dev_set_drvdata(&mdiodev->dev, priv); in qca8k_sw_probe()
2096 return dsa_register_switch(priv->ds); in qca8k_sw_probe()
2102 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev); in qca8k_sw_remove()
2111 dsa_unregister_switch(priv->ds); in qca8k_sw_remove()
2116 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev); in qca8k_sw_shutdown()
2121 dsa_switch_shutdown(priv->ds); in qca8k_sw_shutdown()
2123 dev_set_drvdata(&mdiodev->dev, NULL); in qca8k_sw_shutdown()
2133 /* Do not enable on resume if the port was in qca8k_set_pm()
2136 if (!(priv->port_enabled_map & BIT(port))) in qca8k_set_pm()
2149 return dsa_switch_suspend(priv->ds); in qca8k_suspend()
2158 return dsa_switch_resume(priv->ds); in qca8k_resume()