Lines Matching +full:6 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2017-2024 Microchip Technology Inc.
14 /* 0 - Operation */
43 #define PME_ENABLE BIT(1)
44 #define PME_POLARITY BIT(0)
48 #define SW_GIGABIT_ABLE BIT(6)
49 #define SW_REDUNDANCY_ABLE BIT(5)
50 #define SW_AVB_ABLE BIT(4)
68 #define SW_QW_ABLE BIT(5)
74 #define LUE_INT BIT(31)
75 #define TRIG_TS_INT BIT(30)
76 #define APB_TIMEOUT_INT BIT(29)
85 /* 1 - Global */
87 #define SW_SPARE_REG_2 BIT(7)
88 #define SW_SPARE_REG_1 BIT(6)
89 #define SW_SPARE_REG_0 BIT(5)
90 #define SW_BIG_ENDIAN BIT(4)
91 #define SPI_AUTO_EDGE_DETECTION BIT(1)
92 #define SPI_CLOCK_OUT_RISING_EDGE BIT(0)
95 #define SW_ENABLE_REFCLKO BIT(1)
96 #define SW_REFCLKO_IS_125MHZ BIT(0)
100 #define SW_IBA_ENABLE BIT(31)
101 #define SW_IBA_DA_MATCH BIT(30)
102 #define SW_IBA_INIT BIT(29)
111 #define APB_TIMEOUT_ACKNOWLEDGE BIT(31)
123 #define SW_DRIVE_STRENGTH_24MA 6
130 #define SW_IBA_REQ BIT(31)
131 #define SW_IBA_RESP BIT(30)
132 #define SW_IBA_DA_MISMATCH BIT(14)
133 #define SW_IBA_FMT_MISMATCH BIT(13)
134 #define SW_IBA_CODE_ERROR BIT(12)
135 #define SW_IBA_CMD_ERROR BIT(11)
136 #define SW_IBA_CMD_LOC_M (BIT(6) - 1)
152 #define SW_IBA_RETRY_CNT_M (BIT(5) - 1)
154 /* 2 - PHY */
157 #define SW_PLL_POWER_DOWN BIT(5)
163 /* 3 - Operation Control */
166 #define SW_DOUBLE_TAG BIT(7)
167 #define SW_RESET BIT(1)
185 #define SW_SHAPING_CREDIT_ACCT BIT(1)
186 #define SW_POLICING_CREDIT_ACCT BIT(0)
190 #define SW_VLAN_ENABLE BIT(7)
191 #define SW_DROP_INVALID_VID BIT(6)
193 #define SW_RESV_MCAST_ENABLE BIT(2)
201 #define UNICAST_LEARN_DISABLE BIT(7)
202 #define SW_SRC_ADDR_FILTER BIT(6)
203 #define SW_FLUSH_STP_TABLE BIT(5)
204 #define SW_FLUSH_MSTP_TABLE BIT(4)
205 #define SW_FWD_MCAST_SRC_ADDR BIT(3)
206 #define SW_AGING_ENABLE BIT(2)
207 #define SW_FAST_AGING BIT(1)
208 #define SW_LINK_AUTO_AGING BIT(0)
212 #define SW_TRAP_DOUBLE_TAG BIT(6)
213 #define SW_EGRESS_VLAN_FILTER_DYN BIT(5)
214 #define SW_EGRESS_VLAN_FILTER_STA BIT(4)
232 #define LEARN_FAIL_INT BIT(2)
233 #define ALMOST_FULL_INT BIT(1)
234 #define WRITE_FAIL_INT BIT(0)
248 #define SW_UNK_UCAST_ENABLE BIT(31)
252 #define SW_UNK_MCAST_ENABLE BIT(31)
256 #define SW_UNK_VID_ENABLE BIT(31)
260 #define SW_NEW_BACKOFF BIT(7)
261 #define SW_CHECK_LENGTH BIT(3)
262 #define SW_PAUSE_UNH_MODE BIT(1)
263 #define SW_AGGR_BACKOFF BIT(0)
267 #define SW_BACK_PRESSURE BIT(5)
269 #define FAIR_FLOW_CTRL BIT(4)
270 #define NO_EXC_COLLISION_DROP BIT(3)
271 #define SW_JUMBO_PACKET BIT(2)
272 #define SW_LEGAL_PACKET_DISABLE BIT(1)
273 #define SW_PASS_SHORT_FRAME BIT(0)
277 #define SW_REPLACE_VID BIT(3)
283 #define SW_PASS_PAUSE BIT(3)
287 #define SW_OUT_RATE_LIMIT_QUEUE_BASED BIT(3)
291 #define SW_MIB_COUNTER_FLUSH BIT(7)
292 #define SW_MIB_COUNTER_FREEZE BIT(6)
306 #define SW_TOS_DSCP_REMARK BIT(1)
307 #define SW_TOS_DSCP_REMAP BIT(0)
344 #define SW_IGMP_SNOOP BIT(6)
345 #define SW_IPV6_MLD_OPTION BIT(3)
346 #define SW_IPV6_MLD_SNOOP BIT(2)
347 #define SW_MIRROR_RX_TX BIT(0)
351 #define SW_CLASS_D_IP_ENABLE BIT(31)
355 #define SW_NO_COLOR_S 6
364 #define PRIO_SCHEME_SELECT_S 6
368 #define UNICAST_VLAN_BOUNDARY BIT(1)
374 /* 4 - */
377 #define VLAN_VALID BIT(31)
378 #define VLAN_FORWARD_OPTION BIT(27)
394 #define VLAN_START BIT(7)
407 #define ALU_DIRECT_INDEX_M (BIT(12) - 1)
411 #define ALU_VALID_CNT_M (BIT(14) - 1)
413 #define ALU_START BIT(7)
414 #define ALU_VALID BIT(6)
415 #define ALU_DIRECT BIT(2)
423 #define ALU_RESV_MCAST_INDEX_M (BIT(6) - 1)
424 #define ALU_STAT_START BIT(7)
425 #define ALU_RESV_MCAST_ADDR BIT(1)
429 #define ALU_V_STATIC_VALID BIT(31)
430 #define ALU_V_SRC_FILTER BIT(30)
431 #define ALU_V_DST_FILTER BIT(29)
432 #define ALU_V_PRIO_AGE_CNT_M (BIT(3) - 1)
438 #define ALU_V_OVERRIDE BIT(31)
439 #define ALU_V_USE_FID BIT(30)
440 #define ALU_V_PORT_MAP (BIT(24) - 1)
444 #define ALU_V_FID_M (BIT(16) - 1)
459 #define HSR_INDEX_MAX BIT(9)
460 #define HSR_DIRECT_INDEX_M (HSR_INDEX_MAX - 1)
464 #define HSR_PATH_INDEX_M (BIT(4) - 1)
468 #define HSR_VALID_CNT_M (BIT(14) - 1)
470 #define HSR_START BIT(7)
471 #define HSR_VALID BIT(6)
472 #define HSR_SEARCH_END BIT(5)
473 #define HSR_DIRECT BIT(2)
481 #define HSR_V_STATIC_VALID BIT(31)
482 #define HSR_V_AGE_CNT_M (BIT(3) - 1)
484 #define HSR_V_PATH_ID_M (BIT(4) - 1)
510 #define HSR_V_SEQ_M (BIT(16) - 1)
512 /* 5 - PTP Clock */
515 #define PTP_STEP_ADJ BIT(6)
516 #define PTP_STEP_DIR BIT(5)
517 #define PTP_READ_TIME BIT(4)
518 #define PTP_LOAD_TIME BIT(3)
519 #define PTP_CLK_ADJ_ENABLE BIT(2)
520 #define PTP_CLK_ENABLE BIT(1)
521 #define PTP_CLK_RESET BIT(0)
538 #define PTP_RATE_DIR BIT(31)
539 #define PTP_TMP_RATE_ENABLE BIT(30)
549 #define PTP_802_1AS BIT(7)
550 #define PTP_ENABLE BIT(6)
551 #define PTP_ETH_ENABLE BIT(5)
552 #define PTP_IPV4_UDP_ENABLE BIT(4)
553 #define PTP_IPV6_UDP_ENABLE BIT(3)
554 #define PTP_TC_P2P BIT(2)
555 #define PTP_MASTER BIT(1)
556 #define PTP_1STEP BIT(0)
560 #define PTP_UNICAST_ENABLE BIT(12)
561 #define PTP_ALTERNATE_MASTER BIT(11)
562 #define PTP_ALL_HIGH_PRIO BIT(10)
563 #define PTP_SYNC_CHECK BIT(9)
564 #define PTP_DELAY_CHECK BIT(8)
565 #define PTP_PDELAY_CHECK BIT(7)
566 #define PTP_DROP_SYNC_DELAY_REQ BIT(5)
567 #define PTP_DOMAIN_CHECK BIT(4)
568 #define PTP_UDP_CHECKSUM BIT(2)
597 #define GPIO_IN BIT(7)
598 #define GPIO_OUT BIT(6)
599 #define TS_INT_ENABLE BIT(5)
600 #define TRIG_ACTIVE BIT(4)
601 #define TRIG_ENABLE BIT(3)
602 #define TRIG_RESET BIT(2)
603 #define TS_ENABLE BIT(1)
604 #define TS_RESET BIT(0)
619 #define TRIG_CASCADE_ENABLE BIT(31)
620 #define TRIG_CASCADE_TAIL BIT(30)
623 #define TRIG_NOW BIT(25)
624 #define TRIG_NOTIFY BIT(24)
625 #define TRIG_EDGE BIT(23)
634 #define TRIG_REG_OUTPUT 6
657 #define TS_EVENT_OVERFLOW BIT(16)
660 #define TS_DETECT_RISE BIT(7)
661 #define TS_DETECT_FALL BIT(6)
662 #define TS_DETECT_S 6
663 #define TS_CASCADE_TAIL BIT(5)
666 #define TS_CASCADE_ENABLE BIT(0)
705 #define TS_EVENT_NANOSEC_M (BIT(30) - 1)
710 (REG_TS_EVENT_1_NANOSEC - REG_TS_EVENT_0_NANOSEC)
719 #define DLR_SRC_PORT_UNICAST BIT(31)
728 #define DLR_RESET_SEQ_ID BIT(3)
729 #define DLR_BACKUP_AUTO_ON BIT(2)
730 #define DLR_BEACON_TX_ENABLE BIT(1)
731 #define DLR_ASSIST_ENABLE BIT(0)
751 #define DLR_TIMEOUT_WINDOW_M (BIT(22) - 1)
755 #define DLR_VLAN_ID_M (BIT(12) - 1)
775 #define HSR_DUPLICATE_DISCARD BIT(7)
776 #define HSR_NODE_UNICAST BIT(6)
779 #define HSR_LEARN_MCAST_DISABLE BIT(2)
788 #define HSR_LEARN_UCAST_DISABLE BIT(7)
789 #define HSR_FLUSH_TABLE BIT(5)
790 #define HSR_PROC_MCAST_SRC BIT(3)
791 #define HSR_AGING_ENABLE BIT(2)
800 #define HSR_WINDOW_OVERFLOW_INT BIT(3)
801 #define HSR_LEARN_FAIL_INT BIT(2)
802 #define HSR_ALMOST_FULL_INT BIT(1)
803 #define HSR_WRITE_FAIL_INT BIT(0)
807 #define HSR_ENTRY_INDEX_M (BIT(10) - 1)
808 #define HSR_FAIL_INDEX_M (BIT(8) - 1)
812 #define HSR_FAIL_LEARN_INDEX_M (BIT(8) - 1)
816 #define HSR_CPU_ACCESS_ENTRY_INDEX_M (BIT(8) - 1)
818 /* 0 - Operation */
831 #define PME_WOL_MAGICPKT BIT(2)
832 #define PME_WOL_LINKUP BIT(1)
833 #define PME_WOL_ENERGY BIT(0)
838 #define PORT_SGMII_INT BIT(3)
839 #define PORT_PTP_INT BIT(2)
840 #define PORT_PHY_INT BIT(1)
841 #define PORT_ACL_INT BIT(0)
848 #define PORT_MAC_LOOPBACK BIT(7)
849 #define PORT_FORCE_TX_FLOW_CTRL BIT(4)
850 #define PORT_FORCE_RX_FLOW_CTRL BIT(3)
851 #define PORT_TAIL_TAG_ENABLE BIT(2)
866 #define PORT_INTF_FULL_DUPLEX BIT(2)
867 #define PORT_TX_FLOW_CTRL BIT(1)
868 #define PORT_RX_FLOW_CTRL BIT(0)
872 /* 1 - PHY */
875 #define PORT_PHY_RESET BIT(15)
876 #define PORT_PHY_LOOPBACK BIT(14)
877 #define PORT_SPEED_100MBIT BIT(13)
878 #define PORT_AUTO_NEG_ENABLE BIT(12)
879 #define PORT_POWER_DOWN BIT(11)
880 #define PORT_ISOLATE BIT(10)
881 #define PORT_AUTO_NEG_RESTART BIT(9)
882 #define PORT_FULL_DUPLEX BIT(8)
883 #define PORT_COLLISION_TEST BIT(7)
884 #define PORT_SPEED_1000MBIT BIT(6)
888 #define PORT_100BT4_CAPABLE BIT(15)
889 #define PORT_100BTX_FD_CAPABLE BIT(14)
890 #define PORT_100BTX_CAPABLE BIT(13)
891 #define PORT_10BT_FD_CAPABLE BIT(12)
892 #define PORT_10BT_CAPABLE BIT(11)
893 #define PORT_EXTENDED_STATUS BIT(8)
894 #define PORT_MII_SUPPRESS_CAPABLE BIT(6)
895 #define PORT_AUTO_NEG_ACKNOWLEDGE BIT(5)
896 #define PORT_REMOTE_FAULT BIT(4)
897 #define PORT_AUTO_NEG_CAPABLE BIT(3)
898 #define PORT_LINK_STATUS BIT(2)
899 #define PORT_JABBER_DETECT BIT(1)
900 #define PORT_EXTENDED_CAPABILITY BIT(0)
910 #define PORT_AUTO_NEG_NEXT_PAGE BIT(15)
911 #define PORT_AUTO_NEG_REMOTE_FAULT BIT(13)
912 #define PORT_AUTO_NEG_ASYM_PAUSE BIT(11)
913 #define PORT_AUTO_NEG_SYM_PAUSE BIT(10)
914 #define PORT_AUTO_NEG_100BT4 BIT(9)
915 #define PORT_AUTO_NEG_100BTX_FD BIT(8)
916 #define PORT_AUTO_NEG_100BTX BIT(7)
917 #define PORT_AUTO_NEG_10BT_FD BIT(6)
918 #define PORT_AUTO_NEG_10BT BIT(5)
927 #define PORT_REMOTE_NEXT_PAGE BIT(15)
928 #define PORT_REMOTE_ACKNOWLEDGE BIT(14)
929 #define PORT_REMOTE_REMOTE_FAULT BIT(13)
930 #define PORT_REMOTE_ASYM_PAUSE BIT(11)
931 #define PORT_REMOTE_SYM_PAUSE BIT(10)
932 #define PORT_REMOTE_100BTX_FD BIT(8)
933 #define PORT_REMOTE_100BTX BIT(7)
934 #define PORT_REMOTE_10BT_FD BIT(6)
935 #define PORT_REMOTE_10BT BIT(5)
939 #define PORT_AUTO_NEG_MANUAL BIT(12)
940 #define PORT_AUTO_NEG_MASTER BIT(11)
941 #define PORT_AUTO_NEG_MASTER_PREFERRED BIT(10)
942 #define PORT_AUTO_NEG_1000BT_FD BIT(9)
943 #define PORT_AUTO_NEG_1000BT BIT(8)
947 #define PORT_MASTER_FAULT BIT(15)
948 #define PORT_LOCAL_MASTER BIT(14)
949 #define PORT_LOCAL_RX_OK BIT(13)
950 #define PORT_REMOTE_RX_OK BIT(12)
951 #define PORT_REMOTE_1000BT_FD BIT(11)
952 #define PORT_REMOTE_1000BT BIT(10)
983 #define DSP_SQI_ERR_DETECTED BIT(15)
991 #define EEE_ADV_100MBIT BIT(1)
992 #define EEE_ADV_1GBIT BIT(2)
1001 #define PORT_100BTX_FD_ABLE BIT(15)
1002 #define PORT_100BTX_ABLE BIT(14)
1003 #define PORT_10BT_FD_ABLE BIT(13)
1004 #define PORT_10BT_ABLE BIT(12)
1007 #define PORT_SGMII_AUTO_INCR BIT(23)
1010 #define PORT_SGMII_ADDR_M (BIT(21) - 1)
1013 #define PORT_SGMII_DATA_M (BIT(16) - 1)
1027 #define SR_MII_RESET BIT(15)
1028 #define SR_MII_LOOPBACK BIT(14)
1029 #define SR_MII_SPEED_100MBIT BIT(13)
1030 #define SR_MII_AUTO_NEG_ENABLE BIT(12)
1031 #define SR_MII_POWER_DOWN BIT(11)
1032 #define SR_MII_AUTO_NEG_RESTART BIT(9)
1033 #define SR_MII_FULL_DUPLEX BIT(8)
1034 #define SR_MII_SPEED_1000MBIT BIT(6)
1041 #define SR_MII_AUTO_NEG_NEXT_PAGE BIT(15)
1054 #define SR_MII_AUTO_NEG_HALF_DUPLEX BIT(6)
1055 #define SR_MII_AUTO_NEG_FULL_DUPLEX BIT(5)
1065 #define SR_MII_8_BIT BIT(8)
1066 #define SR_MII_SGMII_LINK_UP BIT(4)
1067 #define SR_MII_TX_CFG_PHY_MASTER BIT(3)
1071 #define SR_MII_AUTO_NEG_COMPLETE_INTR BIT(0)
1075 #define SR_MII_STAT_LINK_UP BIT(4)
1081 #define SR_MII_STAT_FULL_DUPLEX BIT(1)
1087 #define SR_MII_PHY_WRITE BIT(1)
1088 #define SR_MII_PHY_START_BUSY BIT(0)
1092 #define SR_MII_PHY_ADDR_M (BIT(16) - 1)
1096 #define SR_MII_PHY_DATA_M (BIT(16) - 1)
1103 #define PORT_REMOTE_LOOPBACK BIT(8)
1104 #define PORT_LED_SELECT (3 << 6)
1106 #define PORT_LED_CTRL_TEST BIT(3)
1107 #define PORT_10BT_PREAMBLE BIT(2)
1108 #define PORT_LINK_MD_10BT_ENABLE BIT(1)
1109 #define PORT_LINK_MD_PASS BIT(0)
1113 #define PORT_START_CABLE_DIAG BIT(15)
1114 #define PORT_TX_DISABLE BIT(14)
1129 #define PORT_1000_LINK_GOOD BIT(1)
1130 #define PORT_100_LINK_GOOD BIT(0)
1134 #define PORT_LINK_DETECT BIT(14)
1135 #define PORT_SIGNAL_DETECT BIT(13)
1136 #define PORT_PHY_STAT_MDI BIT(12)
1137 #define PORT_PHY_STAT_MASTER BIT(11)
1144 #define JABBER_INT BIT(7)
1145 #define RX_ERR_INT BIT(6)
1146 #define PAGE_RX_INT BIT(5)
1147 #define PARALLEL_DETECT_FAULT_INT BIT(4)
1148 #define LINK_PARTNER_ACK_INT BIT(3)
1149 #define LINK_DOWN_INT BIT(2)
1150 #define REMOTE_FAULT_INT BIT(1)
1151 #define LINK_UP_INT BIT(0)
1155 #define PORT_REG_CLK_SPEED_25_MHZ BIT(14)
1156 #define PORT_PHY_FORCE_MDI BIT(7)
1157 #define PORT_PHY_AUTO_MDIX_DISABLE BIT(6)
1160 #define PORT_PHY_PCS_LOOPBACK BIT(0)
1166 #define PORT_100BT_FIXED_LATENCY BIT(15)
1170 #define PORT_INT_PIN_HIGH BIT(14)
1171 #define PORT_ENABLE_JABBER BIT(9)
1172 #define PORT_STAT_SPEED_1000MBIT BIT(6)
1173 #define PORT_STAT_SPEED_100MBIT BIT(5)
1174 #define PORT_STAT_SPEED_10MBIT BIT(4)
1175 #define PORT_STAT_FULL_DUPLEX BIT(3)
1178 #define PORT_STAT_MASTER BIT(2)
1179 #define PORT_RESET BIT(1)
1180 #define PORT_LINK_STATUS_FAIL BIT(0)
1182 /* 3 - xMII */
1183 #define PORT_SGMII_SEL BIT(7)
1184 #define PORT_GRXC_ENABLE BIT(0)
1186 #define PORT_RMII_CLK_SEL BIT(7)
1187 #define PORT_MII_SEL_EDGE BIT(5)
1189 /* 4 - MAC */
1192 #define PORT_BROADCAST_STORM BIT(1)
1193 #define PORT_JUMBO_FRAME BIT(0)
1197 #define PORT_BACK_PRESSURE BIT(3)
1198 #define PORT_PASS_ALL BIT(0)
1202 #define PORT_100BT_EEE_DISABLE BIT(7)
1203 #define PORT_1000BT_EEE_DISABLE BIT(6)
1207 #define PORT_IN_PORT_BASED_S 6
1212 #define PORT_IN_PORT_BASED BIT(6)
1213 #define PORT_IN_PACKET_BASED BIT(5)
1214 #define PORT_IN_FLOW_CTRL BIT(4)
1221 #define PORT_COUNT_IFG BIT(1)
1222 #define PORT_COUNT_PREAMBLE BIT(0)
1238 #define PORT_RATE_LIMIT_M (BIT(7) - 1)
1240 /* 5 - MIB Counters */
1243 #define MIB_COUNTER_READ BIT(25)
1244 #define MIB_COUNTER_FLUSH_FREEZE BIT(24)
1245 #define MIB_COUNTER_INDEX_M (BIT(8) - 1)
1251 /* 6 - ACL */
1276 #define ACL_SRC BIT(1)
1277 #define ACL_EQUAL BIT(0)
1303 #define ACL_TCP_FLAG_ENABLE BIT(0)
1318 #define ACL_PRIO_MODE_S 6
1325 #define ACL_VLAN_PRIO_REPLACE BIT(2)
1340 #define ACL_CNT_M (BIT(11) - 1)
1346 #define ACL_MSEC_UNIT BIT(6)
1347 #define ACL_INTR_MODE BIT(5)
1370 #define PORT_ACL_WRITE_DONE BIT(6)
1371 #define PORT_ACL_READ_DONE BIT(5)
1372 #define PORT_ACL_WRITE BIT(4)
1377 /* 8 - Classification and Policing */
1380 #define PORT_MIRROR_RX BIT(6)
1381 #define PORT_MIRROR_TX BIT(5)
1382 #define PORT_MIRROR_SNIFFER BIT(1)
1386 #define PORT_HIGHEST_PRIO BIT(7)
1387 #define PORT_OR_PRIO BIT(6)
1388 #define PORT_MAC_PRIO_ENABLE BIT(4)
1389 #define PORT_VLAN_PRIO_ENABLE BIT(3)
1390 #define PORT_802_1P_PRIO_ENABLE BIT(2)
1391 #define PORT_DIFFSERV_PRIO_ENABLE BIT(1)
1392 #define PORT_ACL_PRIO_ENABLE BIT(0)
1396 #define PORT_USER_PRIO_CEILING BIT(7)
1397 #define PORT_DROP_NON_VLAN BIT(4)
1398 #define PORT_DROP_TAG BIT(3)
1404 #define PORT_ACL_ENABLE BIT(2)
1424 #define POLICE_DROP_ALL BIT(10)
1431 #define PORT_BASED_POLICING BIT(7)
1434 #define COLOR_MARK_ENABLE BIT(4)
1435 #define COLOR_REMAP_ENABLE BIT(3)
1436 #define POLICE_DROP_SRP BIT(2)
1437 #define POLICE_COLOR_NOT_AWARE BIT(1)
1438 #define POLICE_ENABLE BIT(0)
1446 #define POLICE_COLOR_MAP_M (BIT(POLICE_COLOR_MAP_S) - 1)
1461 #define WRED_PM_CTRL_M (BIT(11) - 1)
1476 #define WRED_RANDOM_DROP_ENABLE BIT(31)
1477 #define WRED_PMON_FLUSH BIT(30)
1478 #define WRED_DROP_GYR_DISABLE BIT(29)
1479 #define WRED_DROP_YR_DISABLE BIT(28)
1480 #define WRED_DROP_R_DISABLE BIT(27)
1481 #define WRED_DROP_ALL BIT(26)
1482 #define WRED_PMON_M (BIT(24) - 1)
1484 /* 9 - Shaping */
1488 #define MTI_PVID_REPLACE BIT(0)
1492 /* A - QM */
1504 #define PORT_QM_MIN_RESV_SPACE_M (BIT(11) - 1)
1510 #define PORT_QM_WATER_MARK_M (BIT(11) - 1)
1515 #define PORT_QM_TX_CNT_M (BIT(11) - 1)
1522 /* B - LUE */
1525 #define PORT_VLAN_LOOKUP_VID_0 BIT(7)
1526 #define PORT_INGRESS_FILTER BIT(6)
1527 #define PORT_DISCARD_NON_VID BIT(5)
1528 #define PORT_MAC_BASED_802_1X BIT(4)
1529 #define PORT_SRC_ADDR_FILTER BIT(3)
1535 /* C - PTP */
1556 #define PTP_PORT_SYNC_INT BIT(15)
1557 #define PTP_PORT_XDELAY_REQ_INT BIT(14)
1558 #define PTP_PORT_PDELAY_RESP_INT BIT(13)
1595 #define PTP_TRIG_UNIT_M (BIT(MAX_TRIG_UNIT) - 1)
1596 #define PTP_TS_UNIT_M (BIT(MAX_TIMESTAMP_UNIT) - 1)