Lines Matching +full:canfd +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2012 - 2022 Xilinx, Inc.
6 * Copyright (C) 2017 - 2018 Sandvik Mining and Construction Oy
87 /* CAN register bit masks - XCAN_<REG>_<BIT>_MASK */
94 #define XCAN_2_BRPR_TDCO_MASK GENMASK(13, 8) /* TDCO for CANFD 2.0 */
96 #define XCAN_BTR_TS2_MASK 0x00000070 /* Time segment 2 */
99 #define XCAN_BTR_TS2_MASK_CANFD 0x00000F00 /* Time segment 2 */
141 /* CAN register bit shift - XCAN_<REG>_<BIT>_SHIFT */
144 #define XCAN_BTR_TS2_SHIFT 4 /* Time segment 2 */
146 #define XCAN_BTR_TS2_SHIFT_CANFD 8 /* Time segment 2 */
157 /* TX-FIFO-empty interrupt available */
188 * struct xcan_priv - This definition define CAN driver instance
239 /* AXI CANFD Arbitration Bittiming constants as per AXI CANFD 1.0 spec */
252 /* AXI CANFD Data Bittiming constants as per AXI CANFD 1.0 specs */
265 /* AXI CANFD 2.0 Arbitration Bittiming constants as per AXI CANFD 2.0 spec */
278 /* AXI CANFD 2.0 Data Bittiming constants as per AXI CANFD 2.0 spec */
291 /* Transmission Delay Compensation constants for CANFD 1.0 */
301 /* Transmission Delay Compensation constants for CANFD 2.0 */
312 * xcan_write_reg_le - Write a value to the device register little endian
322 iowrite32(val, priv->reg_base + reg); in xcan_write_reg_le()
326 * xcan_read_reg_le - Read a value from the device register little endian
335 return ioread32(priv->reg_base + reg); in xcan_read_reg_le()
339 * xcan_write_reg_be - Write a value to the device register big endian
349 iowrite32be(val, priv->reg_base + reg); in xcan_write_reg_be()
353 * xcan_read_reg_be - Read a value from the device register big endian
362 return ioread32be(priv->reg_base + reg); in xcan_read_reg_be()
366 * xcan_rx_int_mask - Get the mask for the receive interrupt
374 * while the FIFO is non-empty, but CAN FD HW does not have it in xcan_rx_int_mask()
376 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) in xcan_rx_int_mask()
383 * set_reset_mode - Resets the CAN device mode
396 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); in set_reset_mode()
399 while (!(priv->read_reg(priv, XCAN_SR_OFFSET) & XCAN_SR_CONFIG_MASK)) { in set_reset_mode()
402 return -ETIMEDOUT; in set_reset_mode()
408 priv->tx_head = 0; in set_reset_mode()
409 priv->tx_tail = 0; in set_reset_mode()
415 * xcan_set_bittiming - CAN set bit timing routine
424 struct can_bittiming *bt = &priv->can.bittiming; in xcan_set_bittiming()
425 struct can_bittiming *dbt = &priv->can.data_bittiming; in xcan_set_bittiming()
432 is_config_mode = priv->read_reg(priv, XCAN_SR_OFFSET) & in xcan_set_bittiming()
436 "BUG! Cannot set bittiming - CAN is not in config mode\n"); in xcan_set_bittiming()
437 return -EPERM; in xcan_set_bittiming()
441 btr0 = (bt->brp - 1); in xcan_set_bittiming()
444 btr1 = (bt->prop_seg + bt->phase_seg1 - 1); in xcan_set_bittiming()
446 /* Setting Time Segment 2 in BTR Register */ in xcan_set_bittiming()
447 btr1 |= (bt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; in xcan_set_bittiming()
450 btr1 |= (bt->sjw - 1) << priv->devtype.btr_sjw_shift; in xcan_set_bittiming()
452 priv->write_reg(priv, XCAN_BRPR_OFFSET, btr0); in xcan_set_bittiming()
453 priv->write_reg(priv, XCAN_BTR_OFFSET, btr1); in xcan_set_bittiming()
455 if (priv->devtype.cantype == XAXI_CANFD || in xcan_set_bittiming()
456 priv->devtype.cantype == XAXI_CANFD_2_0) { in xcan_set_bittiming()
458 btr0 = dbt->brp - 1; in xcan_set_bittiming()
459 if (can_tdc_is_enabled(&priv->can)) { in xcan_set_bittiming()
460 if (priv->devtype.cantype == XAXI_CANFD) in xcan_set_bittiming()
461 btr0 |= FIELD_PREP(XCAN_BRPR_TDCO_MASK, priv->can.tdc.tdco) | in xcan_set_bittiming()
464 btr0 |= FIELD_PREP(XCAN_2_BRPR_TDCO_MASK, priv->can.tdc.tdco) | in xcan_set_bittiming()
469 btr1 = dbt->prop_seg + dbt->phase_seg1 - 1; in xcan_set_bittiming()
471 /* Setting Time Segment 2 in BTR Register */ in xcan_set_bittiming()
472 btr1 |= (dbt->phase_seg2 - 1) << priv->devtype.btr_ts2_shift; in xcan_set_bittiming()
475 btr1 |= (dbt->sjw - 1) << priv->devtype.btr_sjw_shift; in xcan_set_bittiming()
477 priv->write_reg(priv, XCAN_F_BRPR_OFFSET, btr0); in xcan_set_bittiming()
478 priv->write_reg(priv, XCAN_F_BTR_OFFSET, btr1); in xcan_set_bittiming()
482 priv->read_reg(priv, XCAN_BRPR_OFFSET), in xcan_set_bittiming()
483 priv->read_reg(priv, XCAN_BTR_OFFSET)); in xcan_set_bittiming()
489 * xcan_chip_start - This the drivers start routine
526 if (priv->devtype.flags & XCAN_FLAG_RXMNF) in xcan_chip_start()
529 priv->write_reg(priv, XCAN_IER_OFFSET, ier); in xcan_chip_start()
532 if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) in xcan_chip_start()
538 * filtering default to non-receipt if all filters are disabled in xcan_chip_start()
540 if (priv->devtype.flags & XCAN_FLAG_EXT_FILTERS) in xcan_chip_start()
541 priv->write_reg(priv, XCAN_AFR_EXT_OFFSET, 0x00000001); in xcan_chip_start()
543 priv->write_reg(priv, XCAN_MSR_OFFSET, reg_msr); in xcan_chip_start()
544 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_CEN_MASK); in xcan_chip_start()
547 priv->read_reg(priv, XCAN_SR_OFFSET)); in xcan_chip_start()
549 priv->can.state = CAN_STATE_ERROR_ACTIVE; in xcan_chip_start()
554 * xcan_do_set_mode - This sets the mode of the driver
576 ret = -EOPNOTSUPP; in xcan_do_set_mode()
584 * xcan_write_frame - Write a frame to HW
592 u32 id, dlc, data[2] = {0, 0}; in xcan_write_frame()
593 struct canfd_frame *cf = (struct canfd_frame *)skb->data; in xcan_write_frame()
598 if (cf->can_id & CAN_EFF_FLAG) { in xcan_write_frame()
600 id = ((cf->can_id & CAN_EFF_MASK) << XCAN_IDR_ID2_SHIFT) & in xcan_write_frame()
602 id |= (((cf->can_id & CAN_EFF_MASK) >> in xcan_write_frame()
603 (CAN_EFF_ID_BITS - CAN_SFF_ID_BITS)) << in xcan_write_frame()
611 if (cf->can_id & CAN_RTR_FLAG) in xcan_write_frame()
616 id = ((cf->can_id & CAN_SFF_MASK) << XCAN_IDR_ID1_SHIFT) & in xcan_write_frame()
619 if (cf->can_id & CAN_RTR_FLAG) in xcan_write_frame()
624 dlc = can_fd_len2dlc(cf->len) << XCAN_DLCR_DLC_SHIFT; in xcan_write_frame()
626 if (cf->flags & CANFD_BRS) in xcan_write_frame()
631 if (!(priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) && in xcan_write_frame()
632 (priv->devtype.flags & XCAN_FLAG_TXFEMP)) in xcan_write_frame()
633 can_put_echo_skb(skb, ndev, priv->tx_head % priv->tx_max, 0); in xcan_write_frame()
637 priv->tx_head++; in xcan_write_frame()
639 priv->write_reg(priv, XCAN_FRAME_ID_OFFSET(frame_offset), id); in xcan_write_frame()
643 priv->write_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_offset), dlc); in xcan_write_frame()
644 if (priv->devtype.cantype == XAXI_CANFD || in xcan_write_frame()
645 priv->devtype.cantype == XAXI_CANFD_2_0) { in xcan_write_frame()
646 for (i = 0; i < cf->len; i += 4) { in xcan_write_frame()
649 priv->write_reg(priv, ramoff, in xcan_write_frame()
650 be32_to_cpup((__be32 *)(cf->data + i))); in xcan_write_frame()
654 if (cf->len > 0) in xcan_write_frame()
655 data[0] = be32_to_cpup((__be32 *)(cf->data + 0)); in xcan_write_frame()
656 if (cf->len > 4) in xcan_write_frame()
657 data[1] = be32_to_cpup((__be32 *)(cf->data + 4)); in xcan_write_frame()
659 if (!(cf->can_id & CAN_RTR_FLAG)) { in xcan_write_frame()
660 priv->write_reg(priv, in xcan_write_frame()
666 priv->write_reg(priv, in xcan_write_frame()
674 * xcan_start_xmit_fifo - Starts the transmission (FIFO mode)
678 * Return: 0 on success, -ENOSPC if FIFO is full.
686 if (unlikely(priv->read_reg(priv, XCAN_SR_OFFSET) & in xcan_start_xmit_fifo()
688 return -ENOSPC; in xcan_start_xmit_fifo()
690 spin_lock_irqsave(&priv->tx_lock, flags); in xcan_start_xmit_fifo()
694 /* Clear TX-FIFO-empty interrupt for xcan_tx_interrupt() */ in xcan_start_xmit_fifo()
695 if (priv->tx_max > 1) in xcan_start_xmit_fifo()
696 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXFEMP_MASK); in xcan_start_xmit_fifo()
699 if ((priv->tx_head - priv->tx_tail) == priv->tx_max) in xcan_start_xmit_fifo()
702 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_start_xmit_fifo()
708 * xcan_start_xmit_mailbox - Starts the transmission (mailbox mode)
712 * Return: 0 on success, -ENOSPC if there is no space
719 if (unlikely(priv->read_reg(priv, XCAN_TRR_OFFSET) & in xcan_start_xmit_mailbox()
721 return -ENOSPC; in xcan_start_xmit_mailbox()
723 spin_lock_irqsave(&priv->tx_lock, flags); in xcan_start_xmit_mailbox()
729 priv->write_reg(priv, XCAN_TRR_OFFSET, BIT(XCAN_TX_MAILBOX_IDX)); in xcan_start_xmit_mailbox()
733 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_start_xmit_mailbox()
739 * xcan_start_xmit - Starts the transmission
755 if (priv->devtype.flags & XCAN_FLAG_TX_MAILBOXES) in xcan_start_xmit()
770 * xcan_rx - Is called from CAN isr to complete the received
783 struct net_device_stats *stats = &ndev->stats; in xcan_rx()
786 u32 id_xcan, dlc, data[2] = {0, 0}; in xcan_rx()
790 stats->rx_dropped++; in xcan_rx()
795 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); in xcan_rx()
796 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)) >> in xcan_rx()
800 cf->len = can_cc_dlc2len(dlc); in xcan_rx()
805 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; in xcan_rx()
806 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> in xcan_rx()
808 cf->can_id |= CAN_EFF_FLAG; in xcan_rx()
810 cf->can_id |= CAN_RTR_FLAG; in xcan_rx()
813 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> in xcan_rx()
816 cf->can_id |= CAN_RTR_FLAG; in xcan_rx()
820 data[0] = priv->read_reg(priv, XCAN_FRAME_DW1_OFFSET(frame_base)); in xcan_rx()
821 data[1] = priv->read_reg(priv, XCAN_FRAME_DW2_OFFSET(frame_base)); in xcan_rx()
823 if (!(cf->can_id & CAN_RTR_FLAG)) { in xcan_rx()
825 if (cf->len > 0) in xcan_rx()
826 *(__be32 *)(cf->data) = cpu_to_be32(data[0]); in xcan_rx()
827 if (cf->len > 4) in xcan_rx()
828 *(__be32 *)(cf->data + 4) = cpu_to_be32(data[1]); in xcan_rx()
830 stats->rx_bytes += cf->len; in xcan_rx()
832 stats->rx_packets++; in xcan_rx()
840 * xcanfd_rx - Is called from CAN isr to complete the received
853 struct net_device_stats *stats = &ndev->stats; in xcanfd_rx()
856 u32 id_xcan, dlc, data[2] = {0, 0}, dwindex = 0, i, dw_offset; in xcanfd_rx()
858 id_xcan = priv->read_reg(priv, XCAN_FRAME_ID_OFFSET(frame_base)); in xcanfd_rx()
859 dlc = priv->read_reg(priv, XCAN_FRAME_DLC_OFFSET(frame_base)); in xcanfd_rx()
866 stats->rx_dropped++; in xcanfd_rx()
870 /* Change Xilinx CANFD data length format to socketCAN data in xcanfd_rx()
874 cf->len = can_fd_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >> in xcanfd_rx()
877 cf->len = can_cc_dlc2len((dlc & XCAN_DLCR_DLC_MASK) >> in xcanfd_rx()
883 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> 3; in xcanfd_rx()
884 cf->can_id |= (id_xcan & XCAN_IDR_ID2_MASK) >> in xcanfd_rx()
886 cf->can_id |= CAN_EFF_FLAG; in xcanfd_rx()
888 cf->can_id |= CAN_RTR_FLAG; in xcanfd_rx()
891 cf->can_id = (id_xcan & XCAN_IDR_ID1_MASK) >> in xcanfd_rx()
895 cf->can_id |= CAN_RTR_FLAG; in xcanfd_rx()
900 for (i = 0; i < cf->len; i += 4) { in xcanfd_rx()
903 data[0] = priv->read_reg(priv, dw_offset); in xcanfd_rx()
904 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]); in xcanfd_rx()
908 for (i = 0; i < cf->len; i += 4) { in xcanfd_rx()
910 data[0] = priv->read_reg(priv, dw_offset + i); in xcanfd_rx()
911 *(__be32 *)(cf->data + i) = cpu_to_be32(data[0]); in xcanfd_rx()
915 if (!(cf->can_id & CAN_RTR_FLAG)) in xcanfd_rx()
916 stats->rx_bytes += cf->len; in xcanfd_rx()
917 stats->rx_packets++; in xcanfd_rx()
925 * xcan_current_error_state - Get current error state from HW
938 u32 status = priv->read_reg(priv, XCAN_SR_OFFSET); in xcan_current_error_state()
949 * xcan_set_error_state - Set new CAN error state
962 u32 ecr = priv->read_reg(priv, XCAN_ECR_OFFSET); in xcan_set_error_state()
968 /* non-ERROR states are handled elsewhere */ in xcan_set_error_state()
975 cf->can_id |= CAN_ERR_CNT; in xcan_set_error_state()
976 cf->data[6] = txerr; in xcan_set_error_state()
977 cf->data[7] = rxerr; in xcan_set_error_state()
982 * xcan_update_error_state_after_rxtx - Update CAN error state after RX/TX
985 * If the device is in a ERROR-WARNING or ERROR-PASSIVE state, check if
992 enum can_state old_state = priv->can.state; in xcan_update_error_state_after_rxtx()
1018 * xcan_err_interrupt - error frame Isr
1029 struct net_device_stats *stats = &ndev->stats; in xcan_err_interrupt()
1033 err_status = priv->read_reg(priv, XCAN_ESR_OFFSET); in xcan_err_interrupt()
1034 priv->write_reg(priv, XCAN_ESR_OFFSET, err_status); in xcan_err_interrupt()
1037 priv->can.state = CAN_STATE_BUS_OFF; in xcan_err_interrupt()
1038 priv->can.can_stats.bus_off++; in xcan_err_interrupt()
1039 /* Leave device in Config Mode in bus-off state */ in xcan_err_interrupt()
1040 priv->write_reg(priv, XCAN_SRR_OFFSET, XCAN_SRR_RESET_MASK); in xcan_err_interrupt()
1046 if (new_state != priv->can.state) in xcan_err_interrupt()
1052 priv->can.can_stats.arbitration_lost++; in xcan_err_interrupt()
1059 stats->rx_over_errors++; in xcan_err_interrupt()
1060 stats->rx_errors++; in xcan_err_interrupt()
1067 stats->rx_dropped++; in xcan_err_interrupt()
1068 stats->rx_errors++; in xcan_err_interrupt()
1078 if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) { in xcan_err_interrupt()
1085 stats->tx_errors++; in xcan_err_interrupt()
1094 stats->tx_errors++; in xcan_err_interrupt()
1097 cf.data[2] = CAN_ERR_PROT_BIT; in xcan_err_interrupt()
1103 stats->rx_errors++; in xcan_err_interrupt()
1106 cf.data[2] = CAN_ERR_PROT_STUFF; in xcan_err_interrupt()
1112 stats->rx_errors++; in xcan_err_interrupt()
1115 cf.data[2] = CAN_ERR_PROT_FORM; in xcan_err_interrupt()
1121 stats->rx_errors++; in xcan_err_interrupt()
1127 priv->can.can_stats.bus_error++; in xcan_err_interrupt()
1135 skb_cf->can_id |= cf.can_id; in xcan_err_interrupt()
1136 memcpy(skb_cf->data, cf.data, CAN_ERR_DLC); in xcan_err_interrupt()
1142 __func__, priv->read_reg(priv, XCAN_ESR_OFFSET)); in xcan_err_interrupt()
1146 * xcan_state_interrupt - It will check the state of the CAN device
1159 priv->can.state = CAN_STATE_SLEEPING; in xcan_state_interrupt()
1163 priv->can.state = CAN_STATE_ERROR_ACTIVE; in xcan_state_interrupt()
1167 * xcan_rx_fifo_get_next_frame - Get register offset of next RX frame
1176 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) { in xcan_rx_fifo_get_next_frame()
1179 /* clear RXOK before the is-empty check so that any newly in xcan_rx_fifo_get_next_frame()
1182 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_RXOK_MASK); in xcan_rx_fifo_get_next_frame()
1184 fsr = priv->read_reg(priv, XCAN_FSR_OFFSET); in xcan_rx_fifo_get_next_frame()
1187 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) in xcan_rx_fifo_get_next_frame()
1193 return -ENOENT; in xcan_rx_fifo_get_next_frame()
1195 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) in xcan_rx_fifo_get_next_frame()
1204 if (!(priv->read_reg(priv, XCAN_ISR_OFFSET) & in xcan_rx_fifo_get_next_frame()
1206 return -ENOENT; in xcan_rx_fifo_get_next_frame()
1216 * xcan_rx_poll - Poll routine for rx packets (NAPI)
1227 struct net_device *ndev = napi->dev; in xcan_rx_poll()
1240 if (priv->devtype.flags & XCAN_FLAG_RX_FIFO_MULTI) in xcan_rx_poll()
1242 priv->write_reg(priv, XCAN_FSR_OFFSET, in xcan_rx_poll()
1245 /* clear rx-not-empty (will actually clear only if in xcan_rx_poll()
1248 priv->write_reg(priv, XCAN_ICR_OFFSET, in xcan_rx_poll()
1257 ier = priv->read_reg(priv, XCAN_IER_OFFSET); in xcan_rx_poll()
1259 priv->write_reg(priv, XCAN_IER_OFFSET, ier); in xcan_rx_poll()
1266 * xcan_tx_interrupt - Tx Done Isr
1273 struct net_device_stats *stats = &ndev->stats; in xcan_tx_interrupt()
1285 spin_lock_irqsave(&priv->tx_lock, flags); in xcan_tx_interrupt()
1287 frames_in_fifo = priv->tx_head - priv->tx_tail; in xcan_tx_interrupt()
1291 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); in xcan_tx_interrupt()
1292 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_tx_interrupt()
1296 /* Check if 2 frames were sent (TXOK only means that at least 1 in xcan_tx_interrupt()
1300 WARN_ON(frames_in_fifo > priv->tx_max); in xcan_tx_interrupt()
1303 * (1) isr variable is up-to-date at least up to TXOK clear in xcan_tx_interrupt()
1307 * (2) No TXOK is left. Having one could mean leaving a in xcan_tx_interrupt()
1314 priv->write_reg(priv, XCAN_ICR_OFFSET, in xcan_tx_interrupt()
1316 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); in xcan_tx_interrupt()
1325 priv->write_reg(priv, XCAN_ICR_OFFSET, XCAN_IXR_TXOK_MASK); in xcan_tx_interrupt()
1328 while (frames_sent--) { in xcan_tx_interrupt()
1329 stats->tx_bytes += can_get_echo_skb(ndev, priv->tx_tail % in xcan_tx_interrupt()
1330 priv->tx_max, NULL); in xcan_tx_interrupt()
1331 priv->tx_tail++; in xcan_tx_interrupt()
1332 stats->tx_packets++; in xcan_tx_interrupt()
1337 spin_unlock_irqrestore(&priv->tx_lock, flags); in xcan_tx_interrupt()
1343 * xcan_interrupt - CAN Isr
1351 * IRQ_NONE - If CAN device is in sleep mode, IRQ_HANDLED otherwise
1362 isr = priv->read_reg(priv, XCAN_ISR_OFFSET); in xcan_interrupt()
1368 priv->write_reg(priv, XCAN_ICR_OFFSET, (XCAN_IXR_SLP_MASK | in xcan_interrupt()
1382 priv->write_reg(priv, XCAN_ICR_OFFSET, isr_errors); in xcan_interrupt()
1388 ier = priv->read_reg(priv, XCAN_IER_OFFSET); in xcan_interrupt()
1390 priv->write_reg(priv, XCAN_IER_OFFSET, ier); in xcan_interrupt()
1391 napi_schedule(&priv->napi); in xcan_interrupt()
1397 * xcan_chip_stop - Driver stop routine
1413 priv->can.state = CAN_STATE_STOPPED; in xcan_chip_stop()
1417 * xcan_open - Driver open routine
1428 ret = phy_power_on(priv->transceiver); in xcan_open()
1432 ret = pm_runtime_get_sync(priv->dev); in xcan_open()
1439 ret = request_irq(ndev->irq, xcan_interrupt, priv->irq_flags, in xcan_open()
1440 ndev->name, ndev); in xcan_open()
1464 napi_enable(&priv->napi); in xcan_open()
1472 free_irq(ndev->irq, ndev); in xcan_open()
1474 pm_runtime_put(priv->dev); in xcan_open()
1475 phy_power_off(priv->transceiver); in xcan_open()
1481 * xcan_close - Driver close routine
1491 napi_disable(&priv->napi); in xcan_close()
1493 free_irq(ndev->irq, ndev); in xcan_close()
1496 pm_runtime_put(priv->dev); in xcan_close()
1497 phy_power_off(priv->transceiver); in xcan_close()
1503 * xcan_get_berr_counter - error counter routine
1516 ret = pm_runtime_get_sync(priv->dev); in xcan_get_berr_counter()
1520 pm_runtime_put(priv->dev); in xcan_get_berr_counter()
1524 bec->txerr = priv->read_reg(priv, XCAN_ECR_OFFSET) & XCAN_ECR_TEC_MASK; in xcan_get_berr_counter()
1525 bec->rxerr = ((priv->read_reg(priv, XCAN_ECR_OFFSET) & in xcan_get_berr_counter()
1528 pm_runtime_put(priv->dev); in xcan_get_berr_counter()
1534 * xcan_get_auto_tdcv - Get Transmitter Delay Compensation Value
1544 *tdcv = FIELD_GET(XCAN_SR_TDCV_MASK, priv->read_reg(priv, XCAN_SR_OFFSET)); in xcan_get_auto_tdcv()
1561 * xcan_suspend - Suspend method for the driver
1581 * xcan_resume - Resume from suspend
1613 * xcan_runtime_suspend - Runtime suspend method for the driver
1624 clk_disable_unprepare(priv->bus_clk); in xcan_runtime_suspend()
1625 clk_disable_unprepare(priv->can_clk); in xcan_runtime_suspend()
1631 * xcan_runtime_resume - Runtime resume from suspend
1643 ret = clk_prepare_enable(priv->bus_clk); in xcan_runtime_resume()
1648 ret = clk_prepare_enable(priv->can_clk); in xcan_runtime_resume()
1651 clk_disable_unprepare(priv->bus_clk); in xcan_runtime_resume()
1707 { .compatible = "xlnx,zynq-can-1.0", .data = &xcan_zynq_data },
1708 { .compatible = "xlnx,axi-can-1.00.a", .data = &xcan_axi_data },
1709 { .compatible = "xlnx,canfd-1.0", .data = &xcan_canfd_data },
1710 { .compatible = "xlnx,canfd-2.0", .data = &xcan_canfd2_data },
1716 * xcan_probe - Platform registration call
1744 of_id = of_match_device(xcan_of_match, &pdev->dev); in xcan_probe()
1745 if (of_id && of_id->data) in xcan_probe()
1746 devtype = of_id->data; in xcan_probe()
1748 hw_tx_max_property = devtype->flags & XCAN_FLAG_TX_MAILBOXES ? in xcan_probe()
1749 "tx-mailbox-count" : "tx-fifo-depth"; in xcan_probe()
1751 ret = of_property_read_u32(pdev->dev.of_node, hw_tx_max_property, in xcan_probe()
1754 dev_err(&pdev->dev, "missing %s property\n", in xcan_probe()
1759 ret = of_property_read_u32(pdev->dev.of_node, "rx-fifo-depth", in xcan_probe()
1762 dev_err(&pdev->dev, in xcan_probe()
1763 "missing rx-fifo-depth property (mailbox mode is not supported)\n"); in xcan_probe()
1771 * is supported, we can have 2 frames in the FIFO and use TXFEMP in xcan_probe()
1772 * to determine if 1 or 2 frames have been sent. in xcan_probe()
1775 * FIFO, with watermark at 2 frames, it can happen that TXFWMEMP (less in xcan_probe()
1776 * than 2 frames in FIFO) is set anyway with no TXOK (a frame was in xcan_probe()
1777 * sent), which is not a sensible state - possibly TXFWMEMP is not in xcan_probe()
1785 if (!(devtype->flags & XCAN_FLAG_TX_MAILBOXES) && in xcan_probe()
1786 (devtype->flags & XCAN_FLAG_TXFEMP)) in xcan_probe()
1787 tx_max = min(hw_tx_max, 2U); in xcan_probe()
1796 return -ENOMEM; in xcan_probe()
1799 priv->dev = &pdev->dev; in xcan_probe()
1800 priv->can.bittiming_const = devtype->bittiming_const; in xcan_probe()
1801 priv->can.do_set_mode = xcan_do_set_mode; in xcan_probe()
1802 priv->can.do_get_berr_counter = xcan_get_berr_counter; in xcan_probe()
1803 priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | in xcan_probe()
1805 priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); in xcan_probe()
1806 if (IS_ERR(priv->rstc)) { in xcan_probe()
1807 dev_err(&pdev->dev, "Cannot get CAN reset.\n"); in xcan_probe()
1808 ret = PTR_ERR(priv->rstc); in xcan_probe()
1812 ret = reset_control_reset(priv->rstc); in xcan_probe()
1816 if (devtype->cantype == XAXI_CANFD) { in xcan_probe()
1817 priv->can.data_bittiming_const = in xcan_probe()
1819 priv->can.tdc_const = &xcan_tdc_const_canfd; in xcan_probe()
1822 if (devtype->cantype == XAXI_CANFD_2_0) { in xcan_probe()
1823 priv->can.data_bittiming_const = in xcan_probe()
1825 priv->can.tdc_const = &xcan_tdc_const_canfd2; in xcan_probe()
1828 if (devtype->cantype == XAXI_CANFD || in xcan_probe()
1829 devtype->cantype == XAXI_CANFD_2_0) { in xcan_probe()
1830 priv->can.ctrlmode_supported |= CAN_CTRLMODE_FD | in xcan_probe()
1832 priv->can.do_get_auto_tdcv = xcan_get_auto_tdcv; in xcan_probe()
1835 priv->reg_base = addr; in xcan_probe()
1836 priv->tx_max = tx_max; in xcan_probe()
1837 priv->devtype = *devtype; in xcan_probe()
1838 spin_lock_init(&priv->tx_lock); in xcan_probe()
1845 ndev->irq = ret; in xcan_probe()
1847 ndev->flags |= IFF_ECHO; /* We support local echo */ in xcan_probe()
1850 SET_NETDEV_DEV(ndev, &pdev->dev); in xcan_probe()
1851 ndev->netdev_ops = &xcan_netdev_ops; in xcan_probe()
1852 ndev->ethtool_ops = &xcan_ethtool_ops; in xcan_probe()
1855 priv->can_clk = devm_clk_get(&pdev->dev, "can_clk"); in xcan_probe()
1856 if (IS_ERR(priv->can_clk)) { in xcan_probe()
1857 ret = dev_err_probe(&pdev->dev, PTR_ERR(priv->can_clk), in xcan_probe()
1862 priv->bus_clk = devm_clk_get(&pdev->dev, devtype->bus_clk_name); in xcan_probe()
1863 if (IS_ERR(priv->bus_clk)) { in xcan_probe()
1864 ret = dev_err_probe(&pdev->dev, PTR_ERR(priv->bus_clk), in xcan_probe()
1869 transceiver = devm_phy_optional_get(&pdev->dev, NULL); in xcan_probe()
1872 dev_err_probe(&pdev->dev, ret, "failed to get phy\n"); in xcan_probe()
1875 priv->transceiver = transceiver; in xcan_probe()
1877 priv->write_reg = xcan_write_reg_le; in xcan_probe()
1878 priv->read_reg = xcan_read_reg_le; in xcan_probe()
1880 pm_runtime_enable(&pdev->dev); in xcan_probe()
1881 ret = pm_runtime_get_sync(&pdev->dev); in xcan_probe()
1888 if (priv->read_reg(priv, XCAN_SR_OFFSET) != XCAN_SR_CONFIG_MASK) { in xcan_probe()
1889 priv->write_reg = xcan_write_reg_be; in xcan_probe()
1890 priv->read_reg = xcan_read_reg_be; in xcan_probe()
1893 priv->can.clock.freq = clk_get_rate(priv->can_clk); in xcan_probe()
1895 netif_napi_add_weight(ndev, &priv->napi, xcan_rx_poll, rx_max); in xcan_probe()
1899 dev_err(&pdev->dev, "fail to register failed (err=%d)\n", ret); in xcan_probe()
1904 pm_runtime_put(&pdev->dev); in xcan_probe()
1906 if (priv->devtype.flags & XCAN_FLAG_CANFD_2) { in xcan_probe()
1907 priv->write_reg(priv, XCAN_AFR_2_ID_OFFSET, 0x00000000); in xcan_probe()
1908 priv->write_reg(priv, XCAN_AFR_2_MASK_OFFSET, 0x00000000); in xcan_probe()
1912 priv->reg_base, ndev->irq, priv->can.clock.freq, in xcan_probe()
1913 hw_tx_max, priv->tx_max); in xcan_probe()
1918 pm_runtime_put(priv->dev); in xcan_probe()
1919 pm_runtime_disable(&pdev->dev); in xcan_probe()
1921 reset_control_assert(priv->rstc); in xcan_probe()
1929 * xcan_remove - Unregister the device after releasing the resources
1941 pm_runtime_disable(&pdev->dev); in xcan_remove()
1942 reset_control_assert(priv->rstc); in xcan_remove()