Lines Matching +full:canfd +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Renesas R-Car CAN FD device driver
7 /* The R-Car CAN FD controller can operate in either one of the below two modes
8 * - CAN FD only mode
9 * - Classical CAN (CAN 2.0) only mode
16 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
62 #define RCANFD_GCTR_GSLPR BIT(2)
70 #define RCANFD_GSTS_GSLPSTS BIT(2)
73 /* Non-operational status */
74 #define RCANFD_GSTS_GNOPM (BIT(0) | BIT(1) | BIT(2) | BIT(3))
80 #define RCANFD_GERFL_THLES BIT(2)
88 ((gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0)))
95 (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8)))
98 (((x) >> (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8))) & \
113 /* RSCFDnCmCFG - Classical CAN only */
119 /* RSCFDnCFDCmNCFG - CAN FD only */
150 #define RCANFD_CCTR_CSLPR BIT(2)
162 #define RCANFD_CSTS_SLPSTS BIT(2)
182 #define RCANFD_CERFL_EPF BIT(2)
215 #define RCANFD_RFSTS_RFMLT BIT(2)
229 #define RCANFD_RFFDSTS_RFFDF BIT(2)
242 #define RCANFD_CFCC_CFTXIE BIT(2)
248 #define RCANFD_CFSTS_CFMLT BIT(2)
263 #define RCANFD_CFFDCSTS_CFFDF BIT(2)
301 #define RCANFD_GAFLCFG(ch) (0x009c + (0x04 * ((ch) / 2)))
396 /* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
402 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
409 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
421 /* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
432 /* R-Car Gen4 Classical and CAN FD mode specific register map */
439 /* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
449 /* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
455 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
463 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
479 /* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
495 #define RCANFD_CHANNELS_MASK BIT((RCANFD_NUM_CHANNELS) - 1)
513 RCANFD_CANFDCLK = 0, /* CANFD clock */
548 enum rcar_canfd_fcanclk fcan; /* CANFD or Ext clock */
559 .tseg1_min = 2,
561 .tseg2_min = 2,
572 .tseg1_min = 2,
574 .tseg2_min = 2,
587 .tseg2_min = 2,
596 .max_channels = 2,
597 .postdiv = 2,
603 .postdiv = 2,
608 .max_channels = 2,
616 return gpriv->info == &rcar_gen4_hw_info;
665 lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
667 *((u32 *)cf->data + i) =
668 rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
676 lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
678 rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
679 *((u32 *)cf->data + i));
693 u32 ch, val = gpriv->fdmode ? RCANFD_GEN4_FDCFG_FDOE
696 for_each_set_bit(ch, &gpriv->channels_mask,
697 gpriv->info->max_channels)
698 rcar_canfd_set_bit(gpriv->base, RCANFD_GEN4_FDCFG(ch),
701 if (gpriv->fdmode)
702 rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
705 rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
718 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
719 !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
721 dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
726 rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
727 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
731 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
732 (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
734 dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
739 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
745 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
746 rcar_canfd_clear_bit(gpriv->base,
749 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
754 err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
756 2, 500000);
758 dev_dbg(&gpriv->pdev->dev,
775 if (gpriv->fdmode)
780 if (gpriv->fcan != RCANFD_CANFDCLK)
783 rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
786 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
787 rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
789 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
804 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
809 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG(ch),
813 else if (gpriv->fdmode)
819 rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, rule_entry_index), 0);
821 rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, rule_entry_index), 0);
823 rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, rule_entry_index), 0);
825 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLP1(offset, rule_entry_index),
829 rcar_canfd_clear_bit(gpriv->base,
842 rfdc = 2; /* b010 - 8 messages Rx FIFO depth */
843 if (gpriv->fdmode)
844 rfpls = 7; /* b111 - Max 64 bytes payload */
846 rfpls = 0; /* b000 - Max 8 bytes payload */
850 rcar_canfd_write(gpriv->base, RCANFD_RFCC(gpriv, ridx), cfg);
865 cfm = 1; /* b01 - Transmit mode */
866 cfdc = 2; /* b010 - 8 messages Tx FIFO depth */
867 if (gpriv->fdmode)
868 cfpls = 7; /* b111 - Max 64 bytes payload */
870 cfpls = 0; /* b000 - Max 8 bytes payload */
875 rcar_canfd_write(gpriv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX), cfg);
877 if (gpriv->fdmode)
879 rcar_canfd_write(gpriv->base,
888 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
892 if (gpriv->fdmode)
895 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
902 rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
905 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
911 u32 ctr, ch = priv->channel;
914 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
922 rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
928 u32 ctr, ch = priv->channel;
935 rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
938 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
944 struct rcar_canfd_global *gpriv = priv->gpriv;
945 struct net_device_stats *stats = &ndev->stats;
946 u32 ch = priv->channel;
950 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
953 stats->tx_dropped++;
956 sts = rcar_canfd_read(priv->base,
960 stats->tx_dropped++;
961 rcar_canfd_write(priv->base,
966 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
969 stats->rx_dropped++;
970 rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
974 if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
985 rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
992 struct net_device_stats *stats = &ndev->stats;
995 u32 ch = priv->channel;
1002 stats->rx_dropped++;
1009 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
1010 cf->data[2] = CAN_ERR_PROT_UNSPEC;
1011 priv->can.can_stats.bus_error++;
1015 stats->tx_errors++;
1016 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
1020 stats->tx_errors++;
1021 cf->data[2] |= CAN_ERR_PROT_BIT0;
1025 stats->tx_errors++;
1026 cf->data[2] |= CAN_ERR_PROT_BIT1;
1030 stats->rx_errors++;
1031 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1035 stats->tx_errors++;
1036 cf->can_id |= CAN_ERR_ACK;
1037 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
1041 stats->rx_errors++;
1042 cf->data[2] |= CAN_ERR_PROT_FORM;
1046 stats->rx_errors++;
1047 cf->data[2] |= CAN_ERR_PROT_STUFF;
1051 priv->can.can_stats.arbitration_lost++;
1052 cf->can_id |= CAN_ERR_LOSTARB;
1053 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
1057 stats->rx_errors++;
1058 cf->can_id |= CAN_ERR_BUSERROR;
1062 priv->can.state = CAN_STATE_ERROR_WARNING;
1063 priv->can.can_stats.error_warning++;
1064 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1065 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
1067 cf->data[6] = txerr;
1068 cf->data[7] = rxerr;
1072 priv->can.state = CAN_STATE_ERROR_PASSIVE;
1073 priv->can.can_stats.error_passive++;
1074 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1075 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1077 cf->data[6] = txerr;
1078 cf->data[7] = rxerr;
1081 netdev_dbg(ndev, "Bus-off entry interrupt\n");
1083 priv->can.state = CAN_STATE_BUS_OFF;
1084 priv->can.can_stats.bus_off++;
1086 cf->can_id |= CAN_ERR_BUSOFF;
1091 stats->tx_errors++;
1092 cf->can_id |= CAN_ERR_PROT;
1093 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1097 rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1105 struct rcar_canfd_global *gpriv = priv->gpriv;
1106 struct net_device_stats *stats = &ndev->stats;
1109 u32 ch = priv->channel;
1114 sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1115 stats->tx_packets++;
1116 stats->tx_bytes += can_get_echo_skb(ndev, sent, NULL);
1118 spin_lock_irqsave(&priv->tx_lock, flags);
1119 priv->tx_tail++;
1120 sts = rcar_canfd_read(priv->base,
1128 if (priv->tx_head - priv->tx_tail <= unsent) {
1129 spin_unlock_irqrestore(&priv->tx_lock, flags);
1132 spin_unlock_irqrestore(&priv->tx_lock, flags);
1137 rcar_canfd_write(priv->base, RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
1143 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1144 struct net_device *ndev = priv->ndev;
1148 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1158 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1166 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1171 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1172 cc = rcar_canfd_read(priv->base, RCANFD_RFCC(gpriv, ridx));
1175 if (napi_schedule_prep(&priv->napi)) {
1177 rcar_canfd_clear_bit(priv->base,
1180 __napi_schedule(&priv->napi);
1190 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1204 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1215 struct net_device_stats *stats = &ndev->stats;
1216 enum can_state rx_state, tx_state, state = priv->can.state;
1226 if (state != priv->can.state) {
1228 state, priv->can.state, txerr, rxerr);
1231 stats->rx_dropped++;
1244 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1245 struct net_device *ndev = priv->ndev;
1249 sts = rcar_canfd_read(priv->base,
1259 rcar_canfd_handle_channel_tx(priv->gpriv, priv->channel);
1266 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1267 struct net_device *ndev = priv->ndev;
1272 cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1273 sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1280 if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
1281 priv->can.state != CAN_STATE_BUS_OFF))
1289 rcar_canfd_handle_channel_err(priv->gpriv, priv->channel);
1300 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1311 struct rcar_canfd_global *gpriv = priv->gpriv;
1312 const struct can_bittiming *bt = &priv->can.bittiming;
1313 const struct can_bittiming *dbt = &priv->can.data_bittiming;
1316 u32 ch = priv->channel;
1319 brp = bt->brp - 1;
1320 sjw = bt->sjw - 1;
1321 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1322 tseg2 = bt->phase_seg2 - 1;
1324 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1329 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1330 netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1334 brp = dbt->brp - 1;
1335 sjw = dbt->sjw - 1;
1336 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1337 tseg2 = dbt->phase_seg2 - 1;
1342 rcar_canfd_write(priv->base, RCANFD_F_DCFG(gpriv, ch), cfg);
1343 netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1359 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1360 netdev_dbg(priv->ndev,
1369 struct rcar_canfd_global *gpriv = priv->gpriv;
1370 int err = -EOPNOTSUPP;
1371 u32 sts, ch = priv->channel;
1379 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1383 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1384 (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1391 rcar_canfd_set_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1393 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1395 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1406 struct rcar_canfd_global *gpriv = priv->gpriv;
1409 err = phy_power_on(priv->transceiver);
1416 err = clk_prepare_enable(gpriv->can_clk);
1428 napi_enable(&priv->napi);
1435 napi_disable(&priv->napi);
1438 clk_disable_unprepare(gpriv->can_clk);
1440 phy_power_off(priv->transceiver);
1447 struct rcar_canfd_global *gpriv = priv->gpriv;
1449 u32 sts, ch = priv->channel;
1453 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1457 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1458 (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1465 rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1467 rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1470 priv->can.state = CAN_STATE_STOPPED;
1476 struct rcar_canfd_global *gpriv = priv->gpriv;
1480 napi_disable(&priv->napi);
1481 clk_disable_unprepare(gpriv->can_clk);
1483 phy_power_off(priv->transceiver);
1491 struct rcar_canfd_global *gpriv = priv->gpriv;
1492 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1495 u32 ch = priv->channel;
1500 if (cf->can_id & CAN_EFF_FLAG) {
1501 id = cf->can_id & CAN_EFF_MASK;
1504 id = cf->can_id & CAN_SFF_MASK;
1507 if (cf->can_id & CAN_RTR_FLAG)
1510 dlc = RCANFD_CFPTR_CFDLC(can_fd_len2dlc(cf->len));
1512 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_gen4(gpriv)) {
1513 rcar_canfd_write(priv->base,
1515 rcar_canfd_write(priv->base,
1521 if (cf->flags & CANFD_BRS)
1524 if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1528 rcar_canfd_write(priv->base,
1534 rcar_canfd_write(priv->base,
1536 rcar_canfd_write(priv->base,
1542 can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH, 0);
1544 spin_lock_irqsave(&priv->tx_lock, flags);
1545 priv->tx_head++;
1548 if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1551 /* Start Tx: Write 0xff to CFPC to increment the CPU-side
1554 rcar_canfd_write(priv->base,
1557 spin_unlock_irqrestore(&priv->tx_lock, flags);
1563 struct net_device_stats *stats = &priv->ndev->stats;
1564 struct rcar_canfd_global *gpriv = priv->gpriv;
1568 u32 ch = priv->channel;
1571 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_gen4(gpriv)) {
1572 id = rcar_canfd_read(priv->base, RCANFD_F_RFID(gpriv, ridx));
1573 dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(gpriv, ridx));
1575 sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(gpriv, ridx));
1577 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) &&
1579 skb = alloc_canfd_skb(priv->ndev, &cf);
1581 skb = alloc_can_skb(priv->ndev,
1584 id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1585 dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1586 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1590 stats->rx_dropped++;
1595 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1597 cf->can_id = id & CAN_SFF_MASK;
1599 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1601 cf->len = can_fd_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1603 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1606 cf->flags |= CANFD_ESI;
1607 netdev_dbg(priv->ndev, "ESI Error\n");
1611 cf->can_id |= CAN_RTR_FLAG;
1614 cf->flags |= CANFD_BRS;
1619 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1621 cf->can_id |= CAN_RTR_FLAG;
1628 /* Write 0xff to RFPC to increment the CPU-side
1631 rcar_canfd_write(priv->base, RCANFD_RFPCTR(gpriv, ridx), 0xff);
1633 if (!(cf->can_id & CAN_RTR_FLAG))
1634 stats->rx_bytes += cf->len;
1635 stats->rx_packets++;
1643 struct rcar_canfd_global *gpriv = priv->gpriv;
1646 u32 ch = priv->channel;
1650 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1659 rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
1667 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx),
1686 return -EOPNOTSUPP;
1694 u32 val, ch = priv->channel;
1697 val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1698 bec->txerr = RCANFD_CSTS_TECCNT(val);
1699 bec->rxerr = RCANFD_CSTS_RECCNT(val);
1717 const struct rcar_canfd_hw_info *info = gpriv->info;
1718 struct platform_device *pdev = gpriv->pdev;
1719 struct device *dev = &pdev->dev;
1722 int err = -ENODEV;
1726 return -ENOMEM;
1730 ndev->netdev_ops = &rcar_canfd_netdev_ops;
1731 ndev->ethtool_ops = &rcar_canfd_ethtool_ops;
1732 ndev->flags |= IFF_ECHO;
1733 priv->ndev = ndev;
1734 priv->base = gpriv->base;
1735 priv->transceiver = transceiver;
1736 priv->channel = ch;
1737 priv->gpriv = gpriv;
1739 priv->can.bitrate_max = transceiver->attrs.max_link_rate;
1740 priv->can.clock.freq = fcan_freq;
1741 dev_info(dev, "can_clk rate is %u\n", priv->can.clock.freq);
1743 if (info->multi_channel_irqs) {
1760 irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_err",
1763 err = -ENOMEM;
1774 irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_trx",
1777 err = -ENOMEM;
1790 if (gpriv->fdmode) {
1791 priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1792 priv->can.data_bittiming_const =
1799 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1802 priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1803 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1806 priv->can.do_set_mode = rcar_canfd_do_set_mode;
1807 priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1810 netif_napi_add_weight(ndev, &priv->napi, rcar_canfd_rx_poll,
1812 spin_lock_init(&priv->tx_lock);
1813 gpriv->ch[priv->channel] = priv;
1819 dev_info(dev, "device registered (channel %u)\n", priv->channel);
1823 netif_napi_del(&priv->napi);
1831 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1834 unregister_candev(priv->ndev);
1835 netif_napi_del(&priv->napi);
1836 free_candev(priv->ndev);
1844 struct device *dev = &pdev->dev;
1853 bool fdmode = true; /* CAN FD only mode - default */
1859 if (of_property_read_bool(dev->of_node, "renesas,no-can-fd"))
1862 for (i = 0; i < info->max_channels; ++i) {
1864 of_child = of_get_child_by_name(dev->of_node, name);
1875 if (info->shared_global_irqs) {
1904 return -ENOMEM;
1906 gpriv->pdev = pdev;
1907 gpriv->channels_mask = channels_mask;
1908 gpriv->fdmode = fdmode;
1909 gpriv->info = info;
1911 gpriv->rstc1 = devm_reset_control_get_optional_exclusive(dev, "rstp_n");
1912 if (IS_ERR(gpriv->rstc1))
1913 return dev_err_probe(dev, PTR_ERR(gpriv->rstc1),
1916 gpriv->rstc2 = devm_reset_control_get_optional_exclusive(dev, "rstc_n");
1917 if (IS_ERR(gpriv->rstc2))
1918 return dev_err_probe(dev, PTR_ERR(gpriv->rstc2),
1922 gpriv->clkp = devm_clk_get(dev, "fck");
1923 if (IS_ERR(gpriv->clkp))
1924 return dev_err_probe(dev, PTR_ERR(gpriv->clkp),
1928 * CANFD clock
1930 gpriv->can_clk = devm_clk_get(dev, "can_clk");
1931 if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1932 gpriv->can_clk = devm_clk_get(dev, "canfd");
1933 if (IS_ERR(gpriv->can_clk))
1934 return dev_err_probe(dev, PTR_ERR(gpriv->can_clk),
1935 "cannot get canfd clock\n");
1937 gpriv->fcan = RCANFD_CANFDCLK;
1940 gpriv->fcan = RCANFD_EXTCLK;
1942 fcan_freq = clk_get_rate(gpriv->can_clk);
1944 if (gpriv->fcan == RCANFD_CANFDCLK)
1945 /* CANFD clock is further divided by (1/2) within the IP */
1946 fcan_freq /= info->postdiv;
1953 gpriv->base = addr;
1956 if (info->shared_global_irqs) {
1959 "canfd.ch_int", gpriv);
1967 0, "canfd.g_int", gpriv);
1976 "canfd.g_recc", gpriv);
1986 "canfd.g_err", gpriv);
1994 err = reset_control_reset(gpriv->rstc1);
1997 err = reset_control_reset(gpriv->rstc2);
1999 reset_control_assert(gpriv->rstc1);
2004 err = clk_prepare_enable(gpriv->clkp);
2021 for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2037 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
2041 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
2042 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
2048 for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2057 gpriv->fcan, gpriv->fdmode);
2061 for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels)
2066 clk_disable_unprepare(gpriv->clkp);
2068 reset_control_assert(gpriv->rstc1);
2069 reset_control_assert(gpriv->rstc2);
2082 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2083 rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
2088 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
2089 clk_disable_unprepare(gpriv->clkp);
2090 reset_control_assert(gpriv->rstc1);
2091 reset_control_assert(gpriv->rstc2);
2108 { .compatible = "renesas,r8a779a0-canfd", .data = &rcar_gen4_hw_info },
2109 { .compatible = "renesas,rcar-gen3-canfd", .data = &rcar_gen3_hw_info },
2110 { .compatible = "renesas,rcar-gen4-canfd", .data = &rcar_gen4_hw_info },
2111 { .compatible = "renesas,rzg2l-canfd", .data = &rzg2l_hw_info },
2131 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");