Lines Matching +full:64 +full:- +full:byte
1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/mtd/spi-nor.h>
67 * struct spansion_nor_params - Spansion private parameters.
76 * spansion_nor_clear_sr() - Clear the Status Register.
81 const struct spansion_nor_params *priv_params = nor->params->priv; in spansion_nor_clear_sr()
84 if (nor->spimem) { in spansion_nor_clear_sr()
85 struct spi_mem_op op = SPANSION_OP(priv_params->clsr); in spansion_nor_clear_sr()
87 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto); in spansion_nor_clear_sr()
89 ret = spi_mem_exec_op(nor->spimem, &op); in spansion_nor_clear_sr()
96 dev_dbg(nor->dev, "error %d clearing SR\n", ret); in spansion_nor_clear_sr()
101 struct spi_nor_flash_parameter *params = nor->params; in cypress_nor_sr_ready_and_clear_reg()
103 CYPRESS_NOR_RD_ANY_REG_OP(params->addr_mode_nbytes, addr, in cypress_nor_sr_ready_and_clear_reg()
104 0, nor->bouncebuf); in cypress_nor_sr_ready_and_clear_reg()
107 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) { in cypress_nor_sr_ready_and_clear_reg()
108 op.addr.nbytes = nor->addr_nbytes; in cypress_nor_sr_ready_and_clear_reg()
109 op.dummy.nbytes = params->rdsr_dummy; in cypress_nor_sr_ready_and_clear_reg()
113 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_sr_ready_and_clear_reg()
117 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { in cypress_nor_sr_ready_and_clear_reg()
118 if (nor->bouncebuf[0] & SR_E_ERR) in cypress_nor_sr_ready_and_clear_reg()
119 dev_err(nor->dev, "Erase Error occurred\n"); in cypress_nor_sr_ready_and_clear_reg()
121 dev_err(nor->dev, "Programming Error occurred\n"); in cypress_nor_sr_ready_and_clear_reg()
129 return -EIO; in cypress_nor_sr_ready_and_clear_reg()
132 return !(nor->bouncebuf[0] & SR_WIP); in cypress_nor_sr_ready_and_clear_reg()
135 * cypress_nor_sr_ready_and_clear() - Query the Status Register of each die by
140 * Return: 1 if ready, 0 if not ready, -errno on errors.
144 struct spi_nor_flash_parameter *params = nor->params; in cypress_nor_sr_ready_and_clear()
149 for (i = 0; i < params->n_dice; i++) { in cypress_nor_sr_ready_and_clear()
150 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_STR1; in cypress_nor_sr_ready_and_clear()
164 u8 *buf = nor->bouncebuf; in cypress_nor_set_memlat()
166 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; in cypress_nor_set_memlat()
171 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_set_memlat()
182 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in cypress_nor_set_memlat()
186 nor->read_dummy = 24; in cypress_nor_set_memlat()
194 u8 *buf = nor->bouncebuf; in cypress_nor_set_octal_dtr_bits()
199 CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes, in cypress_nor_set_octal_dtr_bits()
202 return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in cypress_nor_set_octal_dtr_bits()
207 const struct spi_nor_flash_parameter *params = nor->params; in cypress_nor_octal_dtr_en()
208 u8 *buf = nor->bouncebuf; in cypress_nor_octal_dtr_en()
212 for (i = 0; i < params->n_dice; i++) { in cypress_nor_octal_dtr_en()
213 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR2; in cypress_nor_octal_dtr_en()
218 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; in cypress_nor_octal_dtr_en()
225 ret = spi_nor_read_id(nor, nor->addr_nbytes, 3, buf, in cypress_nor_octal_dtr_en()
228 dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret); in cypress_nor_octal_dtr_en()
232 if (memcmp(buf, nor->info->id, nor->info->id_len)) in cypress_nor_octal_dtr_en()
233 return -EINVAL; in cypress_nor_octal_dtr_en()
241 u8 *buf = nor->bouncebuf; in cypress_nor_set_single_spi_bits()
244 * The register is 1-byte wide, but 1-byte transactions are not allowed in cypress_nor_set_single_spi_bits()
245 * in 8D-8D-8D mode. Since there is no register at the next location, in cypress_nor_set_single_spi_bits()
251 CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, addr, 2, buf); in cypress_nor_set_single_spi_bits()
257 const struct spi_nor_flash_parameter *params = nor->params; in cypress_nor_octal_dtr_dis()
258 u8 *buf = nor->bouncebuf; in cypress_nor_octal_dtr_dis()
262 for (i = 0; i < params->n_dice; i++) { in cypress_nor_octal_dtr_dis()
263 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5; in cypress_nor_octal_dtr_dis()
272 dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret); in cypress_nor_octal_dtr_dis()
276 if (memcmp(buf, nor->info->id, nor->info->id_len)) in cypress_nor_octal_dtr_dis()
277 return -EINVAL; in cypress_nor_octal_dtr_dis()
285 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes; in cypress_nor_quad_enable_volatile_reg()
291 nor->bouncebuf); in cypress_nor_quad_enable_volatile_reg()
293 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_quad_enable_volatile_reg()
297 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN) in cypress_nor_quad_enable_volatile_reg()
301 nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN; in cypress_nor_quad_enable_volatile_reg()
304 nor->bouncebuf); in cypress_nor_quad_enable_volatile_reg()
305 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto); in cypress_nor_quad_enable_volatile_reg()
309 cfr1v_written = nor->bouncebuf[0]; in cypress_nor_quad_enable_volatile_reg()
314 nor->bouncebuf); in cypress_nor_quad_enable_volatile_reg()
315 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_quad_enable_volatile_reg()
319 if (nor->bouncebuf[0] != cfr1v_written) { in cypress_nor_quad_enable_volatile_reg()
320 dev_err(nor->dev, "CFR1: Read back test failed\n"); in cypress_nor_quad_enable_volatile_reg()
321 return -EIO; in cypress_nor_quad_enable_volatile_reg()
328 * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile
333 * to a risk of the non-volatile registers corruption by power interrupt. This
335 * bit in the CFR1 non-volatile in advance (typically by a Flash programmer
337 * also set during Flash power-up.
339 * Return: 0 on success, -errno otherwise.
343 struct spi_nor_flash_parameter *params = nor->params; in cypress_nor_quad_enable_volatile()
348 for (i = 0; i < params->n_dice; i++) { in cypress_nor_quad_enable_volatile()
349 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1; in cypress_nor_quad_enable_volatile()
359 * cypress_nor_determine_addr_mode_by_sr1() - Determine current address mode
360 * (3 or 4-byte) by querying status
367 * from RDSR1(no address), RDAR(3-byte address), and RDAR(4-byte address).
369 * Return: 0 on success, -errno otherwise.
376 nor->bouncebuf); in cypress_nor_determine_addr_mode_by_sr1()
380 ret = spi_nor_read_sr(nor, &nor->bouncebuf[1]); in cypress_nor_determine_addr_mode_by_sr1()
384 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_determine_addr_mode_by_sr1()
388 is3byte = (nor->bouncebuf[0] == nor->bouncebuf[1]); in cypress_nor_determine_addr_mode_by_sr1()
392 nor->bouncebuf); in cypress_nor_determine_addr_mode_by_sr1()
393 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_determine_addr_mode_by_sr1()
397 is4byte = (nor->bouncebuf[0] == nor->bouncebuf[1]); in cypress_nor_determine_addr_mode_by_sr1()
400 return -EIO; in cypress_nor_determine_addr_mode_by_sr1()
410 * cypress_nor_set_addr_mode_nbytes() - Set the number of address bytes mode of
415 * query CFR2V[7] to confirm. If determination is failed, force enter to 4-byte
418 * Return: 0 on success, -errno otherwise.
427 * Read SR1 by RDSR1 and RDAR(3- AND 4-byte addr). Use write enable in cypress_nor_set_addr_mode_nbytes()
428 * that sets bit-1 in SR1. in cypress_nor_set_addr_mode_nbytes()
450 0, nor->bouncebuf); in cypress_nor_set_addr_mode_nbytes()
451 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_set_addr_mode_nbytes()
455 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR2_ADRBYT) { in cypress_nor_set_addr_mode_nbytes()
463 nor->params->addr_nbytes = addr_mode; in cypress_nor_set_addr_mode_nbytes()
464 nor->params->addr_mode_nbytes = addr_mode; in cypress_nor_set_addr_mode_nbytes()
470 * cypress_nor_get_page_size() - Get flash page size configuration.
477 * Return: 0 on success, -errno otherwise.
482 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, in cypress_nor_get_page_size()
483 0, 0, nor->bouncebuf); in cypress_nor_get_page_size()
484 struct spi_nor_flash_parameter *params = nor->params; in cypress_nor_get_page_size()
489 * Use the minimum common page size configuration. Programming 256-byte in cypress_nor_get_page_size()
490 * under 512-byte page size configuration is safe. in cypress_nor_get_page_size()
492 params->page_size = 256; in cypress_nor_get_page_size()
493 for (i = 0; i < params->n_dice; i++) { in cypress_nor_get_page_size()
494 op.addr.val = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR3; in cypress_nor_get_page_size()
496 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in cypress_nor_get_page_size()
500 if (!(nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ)) in cypress_nor_get_page_size()
504 params->page_size = 512; in cypress_nor_get_page_size()
512 * Programming is supported only in 16-byte ECC data unit granularity. in cypress_nor_ecc_init()
513 * Byte-programming, bit-walking, or multiple program operations to the in cypress_nor_ecc_init()
516 nor->params->writesize = 16; in cypress_nor_ecc_init()
517 nor->flags |= SNOR_F_ECC; in cypress_nor_ecc_init()
534 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes, in s25fs256t_post_bfpt_fixup()
536 nor->bouncebuf); in s25fs256t_post_bfpt_fixup()
537 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto); in s25fs256t_post_bfpt_fixup()
542 if (nor->bouncebuf[0]) in s25fs256t_post_bfpt_fixup()
543 return -ENODEV; in s25fs256t_post_bfpt_fixup()
550 struct spi_nor_flash_parameter *params = nor->params; in s25fs256t_post_sfdp_fixup()
557 params->vreg_offset = devm_kmalloc(nor->dev, sizeof(u32), GFP_KERNEL); in s25fs256t_post_sfdp_fixup()
558 if (!params->vreg_offset) in s25fs256t_post_sfdp_fixup()
559 return -ENOMEM; in s25fs256t_post_sfdp_fixup()
561 params->vreg_offset[0] = SPINOR_REG_CYPRESS_VREG; in s25fs256t_post_sfdp_fixup()
562 params->n_dice = 1; in s25fs256t_post_sfdp_fixup()
565 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4; in s25fs256t_post_sfdp_fixup()
566 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4], in s25fs256t_post_sfdp_fixup()
598 nor->params->quad_enable = cypress_nor_quad_enable_volatile; in s25hx_t_post_bfpt_fixup()
605 struct spi_nor_flash_parameter *params = nor->params; in s25hx_t_post_sfdp_fixup()
606 struct spi_nor_erase_type *erase_type = params->erase_map.erase_type; in s25hx_t_post_sfdp_fixup()
609 if (!params->n_dice || !params->vreg_offset) { in s25hx_t_post_sfdp_fixup()
610 dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n", in s25hx_t_post_sfdp_fixup()
612 return -EOPNOTSUPP; in s25hx_t_post_sfdp_fixup()
616 if (params->size == SZ_256M) in s25hx_t_post_sfdp_fixup()
617 params->n_dice = 2; in s25hx_t_post_sfdp_fixup()
620 * In some parts, 3byte erase opcodes are advertised by 4BAIT. in s25hx_t_post_sfdp_fixup()
621 * Convert them to 4byte erase opcodes. in s25hx_t_post_sfdp_fixup()
641 struct spi_nor_flash_parameter *params = nor->params; in s25hx_t_late_init()
644 params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; in s25hx_t_late_init()
645 params->ready = cypress_nor_sr_ready_and_clear; in s25hx_t_late_init()
658 * cypress_nor_set_octal_dtr() - Enable or disable octal DTR on Cypress flashes.
665 * Return: 0 on success, -errno otherwise.
675 struct spi_nor_flash_parameter *params = nor->params; in s28hx_t_post_sfdp_fixup()
677 if (!params->n_dice || !params->vreg_offset) { in s28hx_t_post_sfdp_fixup()
678 dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n", in s28hx_t_post_sfdp_fixup()
680 return -EOPNOTSUPP; in s28hx_t_post_sfdp_fixup()
684 if (params->size == SZ_256M) in s28hx_t_post_sfdp_fixup()
685 params->n_dice = 2; in s28hx_t_post_sfdp_fixup()
689 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. in s28hx_t_post_sfdp_fixup()
691 if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0) in s28hx_t_post_sfdp_fixup()
692 params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode = in s28hx_t_post_sfdp_fixup()
695 /* This flash is also missing the 4-byte Page Program opcode bit. */ in s28hx_t_post_sfdp_fixup()
696 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP], in s28hx_t_post_sfdp_fixup()
702 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR], in s28hx_t_post_sfdp_fixup()
710 params->rdsr_addr_nbytes = 4; in s28hx_t_post_sfdp_fixup()
724 struct spi_nor_flash_parameter *params = nor->params; in s28hx_t_late_init()
726 params->set_octal_dtr = cypress_nor_set_octal_dtr; in s28hx_t_late_init()
727 params->ready = cypress_nor_sr_ready_and_clear; in s28hx_t_late_init()
745 * The S25FS-S chip family reports 512-byte pages in BFPT but in s25fs_s_nor_post_bfpt_fixups()
750 nor->params->page_size = 256; in s25fs_s_nor_post_bfpt_fixups()
760 /* Spansion/Cypress -- single (large) sector size only, at least
763 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64)
765 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128)
767 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64)
771 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256)
780 { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512)
789 { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256)
797 { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512)
805 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) },
806 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) },
807 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64)
811 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256)
815 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8) },
816 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16) },
817 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32) },
818 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64) },
819 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128) },
820 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8)
823 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16)
826 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32)
829 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128)
832 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32)
835 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64)
837 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128)
839 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8)
841 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16)
843 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128)
846 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256)
849 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512)
912 * spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the
916 * Return: 1 if ready, 0 if not ready, -errno on errors.
922 ret = spi_nor_read_sr(nor, nor->bouncebuf); in spansion_nor_sr_ready_and_clear()
926 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) { in spansion_nor_sr_ready_and_clear()
927 if (nor->bouncebuf[0] & SR_E_ERR) in spansion_nor_sr_ready_and_clear()
928 dev_err(nor->dev, "Erase Error occurred\n"); in spansion_nor_sr_ready_and_clear()
930 dev_err(nor->dev, "Programming Error occurred\n"); in spansion_nor_sr_ready_and_clear()
944 return -EIO; in spansion_nor_sr_ready_and_clear()
947 return !(nor->bouncebuf[0] & SR_WIP); in spansion_nor_sr_ready_and_clear()
952 struct spi_nor_flash_parameter *params = nor->params; in spansion_nor_late_init()
954 u8 mfr_flags = nor->info->mfr_flags; in spansion_nor_late_init()
956 if (params->size > SZ_16M) { in spansion_nor_late_init()
957 nor->flags |= SNOR_F_4B_OPCODES; in spansion_nor_late_init()
958 /* No small sector erase for 4-byte command set */ in spansion_nor_late_init()
959 nor->erase_opcode = SPINOR_OP_SE; in spansion_nor_late_init()
960 nor->mtd.erasesize = nor->info->sector_size; in spansion_nor_late_init()
964 priv_params = devm_kmalloc(nor->dev, sizeof(*priv_params), in spansion_nor_late_init()
967 return -ENOMEM; in spansion_nor_late_init()
970 priv_params->clsr = SPINOR_OP_CLSR; in spansion_nor_late_init()
972 priv_params->clsr = SPINOR_OP_CLPEF; in spansion_nor_late_init()
974 params->priv = priv_params; in spansion_nor_late_init()
975 params->ready = spansion_nor_sr_ready_and_clear; in spansion_nor_late_init()