mtd/spi-nor/sfdp.h

1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SFDP_DWORD(i)		((i) - 1)
22 /* JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs. */
23 #define BFPT_DWORD_MAX		20
34 #define BFPT_DWORD1_FAST_READ_1_1_2		BIT(16)
39 #define BFPT_DWORD1_DTR				BIT(19)
40 #define BFPT_DWORD1_FAST_READ_1_2_2		BIT(20)
41 #define BFPT_DWORD1_FAST_READ_1_4_4		BIT(21)
42 #define BFPT_DWORD1_FAST_READ_1_1_4		BIT(22)
45 #define BFPT_DWORD5_FAST_READ_2_2_2		BIT(0)
46 #define BFPT_DWORD5_FAST_READ_4_4_4		BIT(4)
57  * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4
60  * - 001b: QE is bit 1 of status register 2. It is set via Write Status with
61  *         two data bytes where bit 1 of the second byte is one.
63  *         Writing only one byte to the status register has the side-effect of
64  *         clearing status register 2, including the QE bit. The 100b code is
67  * - 010b: QE is bit 6 of status register 1. It is set via Write Status with
68  *         one data byte where bit 6 is one.
70  * - 011b: QE is bit 7 of status register 2. It is set via Write status
71  *         register 2 instruction 3Eh with one data byte where bit 7 is one.
74  * - 100b: QE is bit 1 of status register 2. It is set via Write Status with
75  *         two data bytes where bit 1 of the second byte is one.
79  * - 101b: QE is bit 1 of status register 2. Status register 1 is read using
82  *         two data bytes where bit 1 of the second byte is one.
85 #define BFPT_DWORD15_QER_MASK			GENMASK(22, 20)
86 #define BFPT_DWORD15_QER_NONE			(0x0UL << 20) /* Micron */
87 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY		(0x1UL << 20)
88 #define BFPT_DWORD15_QER_SR1_BIT6		(0x2UL << 20) /* Macronix */
89 #define BFPT_DWORD15_QER_SR2_BIT7		(0x3UL << 20)
90 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD		(0x4UL << 20)
91 #define BFPT_DWORD15_QER_SR2_BIT1		(0x5UL << 20) /* Spansion */
94 #define BFPT_DWORD16_EN4B_ALWAYS_4B		BIT(30)
95 #define BFPT_DWORD16_EN4B_4B_OPCODES		BIT(29)
96 #define BFPT_DWORD16_EN4B_16BIT_NV_CR		BIT(28)
97 #define BFPT_DWORD16_EN4B_BRWR			BIT(27)
98 #define BFPT_DWORD16_EN4B_WREAR			BIT(26)
99 #define BFPT_DWORD16_EN4B_WREN_EN4B		BIT(25)
100 #define BFPT_DWORD16_EN4B_EN4B			BIT(24)
102 #define BFPT_DWORD16_EX4B_16BIT_NV_CR		BIT(18)
103 #define BFPT_DWORD16_EX4B_BRWR			BIT(17)
104 #define BFPT_DWORD16_EX4B_WREAR			BIT(16)
105 #define BFPT_DWORD16_EX4B_WREN_EX4B		BIT(15)
106 #define BFPT_DWORD16_EX4B_EX4B			BIT(14)
119 #define BFPT_DWORD16_SWRST_EN_RST		BIT(12)
125 #define BFPT_DWORD18_CMD_EXT_16B		(0x3UL << 29) /* 16-bit opcode */