Lines Matching refs:rnandc
216 struct rnandc { struct
244 static inline struct rnandc *to_rnandc(struct nand_controller *ctrl) in to_rnandc() argument
246 return container_of(ctrl, struct rnandc, controller); in to_rnandc()
259 static void rnandc_dis_correction(struct rnandc *rnandc) in rnandc_dis_correction() argument
263 control = readl_relaxed(rnandc->regs + CONTROL_REG); in rnandc_dis_correction()
265 writel_relaxed(control, rnandc->regs + CONTROL_REG); in rnandc_dis_correction()
268 static void rnandc_en_correction(struct rnandc *rnandc) in rnandc_en_correction() argument
272 control = readl_relaxed(rnandc->regs + CONTROL_REG); in rnandc_en_correction()
274 writel_relaxed(control, rnandc->regs + CONTROL_REG); in rnandc_en_correction()
277 static void rnandc_clear_status(struct rnandc *rnandc) in rnandc_clear_status() argument
279 writel_relaxed(0, rnandc->regs + INT_STATUS_REG); in rnandc_clear_status()
280 writel_relaxed(0, rnandc->regs + ECC_STAT_REG); in rnandc_clear_status()
281 writel_relaxed(0, rnandc->regs + ECC_CNT_REG); in rnandc_clear_status()
284 static void rnandc_dis_interrupts(struct rnandc *rnandc) in rnandc_dis_interrupts() argument
286 writel_relaxed(0, rnandc->regs + INT_MASK_REG); in rnandc_dis_interrupts()
289 static void rnandc_en_interrupts(struct rnandc *rnandc, u32 val) in rnandc_en_interrupts() argument
291 if (!rnandc->use_polling) in rnandc_en_interrupts()
292 writel_relaxed(val, rnandc->regs + INT_MASK_REG); in rnandc_en_interrupts()
295 static void rnandc_clear_fifo(struct rnandc *rnandc) in rnandc_clear_fifo() argument
297 writel_relaxed(FIFO_INIT, rnandc->regs + FIFO_INIT_REG); in rnandc_clear_fifo()
303 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_select_target() local
306 if (chip == rnandc->selected_chip && die_nr == rnand->selected_die) in rnandc_select_target()
309 rnandc_clear_status(rnandc); in rnandc_select_target()
310 writel_relaxed(MEM_CTRL_CS(cs) | MEM_CTRL_DIS_WP(cs), rnandc->regs + MEM_CTRL_REG); in rnandc_select_target()
311 writel_relaxed(rnand->control, rnandc->regs + CONTROL_REG); in rnandc_select_target()
312 writel_relaxed(rnand->ecc_ctrl, rnandc->regs + ECC_CTRL_REG); in rnandc_select_target()
313 writel_relaxed(rnand->timings_asyn, rnandc->regs + TIMINGS_ASYN_REG); in rnandc_select_target()
314 writel_relaxed(rnand->tim_seq0, rnandc->regs + TIM_SEQ0_REG); in rnandc_select_target()
315 writel_relaxed(rnand->tim_seq1, rnandc->regs + TIM_SEQ1_REG); in rnandc_select_target()
316 writel_relaxed(rnand->tim_gen_seq0, rnandc->regs + TIM_GEN_SEQ0_REG); in rnandc_select_target()
317 writel_relaxed(rnand->tim_gen_seq1, rnandc->regs + TIM_GEN_SEQ1_REG); in rnandc_select_target()
318 writel_relaxed(rnand->tim_gen_seq2, rnandc->regs + TIM_GEN_SEQ2_REG); in rnandc_select_target()
319 writel_relaxed(rnand->tim_gen_seq3, rnandc->regs + TIM_GEN_SEQ3_REG); in rnandc_select_target()
321 rnandc->selected_chip = chip; in rnandc_select_target()
325 static void rnandc_trigger_op(struct rnandc *rnandc, struct rnandc_op *rop) in rnandc_trigger_op() argument
327 writel_relaxed(rop->addr0_col, rnandc->regs + ADDR0_COL_REG); in rnandc_trigger_op()
328 writel_relaxed(rop->addr0_row, rnandc->regs + ADDR0_ROW_REG); in rnandc_trigger_op()
329 writel_relaxed(rop->addr1_col, rnandc->regs + ADDR1_COL_REG); in rnandc_trigger_op()
330 writel_relaxed(rop->addr1_row, rnandc->regs + ADDR1_ROW_REG); in rnandc_trigger_op()
331 writel_relaxed(rop->ecc_offset, rnandc->regs + ECC_OFFSET_REG); in rnandc_trigger_op()
332 writel_relaxed(rop->gen_seq_ctrl, rnandc->regs + GEN_SEQ_CTRL_REG); in rnandc_trigger_op()
333 writel_relaxed(DATA_SIZE(rop->len), rnandc->regs + DATA_SIZE_REG); in rnandc_trigger_op()
334 writel_relaxed(rop->command, rnandc->regs + COMMAND_REG); in rnandc_trigger_op()
337 static void rnandc_trigger_dma(struct rnandc *rnandc) in rnandc_trigger_dma() argument
341 DMA_CTRL_START, rnandc->regs + DMA_CTRL_REG); in rnandc_trigger_dma()
346 struct rnandc *rnandc = private; in rnandc_irq_handler() local
348 rnandc_dis_interrupts(rnandc); in rnandc_irq_handler()
349 complete(&rnandc->complete); in rnandc_irq_handler()
354 static int rnandc_wait_end_of_op(struct rnandc *rnandc, in rnandc_wait_end_of_op() argument
362 ret = readl_poll_timeout(rnandc->regs + STATUS_REG, status, in rnandc_wait_end_of_op()
366 dev_err(rnandc->dev, "Operation timed out, status: 0x%08x\n", in rnandc_wait_end_of_op()
372 static int rnandc_wait_end_of_io(struct rnandc *rnandc, in rnandc_wait_end_of_io() argument
378 if (rnandc->use_polling) { in rnandc_wait_end_of_io()
383 ret = readl_poll_timeout(rnandc->regs + INT_STATUS_REG, status, in rnandc_wait_end_of_io()
388 ret = wait_for_completion_timeout(&rnandc->complete, in rnandc_wait_end_of_io()
402 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_read_page_hw_ecc() local
421 rnandc_clear_status(rnandc); in rnandc_read_page_hw_ecc()
422 reinit_completion(&rnandc->complete); in rnandc_read_page_hw_ecc()
423 rnandc_en_interrupts(rnandc, INT_DMA_ENDED); in rnandc_read_page_hw_ecc()
424 rnandc_en_correction(rnandc); in rnandc_read_page_hw_ecc()
427 dma_addr = dma_map_single(rnandc->dev, rnandc->buf, mtd->writesize, in rnandc_read_page_hw_ecc()
429 writel(dma_addr, rnandc->regs + DMA_ADDR_LOW_REG); in rnandc_read_page_hw_ecc()
430 writel(mtd->writesize, rnandc->regs + DMA_CNT_REG); in rnandc_read_page_hw_ecc()
431 writel(DMA_TLVL_MAX, rnandc->regs + DMA_TLVL_REG); in rnandc_read_page_hw_ecc()
433 rnandc_trigger_op(rnandc, &rop); in rnandc_read_page_hw_ecc()
434 rnandc_trigger_dma(rnandc); in rnandc_read_page_hw_ecc()
436 ret = rnandc_wait_end_of_io(rnandc, chip); in rnandc_read_page_hw_ecc()
437 dma_unmap_single(rnandc->dev, dma_addr, mtd->writesize, DMA_FROM_DEVICE); in rnandc_read_page_hw_ecc()
438 rnandc_dis_correction(rnandc); in rnandc_read_page_hw_ecc()
440 dev_err(rnandc->dev, "Read page operation never ending\n"); in rnandc_read_page_hw_ecc()
444 ecc_stat = readl_relaxed(rnandc->regs + ECC_STAT_REG); in rnandc_read_page_hw_ecc()
459 bf = nand_check_erased_ecc_chunk(rnandc->buf + off, in rnandc_read_page_hw_ecc()
473 bf = ECC_CNT(cs, readl_relaxed(rnandc->regs + ECC_CNT_REG)); in rnandc_read_page_hw_ecc()
482 memcpy(buf, rnandc->buf, mtd->writesize); in rnandc_read_page_hw_ecc()
490 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_read_subpage_hw_ecc() local
515 rnandc_clear_status(rnandc); in rnandc_read_subpage_hw_ecc()
516 rnandc_en_correction(rnandc); in rnandc_read_subpage_hw_ecc()
517 rnandc_trigger_op(rnandc, &rop); in rnandc_read_subpage_hw_ecc()
519 while (!FIFO_STATE_C_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_read_subpage_hw_ecc()
522 while (FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_read_subpage_hw_ecc()
525 ioread32_rep(rnandc->regs + FIFO_DATA_REG, bufpoi + page_off, in rnandc_read_subpage_hw_ecc()
528 if (!FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) { in rnandc_read_subpage_hw_ecc()
529 dev_err(rnandc->dev, "Clearing residual data in the read FIFO\n"); in rnandc_read_subpage_hw_ecc()
530 rnandc_clear_fifo(rnandc); in rnandc_read_subpage_hw_ecc()
533 ret = rnandc_wait_end_of_op(rnandc, chip); in rnandc_read_subpage_hw_ecc()
534 rnandc_dis_correction(rnandc); in rnandc_read_subpage_hw_ecc()
536 dev_err(rnandc->dev, "Read subpage operation never ending\n"); in rnandc_read_subpage_hw_ecc()
540 ecc_stat = readl_relaxed(rnandc->regs + ECC_STAT_REG); in rnandc_read_subpage_hw_ecc()
567 bf = ECC_CNT(cs, readl_relaxed(rnandc->regs + ECC_CNT_REG)); in rnandc_read_subpage_hw_ecc()
582 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_write_page_hw_ecc() local
597 memcpy(rnandc->buf, buf, mtd->writesize); in rnandc_write_page_hw_ecc()
601 rnandc_clear_status(rnandc); in rnandc_write_page_hw_ecc()
602 reinit_completion(&rnandc->complete); in rnandc_write_page_hw_ecc()
603 rnandc_en_interrupts(rnandc, INT_MEM_RDY(cs)); in rnandc_write_page_hw_ecc()
604 rnandc_en_correction(rnandc); in rnandc_write_page_hw_ecc()
607 dma_addr = dma_map_single(rnandc->dev, (void *)rnandc->buf, mtd->writesize, in rnandc_write_page_hw_ecc()
609 writel(dma_addr, rnandc->regs + DMA_ADDR_LOW_REG); in rnandc_write_page_hw_ecc()
610 writel(mtd->writesize, rnandc->regs + DMA_CNT_REG); in rnandc_write_page_hw_ecc()
611 writel(DMA_TLVL_MAX, rnandc->regs + DMA_TLVL_REG); in rnandc_write_page_hw_ecc()
613 rnandc_trigger_op(rnandc, &rop); in rnandc_write_page_hw_ecc()
614 rnandc_trigger_dma(rnandc); in rnandc_write_page_hw_ecc()
616 ret = rnandc_wait_end_of_io(rnandc, chip); in rnandc_write_page_hw_ecc()
617 dma_unmap_single(rnandc->dev, dma_addr, mtd->writesize, DMA_TO_DEVICE); in rnandc_write_page_hw_ecc()
618 rnandc_dis_correction(rnandc); in rnandc_write_page_hw_ecc()
620 dev_err(rnandc->dev, "Write page operation never ending\n"); in rnandc_write_page_hw_ecc()
635 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_write_subpage_hw_ecc() local
655 rnandc_clear_status(rnandc); in rnandc_write_subpage_hw_ecc()
656 rnandc_en_correction(rnandc); in rnandc_write_subpage_hw_ecc()
657 rnandc_trigger_op(rnandc, &rop); in rnandc_write_subpage_hw_ecc()
659 while (FIFO_STATE_W_FULL(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_write_subpage_hw_ecc()
662 iowrite32_rep(rnandc->regs + FIFO_DATA_REG, bufpoi + page_off, in rnandc_write_subpage_hw_ecc()
665 while (!FIFO_STATE_W_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_write_subpage_hw_ecc()
668 ret = rnandc_wait_end_of_op(rnandc, chip); in rnandc_write_subpage_hw_ecc()
669 rnandc_dis_correction(rnandc); in rnandc_write_subpage_hw_ecc()
671 dev_err(rnandc->dev, "Write subpage operation never ending\n"); in rnandc_write_subpage_hw_ecc()
685 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_exec_op() local
835 dev_err(rnandc->dev, "Cannot handle more than one wait delay\n"); in rnandc_exec_op()
842 rnandc_trigger_op(rnandc, &rop); in rnandc_exec_op()
847 while (!FIFO_STATE_C_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_exec_op()
850 while (FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_exec_op()
853 ioread32_rep(rnandc->regs + FIFO_DATA_REG, rop.buf, words); in rnandc_exec_op()
855 last_bytes = readl_relaxed(rnandc->regs + FIFO_DATA_REG); in rnandc_exec_op()
860 if (!FIFO_STATE_R_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) { in rnandc_exec_op()
861 dev_warn(rnandc->dev, in rnandc_exec_op()
863 rnandc_clear_fifo(rnandc); in rnandc_exec_op()
866 while (FIFO_STATE_W_FULL(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_exec_op()
869 iowrite32_rep(rnandc->regs + FIFO_DATA_REG, rop.buf, in rnandc_exec_op()
875 writel_relaxed(last_bytes, rnandc->regs + FIFO_DATA_REG); in rnandc_exec_op()
878 while (!FIFO_STATE_W_EMPTY(readl(rnandc->regs + FIFO_STATE_REG))) in rnandc_exec_op()
882 ret = rnandc_wait_end_of_op(rnandc, chip); in rnandc_exec_op()
893 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_setup_interface() local
894 unsigned int period_ns = 1000000000 / rnandc->ext_clk_rate; in rnandc_setup_interface()
903 dev_err(rnandc->dev, "Read and write hold times must be identical\n"); in rnandc_setup_interface()
1011 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_hw_ecc_controller_init() local
1014 dev_err(rnandc->dev, "Unsupported page size\n"); in rnandc_hw_ecc_controller_init()
1029 dev_err(rnandc->dev, "Unsupported ECC chunk size\n"); in rnandc_hw_ecc_controller_init()
1059 dev_err(rnandc->dev, "Unsupported ECC strength\n"); in rnandc_hw_ecc_controller_init()
1080 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_ecc_init() local
1089 dev_err(rnandc->dev, "No minimum ECC strength\n"); in rnandc_ecc_init()
1114 struct rnandc *rnandc = to_rnandc(chip->controller); in rnandc_attach_chip() local
1124 dev_err(rnandc->dev, "Small page devices not supported\n"); in rnandc_attach_chip()
1144 dev_err(rnandc->dev, "Unsupported memory organization\n"); in rnandc_attach_chip()
1152 dev_err(rnandc->dev, "ECC initialization failed (%d)\n", ret); in rnandc_attach_chip()
1168 static int rnandc_alloc_dma_buf(struct rnandc *rnandc, in rnandc_alloc_dma_buf() argument
1176 list_for_each_entry_safe(entry, temp, &rnandc->chips, node) { in rnandc_alloc_dma_buf()
1182 if (rnandc->buf && rnandc->buf_sz < max_len) { in rnandc_alloc_dma_buf()
1183 devm_kfree(rnandc->dev, rnandc->buf); in rnandc_alloc_dma_buf()
1184 rnandc->buf = NULL; in rnandc_alloc_dma_buf()
1187 if (!rnandc->buf) { in rnandc_alloc_dma_buf()
1188 rnandc->buf_sz = max_len; in rnandc_alloc_dma_buf()
1189 rnandc->buf = devm_kmalloc(rnandc->dev, max_len, in rnandc_alloc_dma_buf()
1191 if (!rnandc->buf) in rnandc_alloc_dma_buf()
1198 static int rnandc_chip_init(struct rnandc *rnandc, struct device_node *np) in rnandc_chip_init() argument
1209 dev_err(rnandc->dev, "Invalid reg property (%d)\n", ret); in rnandc_chip_init()
1214 rnand = devm_kzalloc(rnandc->dev, struct_size(rnand, sels, nsels), in rnandc_chip_init()
1225 dev_err(rnandc->dev, "Incomplete reg property (%d)\n", ret); in rnandc_chip_init()
1230 dev_err(rnandc->dev, "Invalid reg property (%d)\n", cs); in rnandc_chip_init()
1234 if (test_and_set_bit(cs, &rnandc->assigned_cs)) { in rnandc_chip_init()
1235 dev_err(rnandc->dev, "CS %d already assigned\n", cs); in rnandc_chip_init()
1247 chip->controller = &rnandc->controller; in rnandc_chip_init()
1251 mtd->dev.parent = rnandc->dev; in rnandc_chip_init()
1253 dev_err(rnandc->dev, "Missing MTD label\n"); in rnandc_chip_init()
1259 dev_err(rnandc->dev, "Failed to scan the NAND chip (%d)\n", ret); in rnandc_chip_init()
1263 ret = rnandc_alloc_dma_buf(rnandc, mtd); in rnandc_chip_init()
1269 dev_err(rnandc->dev, "Failed to register MTD device (%d)\n", ret); in rnandc_chip_init()
1273 list_add_tail(&rnand->node, &rnandc->chips); in rnandc_chip_init()
1283 static void rnandc_chips_cleanup(struct rnandc *rnandc) in rnandc_chips_cleanup() argument
1289 list_for_each_entry_safe(entry, temp, &rnandc->chips, node) { in rnandc_chips_cleanup()
1298 static int rnandc_chips_init(struct rnandc *rnandc) in rnandc_chips_init() argument
1303 for_each_child_of_node(rnandc->dev->of_node, np) { in rnandc_chips_init()
1304 ret = rnandc_chip_init(rnandc, np); in rnandc_chips_init()
1314 rnandc_chips_cleanup(rnandc); in rnandc_chips_init()
1321 struct rnandc *rnandc; in rnandc_probe() local
1325 rnandc = devm_kzalloc(&pdev->dev, sizeof(*rnandc), GFP_KERNEL); in rnandc_probe()
1326 if (!rnandc) in rnandc_probe()
1329 rnandc->dev = &pdev->dev; in rnandc_probe()
1330 nand_controller_init(&rnandc->controller); in rnandc_probe()
1331 rnandc->controller.ops = &rnandc_ops; in rnandc_probe()
1332 INIT_LIST_HEAD(&rnandc->chips); in rnandc_probe()
1333 init_completion(&rnandc->complete); in rnandc_probe()
1335 rnandc->regs = devm_platform_ioremap_resource(pdev, 0); in rnandc_probe()
1336 if (IS_ERR(rnandc->regs)) in rnandc_probe()
1337 return PTR_ERR(rnandc->regs); in rnandc_probe()
1351 rnandc->ext_clk_rate = clk_get_rate(eclk); in rnandc_probe()
1354 rnandc_dis_interrupts(rnandc); in rnandc_probe()
1361 rnandc->use_polling = true; in rnandc_probe()
1364 "renesas-nand-controller", rnandc); in rnandc_probe()
1373 rnandc_clear_fifo(rnandc); in rnandc_probe()
1375 platform_set_drvdata(pdev, rnandc); in rnandc_probe()
1377 ret = rnandc_chips_init(rnandc); in rnandc_probe()
1391 struct rnandc *rnandc = platform_get_drvdata(pdev); in rnandc_remove() local
1393 rnandc_chips_cleanup(rnandc); in rnandc_remove()