Lines Matching refs:nandc
207 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg)) argument
567 static void free_bam_transaction(struct qcom_nand_controller *nandc) in free_bam_transaction() argument
569 struct bam_transaction *bam_txn = nandc->bam_txn; in free_bam_transaction()
571 devm_kfree(nandc->dev, bam_txn); in free_bam_transaction()
576 alloc_bam_transaction(struct qcom_nand_controller *nandc) in alloc_bam_transaction() argument
580 unsigned int num_cw = nandc->max_cwperpage; in alloc_bam_transaction()
589 bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL); in alloc_bam_transaction()
612 static void clear_bam_transaction(struct qcom_nand_controller *nandc) in clear_bam_transaction() argument
614 struct bam_transaction *bam_txn = nandc->bam_txn; in clear_bam_transaction()
616 if (!nandc->props->is_bam) in clear_bam_transaction()
630 sg_init_table(bam_txn->cmd_sgl, nandc->max_cwperpage * in clear_bam_transaction()
632 sg_init_table(bam_txn->data_sgl, nandc->max_cwperpage * in clear_bam_transaction()
668 static inline u32 nandc_read(struct qcom_nand_controller *nandc, int offset) in nandc_read() argument
670 return ioread32(nandc->base + offset); in nandc_read()
673 static inline void nandc_write(struct qcom_nand_controller *nandc, int offset, in nandc_write() argument
676 iowrite32(val, nandc->base + offset); in nandc_write()
679 static inline void nandc_read_buffer_sync(struct qcom_nand_controller *nandc, in nandc_read_buffer_sync() argument
682 if (!nandc->props->is_bam) in nandc_read_buffer_sync()
686 dma_sync_single_for_cpu(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
688 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
691 dma_sync_single_for_device(nandc->dev, nandc->reg_read_dma, in nandc_read_buffer_sync()
693 sizeof(*nandc->reg_read_buf), in nandc_read_buffer_sync()
754 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in nandc_set_reg() local
755 struct nandc_regs *regs = nandc->regs; in nandc_set_reg()
774 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in nandc_set_read_loc() local
778 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
783 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in nandc_set_read_loc()
815 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in update_rw_regs() local
844 if (!nandc->props->qpic_v2) in update_rw_regs()
860 static int prepare_bam_async_desc(struct qcom_nand_controller *nandc, in prepare_bam_async_desc() argument
868 struct bam_transaction *bam_txn = nandc->bam_txn; in prepare_bam_async_desc()
876 if (chan == nandc->cmd_chan) { in prepare_bam_async_desc()
882 } else if (chan == nandc->tx_chan) { in prepare_bam_async_desc()
897 ret = dma_map_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
899 dev_err(nandc->dev, "failure in mapping desc\n"); in prepare_bam_async_desc()
911 dev_err(nandc->dev, "failure in prep desc\n"); in prepare_bam_async_desc()
912 dma_unmap_sg(nandc->dev, sgl, sgl_cnt, desc->dir); in prepare_bam_async_desc()
920 if (chan == nandc->cmd_chan) in prepare_bam_async_desc()
925 list_add_tail(&desc->node, &nandc->desc_list); in prepare_bam_async_desc()
939 static int prep_bam_dma_desc_cmd(struct qcom_nand_controller *nandc, bool read, in prep_bam_dma_desc_cmd() argument
946 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_cmd()
954 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
956 reg_buf_dma_addr(nandc, in prep_bam_dma_desc_cmd()
960 nandc_reg_phys(nandc, reg_off + 4 * i), in prep_bam_dma_desc_cmd()
979 ret = prepare_bam_async_desc(nandc, nandc->cmd_chan, in prep_bam_dma_desc_cmd()
994 static int prep_bam_dma_desc_data(struct qcom_nand_controller *nandc, bool read, in prep_bam_dma_desc_data() argument
999 struct bam_transaction *bam_txn = nandc->bam_txn; in prep_bam_dma_desc_data()
1015 ret = prepare_bam_async_desc(nandc, nandc->tx_chan, in prep_bam_dma_desc_data()
1025 static int prep_adm_dma_desc(struct qcom_nand_controller *nandc, bool read, in prep_adm_dma_desc() argument
1053 ret = dma_map_sg(nandc->dev, sgl, 1, desc->dir); in prep_adm_dma_desc()
1064 slave_conf.src_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
1065 if (nandc->data_crci) { in prep_adm_dma_desc()
1066 periph_conf.crci = nandc->data_crci; in prep_adm_dma_desc()
1072 slave_conf.dst_addr = nandc->base_dma + reg_off; in prep_adm_dma_desc()
1073 if (nandc->cmd_crci) { in prep_adm_dma_desc()
1074 periph_conf.crci = nandc->cmd_crci; in prep_adm_dma_desc()
1080 ret = dmaengine_slave_config(nandc->chan, &slave_conf); in prep_adm_dma_desc()
1082 dev_err(nandc->dev, "failed to configure dma channel\n"); in prep_adm_dma_desc()
1086 dma_desc = dmaengine_prep_slave_sg(nandc->chan, sgl, 1, dir_eng, 0); in prep_adm_dma_desc()
1088 dev_err(nandc->dev, "failed to prepare desc\n"); in prep_adm_dma_desc()
1095 list_add_tail(&desc->node, &nandc->desc_list); in prep_adm_dma_desc()
1112 static int read_reg_dma(struct qcom_nand_controller *nandc, int first, in read_reg_dma() argument
1118 vaddr = nandc->reg_read_buf + nandc->reg_read_pos; in read_reg_dma()
1119 nandc->reg_read_pos += num_regs; in read_reg_dma()
1122 first = dev_cmd_reg_addr(nandc, first); in read_reg_dma()
1124 if (nandc->props->is_bam) in read_reg_dma()
1125 return prep_bam_dma_desc_cmd(nandc, true, first, vaddr, in read_reg_dma()
1131 return prep_adm_dma_desc(nandc, true, first, vaddr, in read_reg_dma()
1143 static int write_reg_dma(struct qcom_nand_controller *nandc, int first, in write_reg_dma() argument
1147 struct nandc_regs *regs = nandc->regs; in write_reg_dma()
1163 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD1); in write_reg_dma()
1166 first = dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD); in write_reg_dma()
1168 if (nandc->props->is_bam) in write_reg_dma()
1169 return prep_bam_dma_desc_cmd(nandc, false, first, vaddr, in write_reg_dma()
1175 return prep_adm_dma_desc(nandc, false, first, vaddr, in write_reg_dma()
1188 static int read_data_dma(struct qcom_nand_controller *nandc, int reg_off, in read_data_dma() argument
1191 if (nandc->props->is_bam) in read_data_dma()
1192 return prep_bam_dma_desc_data(nandc, true, vaddr, size, flags); in read_data_dma()
1194 return prep_adm_dma_desc(nandc, true, reg_off, vaddr, size, false); in read_data_dma()
1206 static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off, in write_data_dma() argument
1209 if (nandc->props->is_bam) in write_data_dma()
1210 return prep_bam_dma_desc_data(nandc, false, vaddr, size, flags); in write_data_dma()
1212 return prep_adm_dma_desc(nandc, false, reg_off, vaddr, size, false); in write_data_dma()
1221 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in config_nand_page_read() local
1223 write_reg_dma(nandc, NAND_ADDR0, 2, 0); in config_nand_page_read()
1224 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); in config_nand_page_read()
1225 if (!nandc->props->qpic_v2) in config_nand_page_read()
1226 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0); in config_nand_page_read()
1227 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, 0); in config_nand_page_read()
1228 write_reg_dma(nandc, NAND_ERASED_CW_DETECT_CFG, 1, in config_nand_page_read()
1239 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in config_nand_cw_read() local
1244 if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw)) in config_nand_cw_read()
1247 if (nandc->props->is_bam) in config_nand_cw_read()
1248 write_reg_dma(nandc, reg, 4, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1250 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1251 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1254 read_reg_dma(nandc, NAND_FLASH_STATUS, 2, 0); in config_nand_cw_read()
1255 read_reg_dma(nandc, NAND_ERASED_CW_DETECT_STATUS, 1, in config_nand_cw_read()
1258 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_read()
1280 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in config_nand_page_write() local
1282 write_reg_dma(nandc, NAND_ADDR0, 2, 0); in config_nand_page_write()
1283 write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0); in config_nand_page_write()
1284 if (!nandc->props->qpic_v2) in config_nand_page_write()
1285 write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, in config_nand_page_write()
1295 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in config_nand_cw_write() local
1297 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1298 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1300 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1302 write_reg_dma(nandc, NAND_FLASH_STATUS, 1, 0); in config_nand_cw_write()
1303 write_reg_dma(nandc, NAND_READ_STATUS, 1, NAND_BAM_NEXT_SGL); in config_nand_cw_write()
1307 static int submit_descs(struct qcom_nand_controller *nandc) in submit_descs() argument
1311 struct bam_transaction *bam_txn = nandc->bam_txn; in submit_descs()
1314 if (nandc->props->is_bam) { in submit_descs()
1316 ret = prepare_bam_async_desc(nandc, nandc->rx_chan, 0); in submit_descs()
1322 ret = prepare_bam_async_desc(nandc, nandc->tx_chan, in submit_descs()
1329 ret = prepare_bam_async_desc(nandc, nandc->cmd_chan, in submit_descs()
1336 list_for_each_entry(desc, &nandc->desc_list, node) in submit_descs()
1339 if (nandc->props->is_bam) { in submit_descs()
1348 dma_async_issue_pending(nandc->tx_chan); in submit_descs()
1349 dma_async_issue_pending(nandc->rx_chan); in submit_descs()
1350 dma_async_issue_pending(nandc->cmd_chan); in submit_descs()
1356 if (dma_sync_wait(nandc->chan, cookie) != DMA_COMPLETE) in submit_descs()
1365 list_for_each_entry_safe(desc, n, &nandc->desc_list, node) { in submit_descs()
1368 if (nandc->props->is_bam) in submit_descs()
1369 dma_unmap_sg(nandc->dev, desc->bam_sgl, in submit_descs()
1372 dma_unmap_sg(nandc->dev, &desc->adm_sgl, 1, in submit_descs()
1382 static void clear_read_regs(struct qcom_nand_controller *nandc) in clear_read_regs() argument
1384 nandc->reg_read_pos = 0; in clear_read_regs()
1385 nandc_read_buffer_sync(nandc, false); in clear_read_regs()
1446 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in check_flash_errors() local
1449 nandc_read_buffer_sync(nandc, true); in check_flash_errors()
1452 u32 flash = le32_to_cpu(nandc->reg_read_buf[i]); in check_flash_errors()
1467 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_cw_raw() local
1474 nandc->buf_count = 0; in qcom_nandc_read_cw_raw()
1475 nandc->buf_start = 0; in qcom_nandc_read_cw_raw()
1476 clear_read_regs(nandc); in qcom_nandc_read_cw_raw()
1479 if (nandc->props->qpic_v2) in qcom_nandc_read_cw_raw()
1482 clear_bam_transaction(nandc); in qcom_nandc_read_cw_raw()
1500 if (nandc->props->is_bam) { in qcom_nandc_read_cw_raw()
1515 read_data_dma(nandc, reg_off, data_buf, data_size1, 0); in qcom_nandc_read_cw_raw()
1518 read_data_dma(nandc, reg_off, oob_buf, oob_size1, 0); in qcom_nandc_read_cw_raw()
1521 read_data_dma(nandc, reg_off, data_buf + data_size1, data_size2, 0); in qcom_nandc_read_cw_raw()
1524 read_data_dma(nandc, reg_off, oob_buf + oob_size1, oob_size2, 0); in qcom_nandc_read_cw_raw()
1526 ret = submit_descs(nandc); in qcom_nandc_read_cw_raw()
1528 dev_err(nandc->dev, "failure to read raw cw %d\n", cw); in qcom_nandc_read_cw_raw()
1614 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in parse_read_errors() local
1623 buf = (struct read_stats *)nandc->reg_read_buf; in parse_read_errors()
1624 nandc_read_buffer_sync(nandc, true); in parse_read_errors()
1717 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in read_page_ecc() local
1737 if (nandc->props->is_bam) { in read_page_ecc()
1753 read_data_dma(nandc, FLASH_BUF_ACC, data_buf, in read_page_ecc()
1769 read_data_dma(nandc, FLASH_BUF_ACC + data_size, in read_page_ecc()
1779 ret = submit_descs(nandc); in read_page_ecc()
1781 dev_err(nandc->dev, "failure to read page/oob\n"); in read_page_ecc()
1795 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in copy_last_cw() local
1800 clear_read_regs(nandc); in copy_last_cw()
1805 memset(nandc->data_buffer, 0xff, size); in copy_last_cw()
1812 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0); in copy_last_cw()
1814 ret = submit_descs(nandc); in copy_last_cw()
1816 dev_err(nandc->dev, "failed to copy last codeword\n"); in copy_last_cw()
1889 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_page() local
1897 nandc->buf_count = 0; in qcom_nandc_read_page()
1898 nandc->buf_start = 0; in qcom_nandc_read_page()
1900 clear_read_regs(nandc); in qcom_nandc_read_page()
1907 clear_bam_transaction(nandc); in qcom_nandc_read_page()
1942 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_read_oob() local
1948 clear_read_regs(nandc); in qcom_nandc_read_oob()
1949 clear_bam_transaction(nandc); in qcom_nandc_read_oob()
1963 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_page() local
1974 nandc->buf_count = 0; in qcom_nandc_write_page()
1975 nandc->buf_start = 0; in qcom_nandc_write_page()
1976 clear_read_regs(nandc); in qcom_nandc_write_page()
1977 clear_bam_transaction(nandc); in qcom_nandc_write_page()
1998 write_data_dma(nandc, FLASH_BUF_ACC, data_buf, data_size, in qcom_nandc_write_page()
2011 write_data_dma(nandc, FLASH_BUF_ACC + data_size, in qcom_nandc_write_page()
2021 ret = submit_descs(nandc); in qcom_nandc_write_page()
2023 dev_err(nandc->dev, "failure to write page\n"); in qcom_nandc_write_page()
2037 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_page_raw() local
2046 clear_read_regs(nandc); in qcom_nandc_write_page_raw()
2047 clear_bam_transaction(nandc); in qcom_nandc_write_page_raw()
2073 write_data_dma(nandc, reg_off, data_buf, data_size1, in qcom_nandc_write_page_raw()
2078 write_data_dma(nandc, reg_off, oob_buf, oob_size1, in qcom_nandc_write_page_raw()
2083 write_data_dma(nandc, reg_off, data_buf, data_size2, in qcom_nandc_write_page_raw()
2088 write_data_dma(nandc, reg_off, oob_buf, oob_size2, 0); in qcom_nandc_write_page_raw()
2094 ret = submit_descs(nandc); in qcom_nandc_write_page_raw()
2096 dev_err(nandc->dev, "failure to write raw page\n"); in qcom_nandc_write_page_raw()
2114 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_write_oob() local
2124 clear_bam_transaction(nandc); in qcom_nandc_write_oob()
2130 memset(nandc->data_buffer, 0xff, host->cw_data); in qcom_nandc_write_oob()
2132 mtd_ooblayout_get_databytes(mtd, nandc->data_buffer + data_size, oob, in qcom_nandc_write_oob()
2139 write_data_dma(nandc, FLASH_BUF_ACC, in qcom_nandc_write_oob()
2140 nandc->data_buffer, data_size + oob_size, 0); in qcom_nandc_write_oob()
2143 ret = submit_descs(nandc); in qcom_nandc_write_oob()
2145 dev_err(nandc->dev, "failure to write oob\n"); in qcom_nandc_write_oob()
2156 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_block_bad() local
2170 clear_bam_transaction(nandc); in qcom_nandc_block_bad()
2176 dev_warn(nandc->dev, "error when trying to read BBM\n"); in qcom_nandc_block_bad()
2182 bad = nandc->data_buffer[bbpos] != 0xff; in qcom_nandc_block_bad()
2185 bad = bad || (nandc->data_buffer[bbpos + 1] != 0xff); in qcom_nandc_block_bad()
2193 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nandc_block_markbad() local
2197 clear_read_regs(nandc); in qcom_nandc_block_markbad()
2198 clear_bam_transaction(nandc); in qcom_nandc_block_markbad()
2205 memset(nandc->data_buffer, 0x00, host->cw_size); in qcom_nandc_block_markbad()
2215 write_data_dma(nandc, FLASH_BUF_ACC, in qcom_nandc_block_markbad()
2216 nandc->data_buffer, host->cw_size, 0); in qcom_nandc_block_markbad()
2219 ret = submit_descs(nandc); in qcom_nandc_block_markbad()
2221 dev_err(nandc->dev, "failure to update BBM\n"); in qcom_nandc_block_markbad()
2370 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_nand_attach_chip() local
2387 dev_err(nandc->dev, "No valid ECC settings possible\n"); in qcom_nand_attach_chip()
2411 if (nandc->props->ecc_modes & ECC_BCH_4BIT) { in qcom_nand_attach_chip()
2458 if (nandc->props->is_bam) in qcom_nand_attach_chip()
2459 free_bam_transaction(nandc); in qcom_nand_attach_chip()
2461 nandc->max_cwperpage = max_t(unsigned int, nandc->max_cwperpage, in qcom_nand_attach_chip()
2465 if (nandc->props->is_bam) { in qcom_nand_attach_chip()
2466 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nand_attach_chip()
2467 if (!nandc->bam_txn) { in qcom_nand_attach_chip()
2468 dev_err(nandc->dev, in qcom_nand_attach_chip()
2525 if (!nandc->props->qpic_v2) in qcom_nand_attach_chip()
2530 nandc->regs->erased_cw_detect_cfg_clr = in qcom_nand_attach_chip()
2532 nandc->regs->erased_cw_detect_cfg_set = in qcom_nand_attach_chip()
2535 dev_dbg(nandc->dev, in qcom_nand_attach_chip()
2547 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_op_cmd_mapping() local
2559 if (nandc->props->qpic_v2) in qcom_op_cmd_mapping()
2574 nandc->exec_opwrite = true; in qcom_op_cmd_mapping()
2584 dev_err(nandc->dev, "Opcode not supported: %u\n", opcode); in qcom_op_cmd_mapping()
2662 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_wait_rdy_poll() local
2666 nandc_read_buffer_sync(nandc, true); in qcom_wait_rdy_poll()
2669 flash = le32_to_cpu(nandc->reg_read_buf[0]); in qcom_wait_rdy_poll()
2675 dev_err(nandc->dev, "Timeout waiting for device to be ready:0x%08x\n", flash); in qcom_wait_rdy_poll()
2684 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_read_status_exec() local
2699 num_cw = nandc->exec_opwrite ? ecc->steps : 1; in qcom_read_status_exec()
2700 nandc->exec_opwrite = false; in qcom_read_status_exec()
2702 nandc->buf_count = 0; in qcom_read_status_exec()
2703 nandc->buf_start = 0; in qcom_read_status_exec()
2706 clear_read_regs(nandc); in qcom_read_status_exec()
2707 clear_bam_transaction(nandc); in qcom_read_status_exec()
2712 write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_read_status_exec()
2713 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_read_status_exec()
2714 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in qcom_read_status_exec()
2716 ret = submit_descs(nandc); in qcom_read_status_exec()
2718 dev_err(nandc->dev, "failure in submitting status descriptor\n"); in qcom_read_status_exec()
2722 nandc_read_buffer_sync(nandc, true); in qcom_read_status_exec()
2725 flash_status = le32_to_cpu(nandc->reg_read_buf[i]); in qcom_read_status_exec()
2747 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_read_id_type_exec() local
2759 nandc->buf_count = 0; in qcom_read_id_type_exec()
2760 nandc->buf_start = 0; in qcom_read_id_type_exec()
2763 clear_read_regs(nandc); in qcom_read_id_type_exec()
2764 clear_bam_transaction(nandc); in qcom_read_id_type_exec()
2770 nandc->props->is_bam ? 0 : DM_EN); in qcom_read_id_type_exec()
2774 write_reg_dma(nandc, NAND_FLASH_CMD, 4, NAND_BAM_NEXT_SGL); in qcom_read_id_type_exec()
2775 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_read_id_type_exec()
2777 read_reg_dma(nandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); in qcom_read_id_type_exec()
2779 ret = submit_descs(nandc); in qcom_read_id_type_exec()
2781 dev_err(nandc->dev, "failure in submitting read id descriptor\n"); in qcom_read_id_type_exec()
2789 nandc_read_buffer_sync(nandc, true); in qcom_read_id_type_exec()
2790 memcpy(instr->ctx.data.buf.in, nandc->reg_read_buf, len); in qcom_read_id_type_exec()
2798 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_misc_cmd_type_exec() local
2822 nandc->buf_count = 0; in qcom_misc_cmd_type_exec()
2823 nandc->buf_start = 0; in qcom_misc_cmd_type_exec()
2826 clear_read_regs(nandc); in qcom_misc_cmd_type_exec()
2827 clear_bam_transaction(nandc); in qcom_misc_cmd_type_exec()
2832 write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL); in qcom_misc_cmd_type_exec()
2834 write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); in qcom_misc_cmd_type_exec()
2836 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); in qcom_misc_cmd_type_exec()
2837 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); in qcom_misc_cmd_type_exec()
2839 ret = submit_descs(nandc); in qcom_misc_cmd_type_exec()
2841 dev_err(nandc->dev, "failure in submitting misc descriptor\n"); in qcom_misc_cmd_type_exec()
2856 struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); in qcom_param_page_type_exec() local
2869 nandc->buf_count = 0; in qcom_param_page_type_exec()
2870 nandc->buf_start = 0; in qcom_param_page_type_exec()
2872 clear_read_regs(nandc); in qcom_param_page_type_exec()
2873 clear_bam_transaction(nandc); in qcom_param_page_type_exec()
2890 if (!nandc->props->qpic_v2) in qcom_param_page_type_exec()
2894 if (!nandc->props->qpic_v2) { in qcom_param_page_type_exec()
2896 (nandc->vld & ~READ_START_VLD)); in qcom_param_page_type_exec()
2898 (nandc->cmd1 & ~(0xFF << READ_ADDR)) in qcom_param_page_type_exec()
2904 if (!nandc->props->qpic_v2) { in qcom_param_page_type_exec()
2905 nandc_set_reg(chip, NAND_DEV_CMD1_RESTORE, nandc->cmd1); in qcom_param_page_type_exec()
2906 nandc_set_reg(chip, NAND_DEV_CMD_VLD_RESTORE, nandc->vld); in qcom_param_page_type_exec()
2915 if (!nandc->props->qpic_v2) { in qcom_param_page_type_exec()
2916 write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0); in qcom_param_page_type_exec()
2917 write_reg_dma(nandc, NAND_DEV_CMD1, 1, NAND_BAM_NEXT_SGL); in qcom_param_page_type_exec()
2920 nandc->buf_count = len; in qcom_param_page_type_exec()
2921 memset(nandc->data_buffer, 0xff, nandc->buf_count); in qcom_param_page_type_exec()
2925 read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, in qcom_param_page_type_exec()
2926 nandc->buf_count, 0); in qcom_param_page_type_exec()
2929 if (!nandc->props->qpic_v2) { in qcom_param_page_type_exec()
2930 write_reg_dma(nandc, NAND_DEV_CMD1_RESTORE, 1, 0); in qcom_param_page_type_exec()
2931 write_reg_dma(nandc, NAND_DEV_CMD_VLD_RESTORE, 1, NAND_BAM_NEXT_SGL); in qcom_param_page_type_exec()
2934 ret = submit_descs(nandc); in qcom_param_page_type_exec()
2936 dev_err(nandc->dev, "failure in submitting param page descriptor\n"); in qcom_param_page_type_exec()
2944 memcpy(instr->ctx.data.buf.in, nandc->data_buffer, len); in qcom_param_page_type_exec()
3018 static void qcom_nandc_unalloc(struct qcom_nand_controller *nandc) in qcom_nandc_unalloc() argument
3020 if (nandc->props->is_bam) { in qcom_nandc_unalloc()
3021 if (!dma_mapping_error(nandc->dev, nandc->reg_read_dma)) in qcom_nandc_unalloc()
3022 dma_unmap_single(nandc->dev, nandc->reg_read_dma, in qcom_nandc_unalloc()
3024 sizeof(*nandc->reg_read_buf), in qcom_nandc_unalloc()
3027 if (nandc->tx_chan) in qcom_nandc_unalloc()
3028 dma_release_channel(nandc->tx_chan); in qcom_nandc_unalloc()
3030 if (nandc->rx_chan) in qcom_nandc_unalloc()
3031 dma_release_channel(nandc->rx_chan); in qcom_nandc_unalloc()
3033 if (nandc->cmd_chan) in qcom_nandc_unalloc()
3034 dma_release_channel(nandc->cmd_chan); in qcom_nandc_unalloc()
3036 if (nandc->chan) in qcom_nandc_unalloc()
3037 dma_release_channel(nandc->chan); in qcom_nandc_unalloc()
3041 static int qcom_nandc_alloc(struct qcom_nand_controller *nandc) in qcom_nandc_alloc() argument
3045 ret = dma_set_coherent_mask(nandc->dev, DMA_BIT_MASK(32)); in qcom_nandc_alloc()
3047 dev_err(nandc->dev, "failed to set DMA mask\n"); in qcom_nandc_alloc()
3057 nandc->buf_size = 532; in qcom_nandc_alloc()
3059 nandc->data_buffer = devm_kzalloc(nandc->dev, nandc->buf_size, GFP_KERNEL); in qcom_nandc_alloc()
3060 if (!nandc->data_buffer) in qcom_nandc_alloc()
3063 nandc->regs = devm_kzalloc(nandc->dev, sizeof(*nandc->regs), GFP_KERNEL); in qcom_nandc_alloc()
3064 if (!nandc->regs) in qcom_nandc_alloc()
3067 nandc->reg_read_buf = devm_kcalloc(nandc->dev, MAX_REG_RD, in qcom_nandc_alloc()
3068 sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
3070 if (!nandc->reg_read_buf) in qcom_nandc_alloc()
3073 if (nandc->props->is_bam) { in qcom_nandc_alloc()
3074 nandc->reg_read_dma = in qcom_nandc_alloc()
3075 dma_map_single(nandc->dev, nandc->reg_read_buf, in qcom_nandc_alloc()
3077 sizeof(*nandc->reg_read_buf), in qcom_nandc_alloc()
3079 if (dma_mapping_error(nandc->dev, nandc->reg_read_dma)) { in qcom_nandc_alloc()
3080 dev_err(nandc->dev, "failed to DMA MAP reg buffer\n"); in qcom_nandc_alloc()
3084 nandc->tx_chan = dma_request_chan(nandc->dev, "tx"); in qcom_nandc_alloc()
3085 if (IS_ERR(nandc->tx_chan)) { in qcom_nandc_alloc()
3086 ret = PTR_ERR(nandc->tx_chan); in qcom_nandc_alloc()
3087 nandc->tx_chan = NULL; in qcom_nandc_alloc()
3088 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
3093 nandc->rx_chan = dma_request_chan(nandc->dev, "rx"); in qcom_nandc_alloc()
3094 if (IS_ERR(nandc->rx_chan)) { in qcom_nandc_alloc()
3095 ret = PTR_ERR(nandc->rx_chan); in qcom_nandc_alloc()
3096 nandc->rx_chan = NULL; in qcom_nandc_alloc()
3097 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
3102 nandc->cmd_chan = dma_request_chan(nandc->dev, "cmd"); in qcom_nandc_alloc()
3103 if (IS_ERR(nandc->cmd_chan)) { in qcom_nandc_alloc()
3104 ret = PTR_ERR(nandc->cmd_chan); in qcom_nandc_alloc()
3105 nandc->cmd_chan = NULL; in qcom_nandc_alloc()
3106 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
3117 nandc->max_cwperpage = 1; in qcom_nandc_alloc()
3118 nandc->bam_txn = alloc_bam_transaction(nandc); in qcom_nandc_alloc()
3119 if (!nandc->bam_txn) { in qcom_nandc_alloc()
3120 dev_err(nandc->dev, in qcom_nandc_alloc()
3126 nandc->chan = dma_request_chan(nandc->dev, "rxtx"); in qcom_nandc_alloc()
3127 if (IS_ERR(nandc->chan)) { in qcom_nandc_alloc()
3128 ret = PTR_ERR(nandc->chan); in qcom_nandc_alloc()
3129 nandc->chan = NULL; in qcom_nandc_alloc()
3130 dev_err_probe(nandc->dev, ret, in qcom_nandc_alloc()
3136 INIT_LIST_HEAD(&nandc->desc_list); in qcom_nandc_alloc()
3137 INIT_LIST_HEAD(&nandc->host_list); in qcom_nandc_alloc()
3139 nand_controller_init(&nandc->controller); in qcom_nandc_alloc()
3140 nandc->controller.ops = &qcom_nandc_ops; in qcom_nandc_alloc()
3144 qcom_nandc_unalloc(nandc); in qcom_nandc_alloc()
3149 static int qcom_nandc_setup(struct qcom_nand_controller *nandc) in qcom_nandc_setup() argument
3154 if (!nandc->props->is_qpic) in qcom_nandc_setup()
3155 nandc_write(nandc, SFLASHC_BURST_CFG, 0); in qcom_nandc_setup()
3157 if (!nandc->props->qpic_v2) in qcom_nandc_setup()
3158 nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD), in qcom_nandc_setup()
3162 if (nandc->props->is_bam) { in qcom_nandc_setup()
3163 nand_ctrl = nandc_read(nandc, NAND_CTRL); in qcom_nandc_setup()
3173 nandc_write(nandc, NAND_CTRL, nand_ctrl | BAM_MODE_EN); in qcom_nandc_setup()
3175 nandc_write(nandc, NAND_FLASH_CHIP_SELECT, DM_EN); in qcom_nandc_setup()
3179 if (!nandc->props->qpic_v2) { in qcom_nandc_setup()
3180 nandc->cmd1 = nandc_read(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD1)); in qcom_nandc_setup()
3181 nandc->vld = NAND_DEV_CMD_VLD_VAL; in qcom_nandc_setup()
3189 static int qcom_nand_host_parse_boot_partitions(struct qcom_nand_controller *nandc, in qcom_nand_host_parse_boot_partitions() argument
3196 struct device *dev = nandc->dev; in qcom_nand_host_parse_boot_partitions()
3257 static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, in qcom_nand_host_init_and_register() argument
3263 struct device *dev = nandc->dev; in qcom_nand_host_init_and_register()
3291 chip->controller = &nandc->controller; in qcom_nand_host_init_and_register()
3306 if (nandc->props->use_codeword_fixup) { in qcom_nand_host_init_and_register()
3307 ret = qcom_nand_host_parse_boot_partitions(nandc, host, dn); in qcom_nand_host_init_and_register()
3319 static int qcom_probe_nand_devices(struct qcom_nand_controller *nandc) in qcom_probe_nand_devices() argument
3321 struct device *dev = nandc->dev; in qcom_probe_nand_devices()
3333 ret = qcom_nand_host_init_and_register(nandc, host, child); in qcom_probe_nand_devices()
3339 list_add_tail(&host->node, &nandc->host_list); in qcom_probe_nand_devices()
3348 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); in qcom_nandc_parse_dt() local
3349 struct device_node *np = nandc->dev->of_node; in qcom_nandc_parse_dt()
3352 if (!nandc->props->is_bam) { in qcom_nandc_parse_dt()
3354 &nandc->cmd_crci); in qcom_nandc_parse_dt()
3356 dev_err(nandc->dev, "command CRCI unspecified\n"); in qcom_nandc_parse_dt()
3361 &nandc->data_crci); in qcom_nandc_parse_dt()
3363 dev_err(nandc->dev, "data CRCI unspecified\n"); in qcom_nandc_parse_dt()
3373 struct qcom_nand_controller *nandc; in qcom_nandc_probe() local
3379 nandc = devm_kzalloc(&pdev->dev, sizeof(*nandc), GFP_KERNEL); in qcom_nandc_probe()
3380 if (!nandc) in qcom_nandc_probe()
3383 platform_set_drvdata(pdev, nandc); in qcom_nandc_probe()
3384 nandc->dev = dev; in qcom_nandc_probe()
3392 nandc->props = dev_data; in qcom_nandc_probe()
3394 nandc->core_clk = devm_clk_get(dev, "core"); in qcom_nandc_probe()
3395 if (IS_ERR(nandc->core_clk)) in qcom_nandc_probe()
3396 return PTR_ERR(nandc->core_clk); in qcom_nandc_probe()
3398 nandc->aon_clk = devm_clk_get(dev, "aon"); in qcom_nandc_probe()
3399 if (IS_ERR(nandc->aon_clk)) in qcom_nandc_probe()
3400 return PTR_ERR(nandc->aon_clk); in qcom_nandc_probe()
3406 nandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in qcom_nandc_probe()
3407 if (IS_ERR(nandc->base)) in qcom_nandc_probe()
3408 return PTR_ERR(nandc->base); in qcom_nandc_probe()
3410 nandc->base_phys = res->start; in qcom_nandc_probe()
3411 nandc->base_dma = dma_map_resource(dev, res->start, in qcom_nandc_probe()
3414 if (dma_mapping_error(dev, nandc->base_dma)) in qcom_nandc_probe()
3417 ret = clk_prepare_enable(nandc->core_clk); in qcom_nandc_probe()
3421 ret = clk_prepare_enable(nandc->aon_clk); in qcom_nandc_probe()
3425 ret = qcom_nandc_alloc(nandc); in qcom_nandc_probe()
3429 ret = qcom_nandc_setup(nandc); in qcom_nandc_probe()
3433 ret = qcom_probe_nand_devices(nandc); in qcom_nandc_probe()
3440 qcom_nandc_unalloc(nandc); in qcom_nandc_probe()
3442 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_probe()
3444 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_probe()
3446 dma_unmap_resource(dev, nandc->base_dma, resource_size(res), in qcom_nandc_probe()
3453 struct qcom_nand_controller *nandc = platform_get_drvdata(pdev); in qcom_nandc_remove() local
3459 list_for_each_entry(host, &nandc->host_list, node) { in qcom_nandc_remove()
3466 qcom_nandc_unalloc(nandc); in qcom_nandc_remove()
3468 clk_disable_unprepare(nandc->aon_clk); in qcom_nandc_remove()
3469 clk_disable_unprepare(nandc->core_clk); in qcom_nandc_remove()
3471 dma_unmap_resource(&pdev->dev, nandc->base_dma, resource_size(res), in qcom_nandc_remove()