Lines Matching full:nfc
214 static void pl35x_smc_update_regs(struct pl35x_nandc *nfc) in pl35x_smc_update_regs() argument
218 nfc->conf_regs + PL35X_SMC_DIRECT_CMD); in pl35x_smc_update_regs()
221 static int pl35x_smc_set_buswidth(struct pl35x_nandc *nfc, unsigned int bw) in pl35x_smc_set_buswidth() argument
226 writel(bw, nfc->conf_regs + PL35X_SMC_OPMODE); in pl35x_smc_set_buswidth()
227 pl35x_smc_update_regs(nfc); in pl35x_smc_set_buswidth()
232 static void pl35x_smc_clear_irq(struct pl35x_nandc *nfc) in pl35x_smc_clear_irq() argument
235 nfc->conf_regs + PL35X_SMC_MEMC_CFG_CLR); in pl35x_smc_clear_irq()
238 static int pl35x_smc_wait_for_irq(struct pl35x_nandc *nfc) in pl35x_smc_wait_for_irq() argument
243 ret = readl_poll_timeout(nfc->conf_regs + PL35X_SMC_MEMC_STATUS, reg, in pl35x_smc_wait_for_irq()
247 dev_err(nfc->dev, in pl35x_smc_wait_for_irq()
251 pl35x_smc_clear_irq(nfc); in pl35x_smc_wait_for_irq()
256 static int pl35x_smc_wait_for_ecc_done(struct pl35x_nandc *nfc) in pl35x_smc_wait_for_ecc_done() argument
261 ret = readl_poll_timeout(nfc->conf_regs + PL35X_SMC_ECC_STATUS, reg, in pl35x_smc_wait_for_ecc_done()
265 dev_err(nfc->dev, in pl35x_smc_wait_for_ecc_done()
271 static int pl35x_smc_set_ecc_mode(struct pl35x_nandc *nfc, in pl35x_smc_set_ecc_mode() argument
278 ecc_cfg = readl(nfc->conf_regs + PL35X_SMC_ECC_CFG); in pl35x_smc_set_ecc_mode()
281 writel(ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG); in pl35x_smc_set_ecc_mode()
289 return pl35x_smc_wait_for_ecc_done(nfc); in pl35x_smc_set_ecc_mode()
297 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller); in pl35x_smc_force_byte_access() local
304 ret = pl35x_smc_set_buswidth(nfc, PL35X_SMC_OPMODE_BW_8); in pl35x_smc_force_byte_access()
306 ret = pl35x_smc_set_buswidth(nfc, PL35X_SMC_OPMODE_BW_16); in pl35x_smc_force_byte_access()
309 dev_err(nfc->dev, "Error in Buswidth\n"); in pl35x_smc_force_byte_access()
315 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller); in pl35x_nand_select_target() local
318 if (chip == nfc->selected_chip) in pl35x_nand_select_target()
322 writel(plnand->timings, nfc->conf_regs + PL35X_SMC_CYCLES); in pl35x_nand_select_target()
323 pl35x_smc_update_regs(nfc); in pl35x_nand_select_target()
326 writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG); in pl35x_nand_select_target()
328 nfc->selected_chip = chip; in pl35x_nand_select_target()
335 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller); in pl35x_nand_read_data_op() local
351 buf32[i] = readl(nfc->io_regs + data_phase_addr); in pl35x_nand_read_data_op()
356 buf8[i] = readb(nfc->io_regs + PL35X_SMC_DATA_PHASE); in pl35x_nand_read_data_op()
367 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller); in pl35x_nand_write_data_op() local
383 writel(buf32[i], nfc->io_regs + data_phase_addr); in pl35x_nand_write_data_op()
388 writeb(buf8[i], nfc->io_regs + PL35X_SMC_DATA_PHASE); in pl35x_nand_write_data_op()
394 static int pl35x_nand_correct_data(struct pl35x_nandc *nfc, unsigned char *buf, in pl35x_nand_correct_data() argument
448 static int pl35x_nand_read_eccbytes(struct pl35x_nandc *nfc, in pl35x_nand_read_eccbytes() argument
456 ecc_value = readl(nfc->conf_regs + PL35X_SMC_ECC_VALUE(chunk)); in pl35x_nand_read_eccbytes()
466 static int pl35x_nand_recover_data_hwecc(struct pl35x_nandc *nfc, in pl35x_nand_recover_data_hwecc() argument
479 ecc_value = readl(nfc->conf_regs + PL35X_SMC_ECC_VALUE(chunk)); in pl35x_nand_recover_data_hwecc()
490 stats = pl35x_nand_correct_data(nfc, data, read_ecc, calc_ecc); in pl35x_nand_recover_data_hwecc()
506 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller); in pl35x_nand_write_page_hwecc() local
516 ret = pl35x_smc_set_ecc_mode(nfc, chip, PL35X_SMC_ECC_CFG_MODE_APB); in pl35x_nand_write_page_hwecc()
534 writel(addr1, nfc->io_regs + cmd_addr); in pl35x_nand_write_page_hwecc()
536 writel(addr2, nfc->io_regs + cmd_addr); in pl35x_nand_write_page_hwecc()
541 ret = pl35x_smc_wait_for_ecc_done(nfc); in pl35x_nand_write_page_hwecc()
546 ret = pl35x_nand_read_eccbytes(nfc, chip, nfc->ecc_buf); in pl35x_nand_write_page_hwecc()
553 ret = mtd_ooblayout_set_eccbytes(mtd, nfc->ecc_buf, chip->oob_poi, in pl35x_nand_write_page_hwecc()
563 ret = pl35x_smc_wait_for_irq(nfc); in pl35x_nand_write_page_hwecc()
576 pl35x_smc_set_ecc_mode(nfc, chip, PL35X_SMC_ECC_CFG_MODE_BYPASS); in pl35x_nand_write_page_hwecc()
597 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller); in pl35x_nand_read_page_hwecc() local
606 ret = pl35x_smc_set_ecc_mode(nfc, chip, PL35X_SMC_ECC_CFG_MODE_APB); in pl35x_nand_read_page_hwecc()
626 writel(addr1, nfc->io_regs + cmd_addr); in pl35x_nand_read_page_hwecc()
628 writel(addr2, nfc->io_regs + cmd_addr); in pl35x_nand_read_page_hwecc()
632 ret = pl35x_smc_wait_for_irq(nfc); in pl35x_nand_read_page_hwecc()
639 ret = pl35x_smc_wait_for_ecc_done(nfc); in pl35x_nand_read_page_hwecc()
646 ret = mtd_ooblayout_get_eccbytes(mtd, nfc->ecc_buf, chip->oob_poi, 0, in pl35x_nand_read_page_hwecc()
651 pl35x_smc_set_ecc_mode(nfc, chip, PL35X_SMC_ECC_CFG_MODE_BYPASS); in pl35x_nand_read_page_hwecc()
654 return pl35x_nand_recover_data_hwecc(nfc, chip, buf, nfc->ecc_buf); in pl35x_nand_read_page_hwecc()
657 pl35x_smc_set_ecc_mode(nfc, chip, PL35X_SMC_ECC_CFG_MODE_BYPASS); in pl35x_nand_read_page_hwecc()
665 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller); in pl35x_nand_exec_op() local
722 writel(addr1, nfc->io_regs + cmd_addr); in pl35x_nand_exec_op()
724 writel(addr2, nfc->io_regs + cmd_addr); in pl35x_nand_exec_op()
739 ret = pl35x_smc_wait_for_irq(nfc); in pl35x_nand_exec_op()
787 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller); in pl35x_nfc_setup_interface() local
798 mclk = of_clk_get_by_name(nfc->dev->parent->of_node, "memclk"); in pl35x_nfc_setup_interface()
800 dev_err(nfc->dev, "Failed to retrieve SMC memclk\n"); in pl35x_nfc_setup_interface()
805 * SDR timings are given in pico-seconds while NFC timings must be in pl35x_nfc_setup_interface()
868 static void pl35x_smc_set_ecc_pg_size(struct pl35x_nandc *nfc, in pl35x_smc_set_ecc_pg_size() argument
890 plnand->ecc_cfg = readl(nfc->conf_regs + PL35X_SMC_ECC_CFG); in pl35x_smc_set_ecc_pg_size()
893 writel(plnand->ecc_cfg, nfc->conf_regs + PL35X_SMC_ECC_CFG); in pl35x_smc_set_ecc_pg_size()
896 static int pl35x_nand_init_hw_ecc_controller(struct pl35x_nandc *nfc, in pl35x_nand_init_hw_ecc_controller() argument
903 dev_err(nfc->dev, in pl35x_nand_init_hw_ecc_controller()
915 pl35x_smc_set_ecc_pg_size(nfc, chip, mtd->writesize); in pl35x_nand_init_hw_ecc_controller()
917 nfc->ecc_buf = devm_kmalloc(nfc->dev, chip->ecc.bytes * chip->ecc.steps, in pl35x_nand_init_hw_ecc_controller()
919 if (!nfc->ecc_buf) in pl35x_nand_init_hw_ecc_controller()
932 dev_err(nfc->dev, "Unsupported OOB size\n"); in pl35x_nand_init_hw_ecc_controller()
943 struct pl35x_nandc *nfc = to_pl35x_nandc(chip->controller); in pl35x_nand_attach_chip() local
954 dev_info(nfc->dev, in pl35x_nand_attach_chip()
981 ret = pl35x_nand_init_hw_ecc_controller(nfc, chip); in pl35x_nand_attach_chip()
986 dev_err(nfc->dev, "Unsupported ECC mode: %d\n", in pl35x_nand_attach_chip()
1000 static int pl35x_nand_reset_state(struct pl35x_nandc *nfc) in pl35x_nand_reset_state() argument
1008 nfc->conf_regs + PL35X_SMC_MEMC_CFG_CLR); in pl35x_nand_reset_state()
1011 ret = pl35x_smc_set_buswidth(nfc, PL35X_SMC_OPMODE_BW_8); in pl35x_nand_reset_state()
1016 ret = pl35x_smc_set_ecc_mode(nfc, NULL, PL35X_SMC_ECC_CFG_MODE_BYPASS); in pl35x_nand_reset_state()
1028 nfc->conf_regs + PL35X_SMC_ECC_CMD1); in pl35x_nand_reset_state()
1033 nfc->conf_regs + PL35X_SMC_ECC_CMD2); in pl35x_nand_reset_state()
1038 static int pl35x_nand_chip_init(struct pl35x_nandc *nfc, in pl35x_nand_chip_init() argument
1046 plnand = devm_kzalloc(nfc->dev, sizeof(*plnand), GFP_KERNEL); in pl35x_nand_chip_init()
1055 dev_err(nfc->dev, "Wrong CS %d\n", cs); in pl35x_nand_chip_init()
1059 if (test_and_set_bit(cs, &nfc->assigned_cs)) { in pl35x_nand_chip_init()
1060 dev_err(nfc->dev, "Already assigned CS %d\n", cs); in pl35x_nand_chip_init()
1069 chip->controller = &nfc->controller; in pl35x_nand_chip_init()
1071 mtd->dev.parent = nfc->dev; in pl35x_nand_chip_init()
1074 mtd->name = devm_kasprintf(nfc->dev, GFP_KERNEL, in pl35x_nand_chip_init()
1077 dev_err(nfc->dev, "Failed to allocate mtd->name\n"); in pl35x_nand_chip_init()
1092 list_add_tail(&plnand->node, &nfc->chips); in pl35x_nand_chip_init()
1097 static void pl35x_nand_chips_cleanup(struct pl35x_nandc *nfc) in pl35x_nand_chips_cleanup() argument
1103 list_for_each_entry_safe(plnand, tmp, &nfc->chips, node) { in pl35x_nand_chips_cleanup()
1112 static int pl35x_nand_chips_init(struct pl35x_nandc *nfc) in pl35x_nand_chips_init() argument
1114 struct device_node *np = nfc->dev->of_node, *nand_np; in pl35x_nand_chips_init()
1119 dev_err(nfc->dev, "Incorrect number of NAND chips (%d)\n", in pl35x_nand_chips_init()
1125 ret = pl35x_nand_chip_init(nfc, nand_np); in pl35x_nand_chips_init()
1128 pl35x_nand_chips_cleanup(nfc); in pl35x_nand_chips_init()
1140 struct pl35x_nandc *nfc; in pl35x_nand_probe() local
1143 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL); in pl35x_nand_probe()
1144 if (!nfc) in pl35x_nand_probe()
1147 nfc->dev = &pdev->dev; in pl35x_nand_probe()
1148 nand_controller_init(&nfc->controller); in pl35x_nand_probe()
1149 nfc->controller.ops = &pl35x_nandc_ops; in pl35x_nand_probe()
1150 INIT_LIST_HEAD(&nfc->chips); in pl35x_nand_probe()
1152 nfc->conf_regs = devm_ioremap_resource(&smc_amba->dev, &smc_amba->res); in pl35x_nand_probe()
1153 if (IS_ERR(nfc->conf_regs)) in pl35x_nand_probe()
1154 return PTR_ERR(nfc->conf_regs); in pl35x_nand_probe()
1156 nfc->io_regs = devm_platform_ioremap_resource(pdev, 0); in pl35x_nand_probe()
1157 if (IS_ERR(nfc->io_regs)) in pl35x_nand_probe()
1158 return PTR_ERR(nfc->io_regs); in pl35x_nand_probe()
1160 ret = pl35x_nand_reset_state(nfc); in pl35x_nand_probe()
1164 ret = pl35x_nand_chips_init(nfc); in pl35x_nand_probe()
1168 platform_set_drvdata(pdev, nfc); in pl35x_nand_probe()
1175 struct pl35x_nandc *nfc = platform_get_drvdata(pdev); in pl35x_nand_remove() local
1177 pl35x_nand_chips_cleanup(nfc); in pl35x_nand_remove()