69 static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,  in davinci_nand_readl()  function
91 	return davinci_nand_readl(info, NANDF1ECC_OFFSET  in nand_davinci_readecc_1bit()
109 	nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);  in nand_davinci_hwctl_1bit()
186 	davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);  in nand_davinci_hwctl_4bit()
191 	val = davinci_nand_readl(info, NANDFCR_OFFSET);  in nand_davinci_hwctl_4bit()
207 	code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;  in nand_davinci_readecc_4bit()
208 	code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;  in nand_davinci_readecc_4bit()
209 	code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;  in nand_davinci_readecc_4bit()
210 	code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;  in nand_davinci_readecc_4bit()
227 		davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);  in nand_davinci_calculate_4bit()
286 	davinci_nand_readl(info, NANDFSR_OFFSET);  in nand_davinci_correct_4bit()
295 	davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);  in nand_davinci_correct_4bit()
302 			davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));  in nand_davinci_correct_4bit()
315 		ecc_state = (davinci_nand_readl(info,  in nand_davinci_correct_4bit()
321 		u32	fsr = davinci_nand_readl(info, NANDFSR_OFFSET);  in nand_davinci_correct_4bit()
325 			davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);  in nand_davinci_correct_4bit()
328 			davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);  in nand_davinci_correct_4bit()
346 			error_address = davinci_nand_readl(info,  in nand_davinci_correct_4bit()
348 			error_value = davinci_nand_readl(info,  in nand_davinci_correct_4bit()
351 			error_address = davinci_nand_readl(info,  in nand_davinci_correct_4bit()
353 			error_value = davinci_nand_readl(info,  in nand_davinci_correct_4bit()
788 	val = davinci_nand_readl(info, NANDFCR_OFFSET);  in nand_davinci_probe()
811 	val = davinci_nand_readl(info, NRCSR_OFFSET);  in nand_davinci_probe()