Lines Matching +full:brcmnand +full:- +full:v7
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2010-2015 Broadcom Corporation
12 #include <linux/platform_data/brcmnand.h>
17 #include <linux/dma-mapping.h>
33 #include "brcmnand.h"
49 #define DRV_NAME "brcmnand"
237 /* List of NAND hosts (one for each chip-select) */
240 /* EDU info, per-transaction */
261 /* in-memory cache of the FLASH_CACHE, used only for some commands */
267 const u8 *cs_offsets; /* within each chip-select */
278 /* for low-power standby/resume only */
298 /* use for low-power standby/resume only */
329 BRCMNAND_CS1_BASE, /* CS1 regs, if non-contiguous */
343 BRCMNAND_OOB_READ_10_BASE, /* offset 0x10, if non-contiguous */
345 BRCMNAND_OOB_WRITE_10_BASE, /* offset 0x10, if non-contiguous */
349 /* BRCMNAND v2.1-v2.2 */
379 /* BRCMNAND v3.3-v4.0 */
409 /* BRCMNAND v5.0 */
439 /* BRCMNAND v6.0 - v7.1 */
469 /* BRCMNAND v7.1 */
499 /* BRCMNAND v7.2 */
537 /* Per chip-select offsets for v7.1 */
546 /* Per chip-select offsets for pre v7.1, except CS0 on <= v5.0 */
555 /* Per chip-select offset for <= v5.0 on CS0 only */
565 * Bitfields for the CFG and CFG_EXT registers. Pre-v7.1 controllers only had
567 * (v7.1 and newer) added a CFG_EXT register and shuffled a few fields around.
580 /* Only for pre-v7.1 (with no CFG_EXT register) */
584 /* Only for v7.1+ (with CFG_EXT register) */
625 /* Only for v7.2 */
640 return brcmnand_soc_read(ctrl->soc, offs); in nand_readreg()
641 return brcmnand_readl(ctrl->nand_base + offs); in nand_readreg()
648 brcmnand_soc_write(ctrl->soc, val, offs); in nand_writereg()
650 brcmnand_writel(val, ctrl->nand_base + offs); in nand_writereg()
663 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff; in brcmnand_revision_init()
666 if (ctrl->nand_version < 0x0201) { in brcmnand_revision_init()
667 dev_err(ctrl->dev, "version %#x not supported\n", in brcmnand_revision_init()
668 ctrl->nand_version); in brcmnand_revision_init()
669 return -ENODEV; in brcmnand_revision_init()
673 if (ctrl->nand_version >= 0x0702) in brcmnand_revision_init()
674 ctrl->reg_offsets = brcmnand_regs_v72; in brcmnand_revision_init()
675 else if (ctrl->nand_version == 0x0701) in brcmnand_revision_init()
676 ctrl->reg_offsets = brcmnand_regs_v71; in brcmnand_revision_init()
677 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
678 ctrl->reg_offsets = brcmnand_regs_v60; in brcmnand_revision_init()
679 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
680 ctrl->reg_offsets = brcmnand_regs_v50; in brcmnand_revision_init()
681 else if (ctrl->nand_version >= 0x0303) in brcmnand_revision_init()
682 ctrl->reg_offsets = brcmnand_regs_v33; in brcmnand_revision_init()
683 else if (ctrl->nand_version >= 0x0201) in brcmnand_revision_init()
684 ctrl->reg_offsets = brcmnand_regs_v21; in brcmnand_revision_init()
686 /* Chip-select stride */ in brcmnand_revision_init()
687 if (ctrl->nand_version >= 0x0701) in brcmnand_revision_init()
688 ctrl->reg_spacing = 0x14; in brcmnand_revision_init()
690 ctrl->reg_spacing = 0x10; in brcmnand_revision_init()
692 /* Per chip-select registers */ in brcmnand_revision_init()
693 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
694 ctrl->cs_offsets = brcmnand_cs_offsets_v71; in brcmnand_revision_init()
696 ctrl->cs_offsets = brcmnand_cs_offsets; in brcmnand_revision_init()
698 /* v3.3-5.0 have a different CS0 offset layout */ in brcmnand_revision_init()
699 if (ctrl->nand_version >= 0x0303 && in brcmnand_revision_init()
700 ctrl->nand_version <= 0x0500) in brcmnand_revision_init()
701 ctrl->cs0_offsets = brcmnand_cs_offsets_cs0; in brcmnand_revision_init()
705 if (ctrl->nand_version >= 0x0701) { in brcmnand_revision_init()
706 /* >= v7.1 use nice power-of-2 values! */ in brcmnand_revision_init()
707 ctrl->max_page_size = 16 * 1024; in brcmnand_revision_init()
708 ctrl->max_block_size = 2 * 1024 * 1024; in brcmnand_revision_init()
710 if (ctrl->nand_version >= 0x0304) in brcmnand_revision_init()
711 ctrl->page_sizes = page_sizes_v3_4; in brcmnand_revision_init()
712 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
713 ctrl->page_sizes = page_sizes_v2_2; in brcmnand_revision_init()
715 ctrl->page_sizes = page_sizes_v2_1; in brcmnand_revision_init()
717 if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
718 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT; in brcmnand_revision_init()
720 ctrl->page_size_shift = CFG_PAGE_SIZE_SHIFT_v2_1; in brcmnand_revision_init()
722 if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
723 ctrl->block_sizes = block_sizes_v6; in brcmnand_revision_init()
724 else if (ctrl->nand_version >= 0x0400) in brcmnand_revision_init()
725 ctrl->block_sizes = block_sizes_v4; in brcmnand_revision_init()
726 else if (ctrl->nand_version >= 0x0202) in brcmnand_revision_init()
727 ctrl->block_sizes = block_sizes_v2_2; in brcmnand_revision_init()
729 ctrl->block_sizes = block_sizes_v2_1; in brcmnand_revision_init()
731 if (ctrl->nand_version < 0x0400) { in brcmnand_revision_init()
732 if (ctrl->nand_version < 0x0202) in brcmnand_revision_init()
733 ctrl->max_page_size = 2048; in brcmnand_revision_init()
735 ctrl->max_page_size = 4096; in brcmnand_revision_init()
736 ctrl->max_block_size = 512 * 1024; in brcmnand_revision_init()
741 if (ctrl->nand_version == 0x0702) in brcmnand_revision_init()
742 ctrl->max_oob = 128; in brcmnand_revision_init()
743 else if (ctrl->nand_version >= 0x0600) in brcmnand_revision_init()
744 ctrl->max_oob = 64; in brcmnand_revision_init()
745 else if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
746 ctrl->max_oob = 32; in brcmnand_revision_init()
748 ctrl->max_oob = 16; in brcmnand_revision_init()
751 if (ctrl->nand_version >= 0x0600 && ctrl->nand_version != 0x0601) in brcmnand_revision_init()
752 ctrl->features |= BRCMNAND_HAS_PREFETCH; in brcmnand_revision_init()
758 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
759 ctrl->features |= BRCMNAND_HAS_CACHE_MODE; in brcmnand_revision_init()
761 if (ctrl->nand_version >= 0x0500) in brcmnand_revision_init()
762 ctrl->features |= BRCMNAND_HAS_1K_SECTORS; in brcmnand_revision_init()
764 if (ctrl->nand_version >= 0x0700) in brcmnand_revision_init()
765 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
766 else if (of_property_read_bool(ctrl->dev->of_node, "brcm,nand-has-wp")) in brcmnand_revision_init()
767 ctrl->features |= BRCMNAND_HAS_WP; in brcmnand_revision_init()
769 /* v7.2 has different ecc level shift in the acc register */ in brcmnand_revision_init()
770 if (ctrl->nand_version == 0x0702) in brcmnand_revision_init()
771 ctrl->ecc_level_shift = ACC_CONTROL_ECC_EXT_SHIFT; in brcmnand_revision_init()
773 ctrl->ecc_level_shift = ACC_CONTROL_ECC_SHIFT; in brcmnand_revision_init()
781 if (ctrl->nand_version >= 0x0703) in brcmnand_flash_dma_revision_init()
782 ctrl->flash_dma_offsets = flash_dma_regs_v4; in brcmnand_flash_dma_revision_init()
783 else if (ctrl->nand_version == 0x0602) in brcmnand_flash_dma_revision_init()
784 ctrl->flash_dma_offsets = flash_dma_regs_v0; in brcmnand_flash_dma_revision_init()
786 ctrl->flash_dma_offsets = flash_dma_regs_v1; in brcmnand_flash_dma_revision_init()
792 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_read_reg()
803 u16 offs = ctrl->reg_offsets[reg]; in brcmnand_write_reg()
823 return brcmnand_soc_read(ctrl->soc, BRCMNAND_NON_MMIO_FC_ADDR); in brcmnand_read_fc()
824 return __raw_readl(ctrl->nand_fc + word * 4); in brcmnand_read_fc()
831 brcmnand_soc_write(ctrl->soc, val, BRCMNAND_NON_MMIO_FC_ADDR); in brcmnand_write_fc()
833 __raw_writel(val, ctrl->nand_fc + word * 4); in brcmnand_write_fc()
839 u16 offs = ctrl->edu_offsets[reg]; in edu_writel()
841 brcmnand_writel(val, ctrl->edu_base + offs); in edu_writel()
847 u16 offs = ctrl->edu_offsets[reg]; in edu_readl()
849 return brcmnand_readl(ctrl->edu_base + offs); in edu_readl()
890 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cmd_addr()
893 (host->cs << 16) | ((addr >> 32) & 0xffff)); in brcmnand_set_cmd_addr()
903 u16 offs_cs0 = ctrl->reg_offsets[BRCMNAND_CS0_BASE]; in brcmnand_cs_offset()
904 u16 offs_cs1 = ctrl->reg_offsets[BRCMNAND_CS1_BASE]; in brcmnand_cs_offset()
907 if (cs == 0 && ctrl->cs0_offsets) in brcmnand_cs_offset()
908 cs_offs = ctrl->cs0_offsets[reg]; in brcmnand_cs_offset()
910 cs_offs = ctrl->cs_offsets[reg]; in brcmnand_cs_offset()
913 return offs_cs1 + (cs - 1) * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
915 return offs_cs0 + cs * ctrl->reg_spacing + cs_offs; in brcmnand_cs_offset()
920 if (ctrl->nand_version < 0x0600) in brcmnand_count_corrected()
927 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wr_corr_thresh()
930 int cs = host->cs; in brcmnand_wr_corr_thresh()
932 if (!ctrl->reg_offsets[reg]) in brcmnand_wr_corr_thresh()
935 if (ctrl->nand_version == 0x0702) in brcmnand_wr_corr_thresh()
937 else if (ctrl->nand_version >= 0x0600) in brcmnand_wr_corr_thresh()
939 else if (ctrl->nand_version >= 0x0500) in brcmnand_wr_corr_thresh()
944 if (ctrl->nand_version >= 0x0702) { in brcmnand_wr_corr_thresh()
948 } else if (ctrl->nand_version >= 0x0600) { in brcmnand_wr_corr_thresh()
953 brcmnand_rmw_reg(ctrl, reg, (bits - 1) << shift, shift, val); in brcmnand_wr_corr_thresh()
958 /* Kludge for the BCMA-based NAND controller which does not actually in brcmnand_cmd_shift()
961 if (ctrl->nand_version == 0x0304 && brcmnand_non_mmio_ops(ctrl)) in brcmnand_cmd_shift()
964 if (ctrl->nand_version < 0x0602) in brcmnand_cmd_shift()
971 if (ctrl->nand_version == 0x0702) in brcmnand_spare_area_mask()
973 else if (ctrl->nand_version >= 0x0600) in brcmnand_spare_area_mask()
975 else if (ctrl->nand_version >= 0x0303) in brcmnand_spare_area_mask()
983 u32 mask = (ctrl->nand_version >= 0x0600) ? 0x1f : 0x0f; in brcmnand_ecc_level_mask()
987 /* v7.2 includes additional ECC levels */ in brcmnand_ecc_level_mask()
988 if (ctrl->nand_version == 0x0702) in brcmnand_ecc_level_mask()
996 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_ecc_enabled()
997 u16 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_set_ecc_enabled()
1004 acc_control |= host->hwcfg.ecc_level << ctrl->ecc_level_shift; in brcmnand_set_ecc_enabled()
1015 if (ctrl->nand_version >= 0x0702) in brcmnand_sector_1k_shift()
1017 else if (ctrl->nand_version >= 0x0600) in brcmnand_sector_1k_shift()
1019 else if (ctrl->nand_version >= 0x0500) in brcmnand_sector_1k_shift()
1022 return -1; in brcmnand_sector_1k_shift()
1027 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_get_sector_size_1k()
1029 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_get_sector_size_1k()
1040 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_sector_size_1k()
1042 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_sector_size_1k()
1091 dev_warn(ctrl->dev, "timeout on status poll (expected %x got %x)\n", in bcmnand_ctrl_poll_status()
1094 return -ETIMEDOUT; in bcmnand_ctrl_poll_status()
1110 return ctrl->flash_dma_base; in has_flash_dma()
1115 return ctrl->edu_base; in has_edu()
1125 if (ctrl->pio_poll_mode) in disable_ctrl_irqs()
1129 ctrl->flash_dma_base = NULL; in disable_ctrl_irqs()
1130 disable_irq(ctrl->dma_irq); in disable_ctrl_irqs()
1133 disable_irq(ctrl->irq); in disable_ctrl_irqs()
1134 ctrl->pio_poll_mode = true; in disable_ctrl_irqs()
1146 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_writel()
1148 brcmnand_writel(val, ctrl->flash_dma_base + offs); in flash_dma_writel()
1154 u16 offs = ctrl->flash_dma_offsets[dma_reg]; in flash_dma_readl()
1156 return brcmnand_readl(ctrl->flash_dma_base + offs); in flash_dma_readl()
1159 /* Low-level operation types: command, address, write, or read */
1174 if (ctrl->nand_version <= 0x0701) in is_hamming_ecc()
1175 return cfg->sector_size_1k == 0 && cfg->spare_area_size == 16 && in is_hamming_ecc()
1176 cfg->ecc_level == 15; in is_hamming_ecc()
1178 return cfg->sector_size_1k == 0 && ((cfg->spare_area_size == 16 && in is_hamming_ecc()
1179 cfg->ecc_level == 15) || in is_hamming_ecc()
1180 (cfg->spare_area_size == 28 && cfg->ecc_level == 16)); in is_hamming_ecc()
1184 * Set mtd->ooblayout to the appropriate mtd_ooblayout_ops given
1186 * Returns -ERRCODE on failure.
1193 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_hamming_ooblayout_ecc()
1194 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_hamming_ooblayout_ecc()
1195 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_hamming_ooblayout_ecc()
1198 return -ERANGE; in brcmnand_hamming_ooblayout_ecc()
1200 oobregion->offset = (section * sas) + 6; in brcmnand_hamming_ooblayout_ecc()
1201 oobregion->length = 3; in brcmnand_hamming_ooblayout_ecc()
1211 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_hamming_ooblayout_free()
1212 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_hamming_ooblayout_free()
1213 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_hamming_ooblayout_free()
1217 return -ERANGE; in brcmnand_hamming_ooblayout_free()
1224 oobregion->offset = ((section - 1) * sas) + 9; in brcmnand_hamming_ooblayout_free()
1226 if (cfg->page_size > 512) { in brcmnand_hamming_ooblayout_free()
1228 oobregion->offset = 2; in brcmnand_hamming_ooblayout_free()
1231 oobregion->offset = 0; in brcmnand_hamming_ooblayout_free()
1232 next--; in brcmnand_hamming_ooblayout_free()
1236 oobregion->length = next - oobregion->offset; in brcmnand_hamming_ooblayout_free()
1251 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_ecc()
1252 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_ecc()
1253 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_bch_ooblayout_ecc()
1256 return -ERANGE; in brcmnand_bch_ooblayout_ecc()
1258 oobregion->offset = ((section + 1) * sas) - chip->ecc.bytes; in brcmnand_bch_ooblayout_ecc()
1259 oobregion->length = chip->ecc.bytes; in brcmnand_bch_ooblayout_ecc()
1269 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_free_lp()
1270 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_free_lp()
1271 int sectors = cfg->page_size / (512 << cfg->sector_size_1k); in brcmnand_bch_ooblayout_free_lp()
1274 return -ERANGE; in brcmnand_bch_ooblayout_free_lp()
1276 if (sas <= chip->ecc.bytes) in brcmnand_bch_ooblayout_free_lp()
1279 oobregion->offset = section * sas; in brcmnand_bch_ooblayout_free_lp()
1280 oobregion->length = sas - chip->ecc.bytes; in brcmnand_bch_ooblayout_free_lp()
1283 oobregion->offset++; in brcmnand_bch_ooblayout_free_lp()
1284 oobregion->length--; in brcmnand_bch_ooblayout_free_lp()
1295 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_bch_ooblayout_free_sp()
1296 int sas = cfg->spare_area_size << cfg->sector_size_1k; in brcmnand_bch_ooblayout_free_sp()
1298 if (section > 1 || sas - chip->ecc.bytes < 6 || in brcmnand_bch_ooblayout_free_sp()
1299 (section && sas - chip->ecc.bytes == 6)) in brcmnand_bch_ooblayout_free_sp()
1300 return -ERANGE; in brcmnand_bch_ooblayout_free_sp()
1303 oobregion->offset = 0; in brcmnand_bch_ooblayout_free_sp()
1304 oobregion->length = 5; in brcmnand_bch_ooblayout_free_sp()
1306 oobregion->offset = 6; in brcmnand_bch_ooblayout_free_sp()
1307 oobregion->length = sas - chip->ecc.bytes - 6; in brcmnand_bch_ooblayout_free_sp()
1325 struct brcmnand_cfg *p = &host->hwcfg; in brcmstb_choose_ecc_layout()
1326 struct mtd_info *mtd = nand_to_mtd(&host->chip); in brcmstb_choose_ecc_layout()
1327 struct nand_ecc_ctrl *ecc = &host->chip.ecc; in brcmstb_choose_ecc_layout()
1328 unsigned int ecc_level = p->ecc_level; in brcmstb_choose_ecc_layout()
1329 int sas = p->spare_area_size << p->sector_size_1k; in brcmstb_choose_ecc_layout()
1330 int sectors = p->page_size / (512 << p->sector_size_1k); in brcmstb_choose_ecc_layout()
1332 if (p->sector_size_1k) in brcmstb_choose_ecc_layout()
1335 if (is_hamming_ecc(host->ctrl, p)) { in brcmstb_choose_ecc_layout()
1336 ecc->bytes = 3 * sectors; in brcmstb_choose_ecc_layout()
1347 ecc->bytes = DIV_ROUND_UP(ecc_level * 14, 8); in brcmstb_choose_ecc_layout()
1348 if (p->page_size == 512) in brcmstb_choose_ecc_layout()
1353 if (ecc->bytes >= sas) { in brcmstb_choose_ecc_layout()
1354 dev_err(&host->pdev->dev, in brcmstb_choose_ecc_layout()
1356 ecc->bytes, sas); in brcmstb_choose_ecc_layout()
1357 return -EINVAL; in brcmstb_choose_ecc_layout()
1367 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_wp()
1369 if ((ctrl->features & BRCMNAND_HAS_WP) && wp_on == 1) { in brcmnand_wp()
1370 static int old_wp = -1; in brcmnand_wp()
1374 dev_dbg(ctrl->dev, "WP %s\n", wp ? "on" : "off"); in brcmnand_wp()
1401 dev_err_ratelimited(&host->pdev->dev, in brcmnand_wp()
1412 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_READ_BASE]; in oob_reg_read()
1413 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_READ_10_BASE]; in oob_reg_read()
1415 if (offs >= ctrl->max_oob) in oob_reg_read()
1419 reg_offs = offset10 + ((offs - 0x10) & ~0x03); in oob_reg_read()
1423 return nand_readreg(ctrl, reg_offs) >> (24 - ((offs & 0x03) << 3)); in oob_reg_read()
1431 offset0 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_BASE]; in oob_reg_write()
1432 offset10 = ctrl->reg_offsets[BRCMNAND_OOB_WRITE_10_BASE]; in oob_reg_write()
1434 if (offs >= ctrl->max_oob) in oob_reg_write()
1438 reg_offs = offset10 + ((offs - 0x10) & ~0x03); in oob_reg_write()
1446 * read_oob_from_regs - read data from OOB registers
1448 * @i: sub-page sector index
1461 tbytes = max(0, tbytes - (int)ctrl->max_oob); in read_oob_from_regs()
1462 tbytes = min_t(int, tbytes, ctrl->max_oob); in read_oob_from_regs()
1470 * write_oob_to_regs - write data to OOB registers
1471 * @i: sub-page sector index
1486 tbytes = max(0, tbytes - (int)ctrl->max_oob); in write_oob_to_regs()
1487 tbytes = min_t(int, tbytes, ctrl->max_oob); in write_oob_to_regs()
1527 if (ctrl->edu_count) { in brcmnand_edu_irq()
1528 ctrl->edu_count--; in brcmnand_edu_irq()
1535 if (ctrl->edu_count) { in brcmnand_edu_irq()
1536 ctrl->edu_dram_addr += FC_BYTES; in brcmnand_edu_irq()
1537 ctrl->edu_ext_addr += FC_BYTES; in brcmnand_edu_irq()
1539 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_irq()
1541 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_irq()
1544 if (ctrl->oob) { in brcmnand_edu_irq()
1545 if (ctrl->edu_cmd == EDU_CMD_READ) { in brcmnand_edu_irq()
1546 ctrl->oob += read_oob_from_regs(ctrl, in brcmnand_edu_irq()
1547 ctrl->edu_count + 1, in brcmnand_edu_irq()
1548 ctrl->oob, ctrl->sas, in brcmnand_edu_irq()
1549 ctrl->sector_size_1k); in brcmnand_edu_irq()
1552 ctrl->edu_ext_addr); in brcmnand_edu_irq()
1554 ctrl->oob += write_oob_to_regs(ctrl, in brcmnand_edu_irq()
1555 ctrl->edu_count, in brcmnand_edu_irq()
1556 ctrl->oob, ctrl->sas, in brcmnand_edu_irq()
1557 ctrl->sector_size_1k); in brcmnand_edu_irq()
1562 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_irq()
1568 complete(&ctrl->edu_done); in brcmnand_edu_irq()
1578 if (ctrl->dma_pending) in brcmnand_ctlrdy_irq()
1582 if (ctrl->edu_pending) { in brcmnand_ctlrdy_irq()
1583 if (irq == ctrl->irq && ((int)ctrl->edu_irq >= 0)) in brcmnand_ctlrdy_irq()
1591 complete(&ctrl->done); in brcmnand_ctlrdy_irq()
1595 /* Handle SoC-specific interrupt hardware */
1600 if (ctrl->soc->ctlrdy_ack(ctrl->soc)) in brcmnand_irq()
1610 complete(&ctrl->dma_done); in brcmnand_dma_irq()
1617 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_send_cmd()
1623 dev_dbg(ctrl->dev, "send native cmd %d addr 0x%llx\n", cmd, cmd_addr); in brcmnand_send_cmd()
1631 if (ctrl->cmd_pending && in brcmnand_send_cmd()
1635 BUG_ON(ctrl->cmd_pending != 0); in brcmnand_send_cmd()
1636 ctrl->cmd_pending = cmd; in brcmnand_send_cmd()
1659 struct brcmnand_controller *ctrl = host->ctrl; in brcmstb_nand_wait_for_completion()
1664 if (mtd->oops_panic_write || ctrl->irq < 0) { in brcmstb_nand_wait_for_completion()
1674 sts = wait_for_completion_timeout(&ctrl->done, timeo); in brcmstb_nand_wait_for_completion()
1684 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_waitfunc()
1687 dev_dbg(ctrl->dev, "wait on native cmd %d\n", ctrl->cmd_pending); in brcmnand_waitfunc()
1688 if (ctrl->cmd_pending) in brcmnand_waitfunc()
1691 ctrl->cmd_pending = 0; in brcmnand_waitfunc()
1696 dev_err_ratelimited(ctrl->dev, in brcmnand_waitfunc()
1698 dev_err_ratelimited(ctrl->dev, "intfc status %08x\n", in brcmnand_waitfunc()
1700 return -ETIMEDOUT; in brcmnand_waitfunc()
1720 struct nand_chip *chip = &host->chip; in brcmnand_low_level_op()
1721 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_low_level_op()
1746 dev_dbg(ctrl->dev, "ll_op cmd %#x\n", tmp); in brcmnand_low_level_op()
1760 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_cmdfunc()
1761 u64 addr = (u64)page_addr << chip->page_shift; in brcmnand_cmdfunc()
1767 /* Avoid propagating a negative, don't-care address */ in brcmnand_cmdfunc()
1771 dev_dbg(ctrl->dev, "cmd 0x%x addr 0x%llx\n", command, in brcmnand_cmdfunc()
1774 host->last_cmd = command; in brcmnand_cmdfunc()
1775 host->last_byte = 0; in brcmnand_cmdfunc()
1776 host->last_addr = addr; in brcmnand_cmdfunc()
1805 addr &= ~((u64)(FC_BYTES - 1)); in brcmnand_cmdfunc()
1811 host->hwcfg.sector_size_1k = in brcmnand_cmdfunc()
1827 /* Copy flash cache word-wise */ in brcmnand_cmdfunc()
1828 u32 *flash_cache = (u32 *)ctrl->flash_cache; in brcmnand_cmdfunc()
1831 brcmnand_soc_data_bus_prepare(ctrl->soc, true); in brcmnand_cmdfunc()
1844 brcmnand_soc_data_bus_unprepare(ctrl->soc, true); in brcmnand_cmdfunc()
1847 if (host->hwcfg.sector_size_1k) in brcmnand_cmdfunc()
1849 host->hwcfg.sector_size_1k); in brcmnand_cmdfunc()
1852 /* Re-enable protection is necessary only after erase */ in brcmnand_cmdfunc()
1860 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_byte()
1864 switch (host->last_cmd) { in brcmnand_read_byte()
1866 if (host->last_byte < 4) in brcmnand_read_byte()
1868 (24 - (host->last_byte << 3)); in brcmnand_read_byte()
1869 else if (host->last_byte < 8) in brcmnand_read_byte()
1871 (56 - (host->last_byte << 3)); in brcmnand_read_byte()
1875 ret = oob_reg_read(ctrl, host->last_byte); in brcmnand_read_byte()
1887 addr = host->last_addr + host->last_byte; in brcmnand_read_byte()
1888 offs = addr & (FC_BYTES - 1); in brcmnand_read_byte()
1891 if (host->last_byte > 0 && offs == 0) in brcmnand_read_byte()
1894 ret = ctrl->flash_cache[offs]; in brcmnand_read_byte()
1897 if (host->last_byte >= ONFI_SUBFEATURE_PARAM_LEN) { in brcmnand_read_byte()
1900 bool last = host->last_byte == in brcmnand_read_byte()
1901 ONFI_SUBFEATURE_PARAM_LEN - 1; in brcmnand_read_byte()
1907 dev_dbg(ctrl->dev, "read byte = 0x%02x\n", ret); in brcmnand_read_byte()
1908 host->last_byte++; in brcmnand_read_byte()
1927 switch (host->last_cmd) { in brcmnand_write_buf()
1945 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_edu_trans()
1946 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_edu_trans()
1954 dev_dbg(ctrl->dev, "EDU %s %p:%p\n", ((edu_cmd == EDU_CMD_READ) ? in brcmnand_edu_trans()
1957 pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_edu_trans()
1958 if (dma_mapping_error(ctrl->dev, pa)) { in brcmnand_edu_trans()
1959 dev_err(ctrl->dev, "unable to map buffer for EDU DMA\n"); in brcmnand_edu_trans()
1960 return -ENOMEM; in brcmnand_edu_trans()
1963 ctrl->edu_pending = true; in brcmnand_edu_trans()
1964 ctrl->edu_dram_addr = pa; in brcmnand_edu_trans()
1965 ctrl->edu_ext_addr = addr; in brcmnand_edu_trans()
1966 ctrl->edu_cmd = edu_cmd; in brcmnand_edu_trans()
1967 ctrl->edu_count = trans; in brcmnand_edu_trans()
1968 ctrl->sas = cfg->spare_area_size; in brcmnand_edu_trans()
1969 ctrl->oob = oob; in brcmnand_edu_trans()
1971 edu_writel(ctrl, EDU_DRAM_ADDR, (u32)ctrl->edu_dram_addr); in brcmnand_edu_trans()
1973 edu_writel(ctrl, EDU_EXT_ADDR, ctrl->edu_ext_addr); in brcmnand_edu_trans()
1978 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_WRITE)) { in brcmnand_edu_trans()
1980 ctrl->edu_ext_addr); in brcmnand_edu_trans()
1982 ctrl->oob += write_oob_to_regs(ctrl, in brcmnand_edu_trans()
1984 ctrl->oob, ctrl->sas, in brcmnand_edu_trans()
1985 ctrl->sector_size_1k); in brcmnand_edu_trans()
1990 edu_writel(ctrl, EDU_CMD, ctrl->edu_cmd); in brcmnand_edu_trans()
1993 if (wait_for_completion_timeout(&ctrl->edu_done, timeo) <= 0) { in brcmnand_edu_trans()
1994 dev_err(ctrl->dev, in brcmnand_edu_trans()
2000 dma_unmap_single(ctrl->dev, pa, len, dir); in brcmnand_edu_trans()
2003 if (ctrl->oob && (ctrl->edu_cmd == EDU_CMD_READ)) { in brcmnand_edu_trans()
2004 ctrl->oob += read_oob_from_regs(ctrl, in brcmnand_edu_trans()
2006 ctrl->oob, ctrl->sas, in brcmnand_edu_trans()
2007 ctrl->sector_size_1k); in brcmnand_edu_trans()
2014 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_edu_trans()
2016 ret = -EIO; in brcmnand_edu_trans()
2021 dev_warn(ctrl->dev, "EDU still active: %#x\n", in brcmnand_edu_trans()
2025 dev_warn(ctrl->dev, "EDU RBUS error at addr %llx\n", in brcmnand_edu_trans()
2027 ret = -EIO; in brcmnand_edu_trans()
2030 ctrl->edu_pending = false; in brcmnand_edu_trans()
2046 ret = -EUCLEAN; in brcmnand_edu_trans()
2048 ret = -EBADMSG; in brcmnand_edu_trans()
2057 * - Is this descriptor the beginning or end of a linked list?
2058 * - What is the (DMA) address of the next descriptor in the linked list?
2068 desc->next_desc = lower_32_bits(next_desc); in brcmnand_fill_dma_desc()
2069 desc->next_desc_ext = upper_32_bits(next_desc); in brcmnand_fill_dma_desc()
2070 desc->cmd_irq = (dma_cmd << 24) | in brcmnand_fill_dma_desc()
2074 desc->cmd_irq |= 0x01 << 12; in brcmnand_fill_dma_desc()
2076 desc->dram_addr = lower_32_bits(buf); in brcmnand_fill_dma_desc()
2077 desc->dram_addr_ext = upper_32_bits(buf); in brcmnand_fill_dma_desc()
2078 desc->tfr_len = len; in brcmnand_fill_dma_desc()
2079 desc->total_len = len; in brcmnand_fill_dma_desc()
2080 desc->flash_addr = lower_32_bits(addr); in brcmnand_fill_dma_desc()
2081 desc->flash_addr_ext = upper_32_bits(addr); in brcmnand_fill_dma_desc()
2082 desc->cs = host->cs; in brcmnand_fill_dma_desc()
2083 desc->status_valid = 0x01; in brcmnand_fill_dma_desc()
2092 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_run()
2097 if (ctrl->nand_version > 0x0602) { in brcmnand_dma_run()
2104 ctrl->dma_pending = true; in brcmnand_dma_run()
2108 if (wait_for_completion_timeout(&ctrl->dma_done, timeo) <= 0) { in brcmnand_dma_run()
2109 dev_err(ctrl->dev, in brcmnand_dma_run()
2114 ctrl->dma_pending = false; in brcmnand_dma_run()
2121 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_dma_trans()
2125 buf_pa = dma_map_single(ctrl->dev, buf, len, dir); in brcmnand_dma_trans()
2126 if (dma_mapping_error(ctrl->dev, buf_pa)) { in brcmnand_dma_trans()
2127 dev_err(ctrl->dev, "unable to map buffer for DMA\n"); in brcmnand_dma_trans()
2128 return -ENOMEM; in brcmnand_dma_trans()
2131 brcmnand_fill_dma_desc(host, ctrl->dma_desc, addr, buf_pa, len, in brcmnand_dma_trans()
2134 brcmnand_dma_run(host, ctrl->dma_pa); in brcmnand_dma_trans()
2136 dma_unmap_single(ctrl->dev, buf_pa, len, dir); in brcmnand_dma_trans()
2138 if (ctrl->dma_desc->status_valid & FLASH_DMA_ECC_ERROR) in brcmnand_dma_trans()
2139 return -EBADMSG; in brcmnand_dma_trans()
2140 else if (ctrl->dma_desc->status_valid & FLASH_DMA_CORR_ERROR) in brcmnand_dma_trans()
2141 return -EUCLEAN; in brcmnand_dma_trans()
2154 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read_by_pio()
2166 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_read_by_pio()
2171 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_read_by_pio()
2176 mtd->oobsize / trans, in brcmnand_read_by_pio()
2177 host->hwcfg.sector_size_1k); in brcmnand_read_by_pio()
2179 if (ret != -EBADMSG) { in brcmnand_read_by_pio()
2183 ret = -EBADMSG; in brcmnand_read_by_pio()
2190 ret = -EUCLEAN; in brcmnand_read_by_pio()
2205 * On a real error, return a negative error code (-EBADMSG for ECC error), and
2208 * bitflips-per-ECC-sector to the caller.
2217 int page = addr >> chip->page_shift; in brcmstb_nand_verify_erased_page()
2226 ret = chip->ecc.read_page_raw(chip, buf, true, page); in brcmstb_nand_verify_erased_page()
2230 for (i = 0; i < chip->ecc.steps; i++) { in brcmstb_nand_verify_erased_page()
2231 ecc_chunk = buf + chip->ecc.size * i; in brcmstb_nand_verify_erased_page()
2234 ecc_bytes = chip->oob_poi + ecc.offset; in brcmstb_nand_verify_erased_page()
2236 ret = nand_check_erased_ecc_chunk(ecc_chunk, chip->ecc.size, in brcmstb_nand_verify_erased_page()
2239 chip->ecc.strength); in brcmstb_nand_verify_erased_page()
2253 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_read()
2259 dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf); in brcmnand_read()
2264 if (ctrl->dma_trans && (has_edu(ctrl) || !oob) && in brcmnand_read()
2266 err = ctrl->dma_trans(host, addr, buf, oob, in brcmnand_read()
2274 return -EIO; in brcmnand_read()
2282 memset(oob, 0x99, mtd->oobsize); in brcmnand_read()
2297 if ((ctrl->nand_version == 0x0700) || in brcmnand_read()
2298 (ctrl->nand_version == 0x0701)) { in brcmnand_read()
2309 if (ctrl->nand_version < 0x0702) { in brcmnand_read()
2317 dev_dbg(ctrl->dev, "uncorrectable error at 0x%llx\n", in brcmnand_read()
2319 mtd->ecc_stats.failed++; in brcmnand_read()
2332 dev_dbg(ctrl->dev, "corrected error at 0x%llx\n", in brcmnand_read()
2334 mtd->ecc_stats.corrected += corrected; in brcmnand_read()
2335 /* Always exceed the software-imposed threshold */ in brcmnand_read()
2336 return max(mtd->bitflip_threshold, corrected); in brcmnand_read()
2347 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; in brcmnand_read_page()
2351 return brcmnand_read(mtd, chip, host->last_addr, in brcmnand_read_page()
2352 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); in brcmnand_read_page()
2360 u8 *oob = oob_required ? (u8 *)chip->oob_poi : NULL; in brcmnand_read_page_raw()
2366 ret = brcmnand_read(mtd, chip, host->last_addr, in brcmnand_read_page_raw()
2367 mtd->writesize >> FC_SHIFT, (u32 *)buf, oob); in brcmnand_read_page_raw()
2376 return brcmnand_read(mtd, chip, (u64)page << chip->page_shift, in brcmnand_read_oob()
2377 mtd->writesize >> FC_SHIFT, in brcmnand_read_oob()
2378 NULL, (u8 *)chip->oob_poi); in brcmnand_read_oob()
2387 brcmnand_read(mtd, chip, (u64)page << chip->page_shift, in brcmnand_read_oob_raw()
2388 mtd->writesize >> FC_SHIFT, in brcmnand_read_oob_raw()
2389 NULL, (u8 *)chip->oob_poi); in brcmnand_read_oob_raw()
2398 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_write()
2399 unsigned int i, j, trans = mtd->writesize >> FC_SHIFT; in brcmnand_write()
2402 dev_dbg(ctrl->dev, "write %llx <- %p\n", (unsigned long long)addr, buf); in brcmnand_write()
2405 dev_warn(ctrl->dev, "unaligned buffer: %p\n", buf); in brcmnand_write()
2411 for (i = 0; i < ctrl->max_oob; i += 4) in brcmnand_write()
2414 if (mtd->oops_panic_write) in brcmnand_write()
2419 if (ctrl->dma_trans(host, addr, (u32 *)buf, oob, mtd->writesize, in brcmnand_write()
2422 ret = -EIO; in brcmnand_write()
2432 brcmnand_soc_data_bus_prepare(ctrl->soc, false); in brcmnand_write()
2437 brcmnand_soc_data_bus_unprepare(ctrl->soc, false); in brcmnand_write()
2445 mtd->oobsize / trans, in brcmnand_write()
2446 host->hwcfg.sector_size_1k); in brcmnand_write()
2454 dev_info(ctrl->dev, "program failed at %llx\n", in brcmnand_write()
2456 ret = -EIO; in brcmnand_write()
2470 void *oob = oob_required ? chip->oob_poi : NULL; in brcmnand_write_page()
2473 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); in brcmnand_write_page()
2483 void *oob = oob_required ? chip->oob_poi : NULL; in brcmnand_write_page_raw()
2487 brcmnand_write(mtd, chip, host->last_addr, (const u32 *)buf, oob); in brcmnand_write_page_raw()
2496 (u64)page << chip->page_shift, NULL, in brcmnand_write_oob()
2497 chip->oob_poi); in brcmnand_write_oob()
2507 ret = brcmnand_write(mtd, chip, (u64)page << chip->page_shift, NULL, in brcmnand_write_oob_raw()
2508 (u8 *)chip->oob_poi); in brcmnand_write_oob_raw()
2515 * Per-CS setup (1 NAND device)
2521 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_set_cfg()
2522 struct nand_chip *chip = &host->chip; in brcmnand_set_cfg()
2523 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_set_cfg()
2524 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2526 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_set_cfg()
2531 if (ctrl->block_sizes) { in brcmnand_set_cfg()
2534 for (i = 0, found = 0; ctrl->block_sizes[i]; i++) in brcmnand_set_cfg()
2535 if (ctrl->block_sizes[i] * 1024 == cfg->block_size) { in brcmnand_set_cfg()
2540 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2541 cfg->block_size); in brcmnand_set_cfg()
2542 return -EINVAL; in brcmnand_set_cfg()
2545 block_size = ffs(cfg->block_size) - ffs(BRCMNAND_MIN_BLOCKSIZE); in brcmnand_set_cfg()
2548 if (cfg->block_size < BRCMNAND_MIN_BLOCKSIZE || (ctrl->max_block_size && in brcmnand_set_cfg()
2549 cfg->block_size > ctrl->max_block_size)) { in brcmnand_set_cfg()
2550 dev_warn(ctrl->dev, "invalid block size %u\n", in brcmnand_set_cfg()
2551 cfg->block_size); in brcmnand_set_cfg()
2555 if (ctrl->page_sizes) { in brcmnand_set_cfg()
2558 for (i = 0, found = 0; ctrl->page_sizes[i]; i++) in brcmnand_set_cfg()
2559 if (ctrl->page_sizes[i] == cfg->page_size) { in brcmnand_set_cfg()
2564 dev_warn(ctrl->dev, "invalid page size %u\n", in brcmnand_set_cfg()
2565 cfg->page_size); in brcmnand_set_cfg()
2566 return -EINVAL; in brcmnand_set_cfg()
2569 page_size = ffs(cfg->page_size) - ffs(BRCMNAND_MIN_PAGESIZE); in brcmnand_set_cfg()
2572 if (cfg->page_size < BRCMNAND_MIN_PAGESIZE || (ctrl->max_page_size && in brcmnand_set_cfg()
2573 cfg->page_size > ctrl->max_page_size)) { in brcmnand_set_cfg()
2574 dev_warn(ctrl->dev, "invalid page size %u\n", cfg->page_size); in brcmnand_set_cfg()
2575 return -EINVAL; in brcmnand_set_cfg()
2578 if (fls64(cfg->device_size) < fls64(BRCMNAND_MIN_DEVSIZE)) { in brcmnand_set_cfg()
2579 dev_warn(ctrl->dev, "invalid device size 0x%llx\n", in brcmnand_set_cfg()
2580 (unsigned long long)cfg->device_size); in brcmnand_set_cfg()
2581 return -EINVAL; in brcmnand_set_cfg()
2583 device_size = fls64(cfg->device_size) - fls64(BRCMNAND_MIN_DEVSIZE); in brcmnand_set_cfg()
2585 tmp = (cfg->blk_adr_bytes << CFG_BLK_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2586 (cfg->col_adr_bytes << CFG_COL_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2587 (cfg->ful_adr_bytes << CFG_FUL_ADR_BYTES_SHIFT) | in brcmnand_set_cfg()
2588 (!!(cfg->device_width == 16) << CFG_BUS_WIDTH_SHIFT) | in brcmnand_set_cfg()
2591 tmp |= (page_size << ctrl->page_size_shift) | in brcmnand_set_cfg()
2604 if (ctrl->nand_version >= 0x0302) { in brcmnand_set_cfg()
2605 tmp |= cfg->ecc_level << ctrl->ecc_level_shift; in brcmnand_set_cfg()
2606 tmp |= cfg->spare_area_size; in brcmnand_set_cfg()
2610 brcmnand_set_sector_size_1k(host, cfg->sector_size_1k); in brcmnand_set_cfg()
2612 /* threshold = ceil(BCH-level * 0.75) */ in brcmnand_set_cfg()
2613 brcmnand_wr_corr_thresh(host, DIV_ROUND_UP(chip->ecc.strength * 3, 4)); in brcmnand_set_cfg()
2622 "%lluMiB total, %uKiB blocks, %u%s pages, %uB OOB, %u-bit", in brcmnand_print_cfg()
2623 (unsigned long long)cfg->device_size >> 20, in brcmnand_print_cfg()
2624 cfg->block_size >> 10, in brcmnand_print_cfg()
2625 cfg->page_size >= 1024 ? cfg->page_size >> 10 : cfg->page_size, in brcmnand_print_cfg()
2626 cfg->page_size >= 1024 ? "KiB" : "B", in brcmnand_print_cfg()
2627 cfg->spare_area_size, cfg->device_width); in brcmnand_print_cfg()
2630 if (is_hamming_ecc(host->ctrl, cfg)) in brcmnand_print_cfg()
2632 else if (cfg->sector_size_1k) in brcmnand_print_cfg()
2633 sprintf(buf, ", BCH-%u (1KiB sector)", cfg->ecc_level << 1); in brcmnand_print_cfg()
2635 sprintf(buf, ", BCH-%u", cfg->ecc_level); in brcmnand_print_cfg()
2640 * roundup(log2(size / page-size) / 8)
2642 * NB: the following does not "round up" for non-power-of-2 'size'; but this is
2647 return ALIGN(ilog2(size) - ilog2(writesize), 8) >> 3; in get_blk_adr_bytes()
2652 struct mtd_info *mtd = nand_to_mtd(&host->chip); in brcmnand_setup_dev()
2653 struct nand_chip *chip = &host->chip; in brcmnand_setup_dev()
2655 nanddev_get_ecc_requirements(&chip->base); in brcmnand_setup_dev()
2657 nanddev_get_memorg(&chip->base); in brcmnand_setup_dev()
2658 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_setup_dev()
2659 struct brcmnand_cfg *cfg = &host->hwcfg; in brcmnand_setup_dev()
2667 "brcm,nand-oob-sector-size", in brcmnand_setup_dev()
2671 cfg->spare_area_size = mtd->oobsize / in brcmnand_setup_dev()
2672 (mtd->writesize >> FC_SHIFT); in brcmnand_setup_dev()
2674 cfg->spare_area_size = oob_sector; in brcmnand_setup_dev()
2676 if (cfg->spare_area_size > ctrl->max_oob) in brcmnand_setup_dev()
2677 cfg->spare_area_size = ctrl->max_oob; in brcmnand_setup_dev()
2682 mtd->oobsize = cfg->spare_area_size * (mtd->writesize >> FC_SHIFT); in brcmnand_setup_dev()
2683 memorg->oobsize = mtd->oobsize; in brcmnand_setup_dev()
2685 cfg->device_size = mtd->size; in brcmnand_setup_dev()
2686 cfg->block_size = mtd->erasesize; in brcmnand_setup_dev()
2687 cfg->page_size = mtd->writesize; in brcmnand_setup_dev()
2688 cfg->device_width = (chip->options & NAND_BUSWIDTH_16) ? 16 : 8; in brcmnand_setup_dev()
2689 cfg->col_adr_bytes = 2; in brcmnand_setup_dev()
2690 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); in brcmnand_setup_dev()
2692 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) { in brcmnand_setup_dev()
2693 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", in brcmnand_setup_dev()
2694 chip->ecc.engine_type); in brcmnand_setup_dev()
2695 return -EINVAL; in brcmnand_setup_dev()
2698 if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) { in brcmnand_setup_dev()
2699 if (chip->ecc.strength == 1 && chip->ecc.size == 512) in brcmnand_setup_dev()
2700 /* Default to Hamming for 1-bit ECC, if unspecified */ in brcmnand_setup_dev()
2701 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in brcmnand_setup_dev()
2704 chip->ecc.algo = NAND_ECC_ALGO_BCH; in brcmnand_setup_dev()
2707 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING && in brcmnand_setup_dev()
2708 (chip->ecc.strength != 1 || chip->ecc.size != 512)) { in brcmnand_setup_dev()
2709 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", in brcmnand_setup_dev()
2710 chip->ecc.strength, chip->ecc.size); in brcmnand_setup_dev()
2711 return -EINVAL; in brcmnand_setup_dev()
2714 if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE && in brcmnand_setup_dev()
2715 (!chip->ecc.size || !chip->ecc.strength)) { in brcmnand_setup_dev()
2716 if (requirements->step_size && requirements->strength) { in brcmnand_setup_dev()
2718 chip->ecc.size = requirements->step_size; in brcmnand_setup_dev()
2719 chip->ecc.strength = requirements->strength; in brcmnand_setup_dev()
2720 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", in brcmnand_setup_dev()
2721 chip->ecc.size, chip->ecc.strength); in brcmnand_setup_dev()
2725 switch (chip->ecc.size) { in brcmnand_setup_dev()
2727 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) in brcmnand_setup_dev()
2728 cfg->ecc_level = 15; in brcmnand_setup_dev()
2730 cfg->ecc_level = chip->ecc.strength; in brcmnand_setup_dev()
2731 cfg->sector_size_1k = 0; in brcmnand_setup_dev()
2734 if (!(ctrl->features & BRCMNAND_HAS_1K_SECTORS)) { in brcmnand_setup_dev()
2735 dev_err(ctrl->dev, "1KB sectors not supported\n"); in brcmnand_setup_dev()
2736 return -EINVAL; in brcmnand_setup_dev()
2738 if (chip->ecc.strength & 0x1) { in brcmnand_setup_dev()
2739 dev_err(ctrl->dev, in brcmnand_setup_dev()
2741 return -EINVAL; in brcmnand_setup_dev()
2744 cfg->ecc_level = chip->ecc.strength >> 1; in brcmnand_setup_dev()
2745 cfg->sector_size_1k = 1; in brcmnand_setup_dev()
2748 dev_err(ctrl->dev, "unsupported ECC size: %d\n", in brcmnand_setup_dev()
2749 chip->ecc.size); in brcmnand_setup_dev()
2750 return -EINVAL; in brcmnand_setup_dev()
2753 cfg->ful_adr_bytes = cfg->blk_adr_bytes; in brcmnand_setup_dev()
2754 if (mtd->writesize > 512) in brcmnand_setup_dev()
2755 cfg->ful_adr_bytes += cfg->col_adr_bytes; in brcmnand_setup_dev()
2757 cfg->ful_adr_bytes += 1; in brcmnand_setup_dev()
2766 dev_info(ctrl->dev, "detected %s\n", msg); in brcmnand_setup_dev()
2769 offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_ACC_CONTROL); in brcmnand_setup_dev()
2775 if (ctrl->nand_version >= 0x0702) in brcmnand_setup_dev()
2778 if (ctrl->features & BRCMNAND_HAS_PREFETCH) in brcmnand_setup_dev()
2792 chip->options |= NAND_NO_SUBPAGE_WRITE; in brcmnand_attach_chip()
2798 chip->options |= NAND_USES_DMA; in brcmnand_attach_chip()
2800 if (chip->bbt_options & NAND_BBT_USE_FLASH) in brcmnand_attach_chip()
2801 chip->bbt_options |= NAND_BBT_NO_OOB; in brcmnand_attach_chip()
2804 return -ENXIO; in brcmnand_attach_chip()
2806 chip->ecc.size = host->hwcfg.sector_size_1k ? 1024 : 512; in brcmnand_attach_chip()
2809 mtd->bitflip_threshold = 1; in brcmnand_attach_chip()
2814 if (is_hamming_ecc(host->ctrl, &host->hwcfg)) { in brcmnand_attach_chip()
2815 chip->ecc.write_oob = brcmnand_write_oob_raw; in brcmnand_attach_chip()
2816 chip->ecc.read_oob = brcmnand_read_oob_raw; in brcmnand_attach_chip()
2829 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_init_cs()
2830 struct device *dev = ctrl->dev; in brcmnand_init_cs()
2836 mtd = nand_to_mtd(&host->chip); in brcmnand_init_cs()
2837 chip = &host->chip; in brcmnand_init_cs()
2840 mtd->name = devm_kasprintf(dev, GFP_KERNEL, "brcmnand.%d", in brcmnand_init_cs()
2841 host->cs); in brcmnand_init_cs()
2842 if (!mtd->name) in brcmnand_init_cs()
2843 return -ENOMEM; in brcmnand_init_cs()
2845 mtd->owner = THIS_MODULE; in brcmnand_init_cs()
2846 mtd->dev.parent = dev; in brcmnand_init_cs()
2848 chip->legacy.cmd_ctrl = brcmnand_cmd_ctrl; in brcmnand_init_cs()
2849 chip->legacy.cmdfunc = brcmnand_cmdfunc; in brcmnand_init_cs()
2850 chip->legacy.waitfunc = brcmnand_waitfunc; in brcmnand_init_cs()
2851 chip->legacy.read_byte = brcmnand_read_byte; in brcmnand_init_cs()
2852 chip->legacy.read_buf = brcmnand_read_buf; in brcmnand_init_cs()
2853 chip->legacy.write_buf = brcmnand_write_buf; in brcmnand_init_cs()
2855 chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in brcmnand_init_cs()
2856 chip->ecc.read_page = brcmnand_read_page; in brcmnand_init_cs()
2857 chip->ecc.write_page = brcmnand_write_page; in brcmnand_init_cs()
2858 chip->ecc.read_page_raw = brcmnand_read_page_raw; in brcmnand_init_cs()
2859 chip->ecc.write_page_raw = brcmnand_write_page_raw; in brcmnand_init_cs()
2860 chip->ecc.write_oob_raw = brcmnand_write_oob_raw; in brcmnand_init_cs()
2861 chip->ecc.read_oob_raw = brcmnand_read_oob_raw; in brcmnand_init_cs()
2862 chip->ecc.read_oob = brcmnand_read_oob; in brcmnand_init_cs()
2863 chip->ecc.write_oob = brcmnand_write_oob; in brcmnand_init_cs()
2865 chip->controller = &ctrl->controller; in brcmnand_init_cs()
2872 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_init_cs()
2890 struct brcmnand_controller *ctrl = host->ctrl; in brcmnand_save_restore_cs_config()
2891 u16 cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG); in brcmnand_save_restore_cs_config()
2892 u16 cfg_ext_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2894 u16 acc_control_offs = brcmnand_cs_offset(ctrl, host->cs, in brcmnand_save_restore_cs_config()
2896 u16 t1_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING1); in brcmnand_save_restore_cs_config()
2897 u16 t2_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_TIMING2); in brcmnand_save_restore_cs_config()
2900 nand_writereg(ctrl, cfg_offs, host->hwcfg.config); in brcmnand_save_restore_cs_config()
2903 host->hwcfg.config_ext); in brcmnand_save_restore_cs_config()
2904 nand_writereg(ctrl, acc_control_offs, host->hwcfg.acc_control); in brcmnand_save_restore_cs_config()
2905 nand_writereg(ctrl, t1_offs, host->hwcfg.timing_1); in brcmnand_save_restore_cs_config()
2906 nand_writereg(ctrl, t2_offs, host->hwcfg.timing_2); in brcmnand_save_restore_cs_config()
2908 host->hwcfg.config = nand_readreg(ctrl, cfg_offs); in brcmnand_save_restore_cs_config()
2910 host->hwcfg.config_ext = in brcmnand_save_restore_cs_config()
2912 host->hwcfg.acc_control = nand_readreg(ctrl, acc_control_offs); in brcmnand_save_restore_cs_config()
2913 host->hwcfg.timing_1 = nand_readreg(ctrl, t1_offs); in brcmnand_save_restore_cs_config()
2914 host->hwcfg.timing_2 = nand_readreg(ctrl, t2_offs); in brcmnand_save_restore_cs_config()
2923 list_for_each_entry(host, &ctrl->host_list, node) in brcmnand_suspend()
2926 ctrl->nand_cs_nand_select = brcmnand_read_reg(ctrl, BRCMNAND_CS_SELECT); in brcmnand_suspend()
2927 ctrl->nand_cs_nand_xor = brcmnand_read_reg(ctrl, BRCMNAND_CS_XOR); in brcmnand_suspend()
2928 ctrl->corr_stat_threshold = in brcmnand_suspend()
2932 ctrl->flash_dma_mode = flash_dma_readl(ctrl, FLASH_DMA_MODE); in brcmnand_suspend()
2934 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_suspend()
2945 flash_dma_writel(ctrl, FLASH_DMA_MODE, ctrl->flash_dma_mode); in brcmnand_resume()
2950 ctrl->edu_config = edu_readl(ctrl, EDU_CONFIG); in brcmnand_resume()
2951 edu_writel(ctrl, EDU_CONFIG, ctrl->edu_config); in brcmnand_resume()
2956 brcmnand_write_reg(ctrl, BRCMNAND_CS_SELECT, ctrl->nand_cs_nand_select); in brcmnand_resume()
2957 brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor); in brcmnand_resume()
2959 ctrl->corr_stat_threshold); in brcmnand_resume()
2960 if (ctrl->soc) { in brcmnand_resume()
2961 /* Clear/re-enable interrupt */ in brcmnand_resume()
2962 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_resume()
2963 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_resume()
2966 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_resume()
2967 struct nand_chip *chip = &host->chip; in brcmnand_resume()
2971 /* Reset the chip, required by some chips after power-up */ in brcmnand_resume()
2985 { .compatible = "brcm,brcmnand-v2.1" },
2986 { .compatible = "brcm,brcmnand-v2.2" },
2987 { .compatible = "brcm,brcmnand-v4.0" },
2988 { .compatible = "brcm,brcmnand-v5.0" },
2989 { .compatible = "brcm,brcmnand-v6.0" },
2990 { .compatible = "brcm,brcmnand-v6.1" },
2991 { .compatible = "brcm,brcmnand-v6.2" },
2992 { .compatible = "brcm,brcmnand-v7.0" },
2993 { .compatible = "brcm,brcmnand-v7.1" },
2994 { .compatible = "brcm,brcmnand-v7.2" },
2995 { .compatible = "brcm,brcmnand-v7.3" },
3005 struct device *dev = &pdev->dev; in brcmnand_edu_setup()
3006 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_edu_setup()
3010 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-edu"); in brcmnand_edu_setup()
3012 ctrl->edu_base = devm_ioremap_resource(dev, res); in brcmnand_edu_setup()
3013 if (IS_ERR(ctrl->edu_base)) in brcmnand_edu_setup()
3014 return PTR_ERR(ctrl->edu_base); in brcmnand_edu_setup()
3016 ctrl->edu_offsets = edu_regs; in brcmnand_edu_setup()
3025 ctrl->edu_irq = platform_get_irq_optional(pdev, 1); in brcmnand_edu_setup()
3026 if (ctrl->edu_irq < 0) { in brcmnand_edu_setup()
3030 ret = devm_request_irq(dev, ctrl->edu_irq, in brcmnand_edu_setup()
3032 "brcmnand-edu", ctrl); in brcmnand_edu_setup()
3034 dev_err(ctrl->dev, "can't allocate IRQ %d: error %d\n", in brcmnand_edu_setup()
3035 ctrl->edu_irq, ret); in brcmnand_edu_setup()
3040 ctrl->edu_irq); in brcmnand_edu_setup()
3049 struct brcmnand_platform_data *pd = dev_get_platdata(&pdev->dev); in brcmnand_probe()
3050 struct device *dev = &pdev->dev; in brcmnand_probe()
3051 struct device_node *dn = dev->of_node, *child; in brcmnand_probe()
3058 return -ENODEV; in brcmnand_probe()
3062 return -ENOMEM; in brcmnand_probe()
3065 ctrl->dev = dev; in brcmnand_probe()
3066 ctrl->soc = soc; in brcmnand_probe()
3069 * that a non-memory mapped IO access path must be used in brcmnand_probe()
3071 if (brcmnand_soc_has_ops(ctrl->soc)) in brcmnand_probe()
3074 init_completion(&ctrl->done); in brcmnand_probe()
3075 init_completion(&ctrl->dma_done); in brcmnand_probe()
3076 init_completion(&ctrl->edu_done); in brcmnand_probe()
3077 nand_controller_init(&ctrl->controller); in brcmnand_probe()
3078 ctrl->controller.ops = &brcmnand_controller_ops; in brcmnand_probe()
3079 INIT_LIST_HEAD(&ctrl->host_list); in brcmnand_probe()
3083 ctrl->nand_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
3084 if (IS_ERR(ctrl->nand_base) && !brcmnand_soc_has_ops(soc)) in brcmnand_probe()
3085 return PTR_ERR(ctrl->nand_base); in brcmnand_probe()
3088 ctrl->clk = devm_clk_get(dev, "nand"); in brcmnand_probe()
3089 if (!IS_ERR(ctrl->clk)) { in brcmnand_probe()
3090 ret = clk_prepare_enable(ctrl->clk); in brcmnand_probe()
3094 ret = PTR_ERR(ctrl->clk); in brcmnand_probe()
3095 if (ret == -EPROBE_DEFER) in brcmnand_probe()
3098 ctrl->clk = NULL; in brcmnand_probe()
3110 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand-cache"); in brcmnand_probe()
3112 ctrl->nand_fc = devm_ioremap_resource(dev, res); in brcmnand_probe()
3113 if (IS_ERR(ctrl->nand_fc)) { in brcmnand_probe()
3114 ret = PTR_ERR(ctrl->nand_fc); in brcmnand_probe()
3118 ctrl->nand_fc = ctrl->nand_base + in brcmnand_probe()
3119 ctrl->reg_offsets[BRCMNAND_FC_BASE]; in brcmnand_probe()
3123 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash-dma"); in brcmnand_probe()
3125 ctrl->flash_dma_base = devm_ioremap_resource(dev, res); in brcmnand_probe()
3126 if (IS_ERR(ctrl->flash_dma_base)) { in brcmnand_probe()
3127 ret = PTR_ERR(ctrl->flash_dma_base); in brcmnand_probe()
3134 ret = -EIO; in brcmnand_probe()
3135 if (ctrl->nand_version >= 0x0700) in brcmnand_probe()
3136 ret = dma_set_mask_and_coherent(&pdev->dev, in brcmnand_probe()
3139 ret = dma_set_mask_and_coherent(&pdev->dev, in brcmnand_probe()
3144 /* linked-list and stop on error */ in brcmnand_probe()
3149 ctrl->dma_desc = dmam_alloc_coherent(dev, in brcmnand_probe()
3150 sizeof(*ctrl->dma_desc), in brcmnand_probe()
3151 &ctrl->dma_pa, GFP_KERNEL); in brcmnand_probe()
3152 if (!ctrl->dma_desc) { in brcmnand_probe()
3153 ret = -ENOMEM; in brcmnand_probe()
3157 ctrl->dma_irq = platform_get_irq(pdev, 1); in brcmnand_probe()
3158 if ((int)ctrl->dma_irq < 0) { in brcmnand_probe()
3160 ret = -ENODEV; in brcmnand_probe()
3164 ret = devm_request_irq(dev, ctrl->dma_irq, in brcmnand_probe()
3169 ctrl->dma_irq, ret); in brcmnand_probe()
3175 ctrl->dma_trans = brcmnand_dma_trans; in brcmnand_probe()
3183 ctrl->dma_trans = brcmnand_edu_trans; in brcmnand_probe()
3192 if (ctrl->features & BRCMNAND_HAS_WP) { in brcmnand_probe()
3201 ctrl->irq = platform_get_irq_optional(pdev, 0); in brcmnand_probe()
3202 if (ctrl->irq > 0) { in brcmnand_probe()
3208 ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0, in brcmnand_probe()
3212 ctrl->soc->ctlrdy_ack(ctrl->soc); in brcmnand_probe()
3213 ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true); in brcmnand_probe()
3216 ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0, in brcmnand_probe()
3221 ctrl->irq, ret); in brcmnand_probe()
3232 ret = -ENOMEM; in brcmnand_probe()
3235 host->pdev = pdev; in brcmnand_probe()
3236 host->ctrl = ctrl; in brcmnand_probe()
3238 ret = of_property_read_u32(child, "reg", &host->cs); in brcmnand_probe()
3240 dev_err(dev, "can't get chip-select\n"); in brcmnand_probe()
3245 nand_set_flash_node(&host->chip, child); in brcmnand_probe()
3249 if (ret == -EPROBE_DEFER) { in brcmnand_probe()
3254 continue; /* Try all chip-selects */ in brcmnand_probe()
3257 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
3261 if (!list_empty(&ctrl->host_list)) in brcmnand_probe()
3265 ret = -ENODEV; in brcmnand_probe()
3272 ret = -ENOMEM; in brcmnand_probe()
3275 host->pdev = pdev; in brcmnand_probe()
3276 host->ctrl = ctrl; in brcmnand_probe()
3277 host->cs = pd->chip_select; in brcmnand_probe()
3278 host->chip.ecc.size = pd->ecc_stepsize; in brcmnand_probe()
3279 host->chip.ecc.strength = pd->ecc_strength; in brcmnand_probe()
3281 ret = brcmnand_init_cs(host, pd->part_probe_types); in brcmnand_probe()
3285 list_add_tail(&host->node, &ctrl->host_list); in brcmnand_probe()
3287 /* No chip-selects could initialize properly */ in brcmnand_probe()
3288 if (list_empty(&ctrl->host_list)) { in brcmnand_probe()
3289 ret = -ENODEV; in brcmnand_probe()
3296 clk_disable_unprepare(ctrl->clk); in brcmnand_probe()
3304 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); in brcmnand_remove()
3309 list_for_each_entry(host, &ctrl->host_list, node) { in brcmnand_remove()
3310 chip = &host->chip; in brcmnand_remove()
3316 clk_disable_unprepare(ctrl->clk); in brcmnand_remove()
3318 dev_set_drvdata(&pdev->dev, NULL); in brcmnand_remove()
3328 MODULE_ALIAS("platform:brcmnand");