Lines Matching +full:itap +full:- +full:del +full:- +full:sel +full:- +full:sdr12
1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
108 "ti,itap-del-sel-legacy",
110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
111 "ti,itap-del-sel-mmc-hs",
113 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
114 "ti,itap-del-sel-sd-hs",
116 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
117 "ti,itap-del-sel-sdr12",
119 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
120 "ti,itap-del-sel-sdr25",
122 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
125 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
128 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
132 "ti,itap-del-sel-ddr52",
134 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
137 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
183 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, in sdhci_am654_setup_dll()
186 if (sdhci_am654->flags & FREQSEL_2_BIT) { in sdhci_am654_setup_dll()
204 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); in sdhci_am654_setup_dll()
215 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, in sdhci_am654_setup_dll()
220 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; in sdhci_am654_setup_dll()
224 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; in sdhci_am654_setup_dll()
225 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); in sdhci_am654_setup_dll()
228 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, in sdhci_am654_setup_dll()
234 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, in sdhci_am654_setup_dll()
237 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); in sdhci_am654_setup_dll()
246 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, in sdhci_am654_write_itapdly()
248 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, in sdhci_am654_write_itapdly()
250 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, in sdhci_am654_write_itapdly()
252 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); in sdhci_am654_write_itapdly()
260 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); in sdhci_am654_setup_delay_chain()
264 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); in sdhci_am654_setup_delay_chain()
266 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], in sdhci_am654_setup_delay_chain()
267 sdhci_am654->itap_del_ena[timing]); in sdhci_am654_setup_delay_chain()
274 unsigned char timing = host->mmc->ios.timing; in sdhci_am654_set_clock()
278 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); in sdhci_am654_set_clock()
283 otap_del_sel = sdhci_am654->otap_del_sel[timing]; in sdhci_am654_set_clock()
291 if (sdhci_am654->flags & STRBSEL_4_BIT) in sdhci_am654_set_clock()
296 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; in sdhci_am654_set_clock()
299 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); in sdhci_am654_set_clock()
303 sdhci_am654->dll_enable = true; in sdhci_am654_set_clock()
306 sdhci_am654->itap_del_ena[timing] = 0x1; in sdhci_am654_set_clock()
307 sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1]; in sdhci_am654_set_clock()
310 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], in sdhci_am654_set_clock()
311 sdhci_am654->itap_del_ena[timing]); in sdhci_am654_set_clock()
314 sdhci_am654->dll_enable = false; in sdhci_am654_set_clock()
317 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, in sdhci_am654_set_clock()
318 sdhci_am654->clkbuf_sel); in sdhci_am654_set_clock()
326 unsigned char timing = host->mmc->ios.timing; in sdhci_j721e_4bit_set_clock()
333 otap_del_sel = sdhci_am654->otap_del_sel[timing]; in sdhci_j721e_4bit_set_clock()
340 itap_del_ena = sdhci_am654->itap_del_ena[timing]; in sdhci_j721e_4bit_set_clock()
341 itap_del_sel = sdhci_am654->itap_del_sel[timing]; in sdhci_j721e_4bit_set_clock()
347 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, in sdhci_j721e_4bit_set_clock()
349 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); in sdhci_j721e_4bit_set_clock()
350 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); in sdhci_j721e_4bit_set_clock()
351 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, in sdhci_j721e_4bit_set_clock()
352 sdhci_am654->clkbuf_sel); in sdhci_j721e_4bit_set_clock()
359 writeb(val, host->ioaddr + reg); in sdhci_am654_write_power_on()
361 return readb(host->ioaddr + reg); in sdhci_am654_write_power_on()
367 unsigned char timing = host->mmc->ios.timing; in sdhci_am654_write_b()
383 writeb(val, host->ioaddr + reg); in sdhci_am654_write_b()
395 dev_info(mmc_dev(host->mmc), "Power on failed\n"); in sdhci_am654_write_b()
407 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { in sdhci_am654_reset()
438 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_am654_cqhci_irq()
444 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1)
449 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; in sdhci_am654_calculate_itap() local
451 struct device *dev = mmc_dev(host->mmc); in sdhci_am654_calculate_itap()
453 int prev_fail_end = -1; in sdhci_am654_calculate_itap()
459 if (fail_window->length == ITAPDLY_LENGTH) { in sdhci_am654_calculate_itap()
464 first_fail_start = fail_window->start; in sdhci_am654_calculate_itap()
465 last_fail_end = fail_window[num_fails - 1].end; in sdhci_am654_calculate_itap()
470 pass_length = start_fail - (prev_fail_end + 1); in sdhci_am654_calculate_itap()
480 pass_length = ITAPDLY_LAST_INDEX - last_fail_end; in sdhci_am654_calculate_itap()
482 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start; in sdhci_am654_calculate_itap()
490 itap = pass_window.start + (pass_window.length >> 1); in sdhci_am654_calculate_itap()
492 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH; in sdhci_am654_calculate_itap()
494 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap; in sdhci_am654_calculate_itap()
502 unsigned char timing = host->mmc->ios.timing; in sdhci_am654_platform_execute_tuning()
504 u8 curr_pass, itap; in sdhci_am654_platform_execute_tuning() local
511 sdhci_am654->itap_del_ena[timing] = 0x1; in sdhci_am654_platform_execute_tuning()
513 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { in sdhci_am654_platform_execute_tuning()
514 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); in sdhci_am654_platform_execute_tuning()
516 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); in sdhci_am654_platform_execute_tuning()
519 fail_window[fail_index].start = itap; in sdhci_am654_platform_execute_tuning()
522 fail_window[fail_index].end = itap; in sdhci_am654_platform_execute_tuning()
535 itap = sdhci_am654_calculate_itap(host, fail_window, fail_index, in sdhci_am654_platform_execute_tuning()
536 sdhci_am654->dll_enable); in sdhci_am654_platform_execute_tuning()
538 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); in sdhci_am654_platform_execute_tuning()
541 sdhci_am654->itap_del_sel[timing] = itap; in sdhci_am654_platform_execute_tuning()
647 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), in sdhci_am654_cqe_add_host()
650 return -ENOMEM; in sdhci_am654_cqe_add_host()
652 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; in sdhci_am654_cqe_add_host()
653 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; in sdhci_am654_cqe_add_host()
654 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_am654_cqe_add_host()
655 cq_host->ops = &sdhci_am654_cqhci_ops; in sdhci_am654_cqe_add_host()
657 host->mmc->caps2 |= MMC_CAP2_CQE; in sdhci_am654_cqe_add_host()
659 return cqhci_init(cq_host, host->mmc, 1); in sdhci_am654_cqe_add_host()
665 struct device *dev = mmc_dev(host->mmc); in sdhci_am654_get_otap_delay()
672 &sdhci_am654->otap_del_sel[i]); in sdhci_am654_get_otap_delay()
675 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n"); in sdhci_am654_get_otap_delay()
682 * if an otap-del-sel value is not found in sdhci_am654_get_otap_delay()
685 host->mmc->caps &= ~td[i].capability; in sdhci_am654_get_otap_delay()
687 host->mmc->caps2 &= ~td[i].capability; in sdhci_am654_get_otap_delay()
692 &sdhci_am654->itap_del_sel[i]); in sdhci_am654_get_otap_delay()
694 sdhci_am654->itap_del_ena[i] = 0x1; in sdhci_am654_get_otap_delay()
712 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); in sdhci_am654_init()
714 if (sdhci_am654->flags & DLL_CALIB) { in sdhci_am654_init()
715 regmap_read(sdhci_am654->base, PHY_STAT1, &val); in sdhci_am654_init()
718 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, in sdhci_am654_init()
720 ret = regmap_read_poll_timeout(sdhci_am654->base, in sdhci_am654_init()
730 if (sdhci_am654->flags & IOMUX_PRESENT) in sdhci_am654_init()
731 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, in sdhci_am654_init()
735 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) in sdhci_am654_init()
738 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, in sdhci_am654_init()
742 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, in sdhci_am654_init()
771 struct device *dev = &pdev->dev; in sdhci_am654_get_of_property()
775 if (sdhci_am654->flags & DLL_PRESENT) { in sdhci_am654_get_of_property()
776 ret = device_property_read_u32(dev, "ti,trm-icp", in sdhci_am654_get_of_property()
777 &sdhci_am654->trm_icp); in sdhci_am654_get_of_property()
781 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", in sdhci_am654_get_of_property()
788 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; in sdhci_am654_get_of_property()
791 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; in sdhci_am654_get_of_property()
794 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; in sdhci_am654_get_of_property()
797 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; in sdhci_am654_get_of_property()
800 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; in sdhci_am654_get_of_property()
804 return -EINVAL; in sdhci_am654_get_of_property()
808 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); in sdhci_am654_get_of_property()
809 device_property_read_u32(dev, "ti,clkbuf-sel", in sdhci_am654_get_of_property()
810 &sdhci_am654->clkbuf_sel); in sdhci_am654_get_of_property()
812 if (device_property_read_bool(dev, "ti,fails-without-test-cd")) in sdhci_am654_get_of_property()
813 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; in sdhci_am654_get_of_property()
822 .compatible = "ti,am654-sdhci-5.1",
826 .compatible = "ti,j721e-sdhci-8bit",
830 .compatible = "ti,j721e-sdhci-4bit",
834 .compatible = "ti,am64-sdhci-8bit",
838 .compatible = "ti,am64-sdhci-4bit",
842 .compatible = "ti,am62-sdhci",
858 struct device *dev = &pdev->dev; in sdhci_am654_probe()
862 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); in sdhci_am654_probe()
863 drvdata = match->data; in sdhci_am654_probe()
867 if (soc && soc->data) in sdhci_am654_probe()
868 drvdata = soc->data; in sdhci_am654_probe()
870 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); in sdhci_am654_probe()
876 sdhci_am654->flags = drvdata->flags; in sdhci_am654_probe()
885 pltfm_host->clk = clk_xin; in sdhci_am654_probe()
893 sdhci_am654->base = devm_regmap_init_mmio(dev, base, in sdhci_am654_probe()
895 if (IS_ERR(sdhci_am654->base)) { in sdhci_am654_probe()
897 ret = PTR_ERR(sdhci_am654->base); in sdhci_am654_probe()
905 ret = mmc_of_parse(host->mmc); in sdhci_am654_probe()
911 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; in sdhci_am654_probe()
918 ret = clk_prepare_enable(pltfm_host->clk); in sdhci_am654_probe()
934 clk_disable_unprepare(pltfm_host->clk); in sdhci_am654_probe()
948 struct device *dev = &pdev->dev; in sdhci_am654_remove()
956 clk_disable_unprepare(pltfm_host->clk); in sdhci_am654_remove()
971 if (sdhci_am654->flags & DLL_CALIB) { in sdhci_am654_restore()
972 regmap_read(sdhci_am654->base, PHY_STAT1, &val); in sdhci_am654_restore()
975 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, in sdhci_am654_restore()
977 ret = regmap_read_poll_timeout(sdhci_am654->base, in sdhci_am654_restore()
987 if (sdhci_am654->flags & IOMUX_PRESENT) in sdhci_am654_restore()
988 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, in sdhci_am654_restore()
992 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) in sdhci_am654_restore()
995 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, in sdhci_am654_restore()
998 regmap_read(sdhci_am654->base, CTL_CFG_3, &val); in sdhci_am654_restore()
1001 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, in sdhci_am654_restore()
1013 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_am654_runtime_suspend()
1014 mmc_retune_needed(host->mmc); in sdhci_am654_runtime_suspend()
1016 ret = cqhci_suspend(host->mmc); in sdhci_am654_runtime_suspend()
1025 clk_disable_unprepare(pltfm_host->clk); in sdhci_am654_runtime_suspend()
1036 ret = clk_prepare_enable(pltfm_host->clk); in sdhci_am654_runtime_resume()
1048 ret = cqhci_resume(host->mmc); in sdhci_am654_runtime_resume()
1065 .name = "sdhci-am654",