Lines Matching +full:tegra186 +full:- +full:mc
1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
20 #include <linux/mmc/slot-gpio.h>
32 #include "sdhci-cqhci.h"
33 #include "sdhci-pltfm.h"
192 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
194 if (unlikely((soc_data->nvquirks & NVQUIRK_FORCE_SDHCI_SPEC_200) &&
200 return readw(host->ioaddr + reg);
213 pltfm_host->xfer_mode_shadow = val;
216 writel((val << 16) | pltfm_host->xfer_mode_shadow,
217 host->ioaddr + SDHCI_TRANSFER_MODE);
221 writew(val, host->ioaddr + reg);
228 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
237 writel(val, host->ioaddr + reg);
239 if (unlikely((soc_data->nvquirks & NVQUIRK_ENABLE_BLOCK_GAP_DET) &&
242 u8 gap_ctrl = readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
247 writeb(gap_ctrl, host->ioaddr + SDHCI_BLOCK_GAP_CONTROL);
283 writew(val, host->ioaddr + reg);
295 * Write-enable shall be assumed if GPIO is missing in a board's
296 * device-tree because SDHCI's WRITE_PROTECT bit doesn't work on
299 return mmc_gpio_get_ro(host->mmc);
316 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
319 if (IS_ERR(host->mmc->supply.vqmmc))
322 has_1v8 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
325 has_3v3 = regulator_is_supported_voltage(host->mmc->supply.vqmmc,
329 return tegra_host->pad_control_available;
339 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
349 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP)
357 if (soc_data->nvquirks & NVQUIRK_DIS_CARD_CLK_CONFIG_TAP &&
369 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
377 tegra_sdhci_set_tap(host, tegra_host->default_tap);
392 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDHCI_SPEC_300)
395 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
397 if (soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
399 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR104)
401 if (soc_data->nvquirks & NVQUIRK_ENABLE_SDR50)
405 clk_ctrl |= tegra_host->default_trim << SDHCI_CLOCK_CTRL_TRIM_SHIFT;
410 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB) {
416 tegra_host->pad_calib_required = true;
419 tegra_host->ddr_signaling = false;
460 &tegra_host->autocal_offsets;
469 if (tegra_host->pinctrl_state_1v8_drv) {
471 tegra_host->pinctrl_state_1v8_drv;
473 drvup = offsets->pull_up_1v8_timeout;
474 drvdn = offsets->pull_down_1v8_timeout;
477 if (tegra_host->pinctrl_state_3v3_drv) {
479 tegra_host->pinctrl_state_3v3_drv;
481 drvup = offsets->pull_up_3v3_timeout;
482 drvdn = offsets->pull_down_3v3_timeout;
487 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
490 dev_err(mmc_dev(host->mmc),
503 if (!tegra_host->pad_control_available)
507 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
508 tegra_host->pinctrl_state_1v8);
510 dev_err(mmc_dev(host->mmc),
513 ret = pinctrl_select_state(tegra_host->pinctrl_sdmmc,
514 tegra_host->pinctrl_state_3v3);
516 dev_err(mmc_dev(host->mmc),
529 tegra_host->autocal_offsets;
530 struct mmc_ios *ios = &host->mmc->ios;
536 switch (ios->timing) {
544 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
550 /* Set initial offset before auto-calibration */
563 ret = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_AUTO_CAL_STATUS,
572 dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n");
579 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, false);
581 dev_err(mmc_dev(host->mmc),
591 &tegra_host->autocal_offsets;
594 err = device_property_read_u32(mmc_dev(host->mmc),
595 "nvidia,pad-autocal-pull-up-offset-3v3",
596 &autocal->pull_up_3v3);
598 autocal->pull_up_3v3 = 0;
600 err = device_property_read_u32(mmc_dev(host->mmc),
601 "nvidia,pad-autocal-pull-down-offset-3v3",
602 &autocal->pull_down_3v3);
604 autocal->pull_down_3v3 = 0;
606 err = device_property_read_u32(mmc_dev(host->mmc),
607 "nvidia,pad-autocal-pull-up-offset-1v8",
608 &autocal->pull_up_1v8);
610 autocal->pull_up_1v8 = 0;
612 err = device_property_read_u32(mmc_dev(host->mmc),
613 "nvidia,pad-autocal-pull-down-offset-1v8",
614 &autocal->pull_down_1v8);
616 autocal->pull_down_1v8 = 0;
618 err = device_property_read_u32(mmc_dev(host->mmc),
619 "nvidia,pad-autocal-pull-up-offset-sdr104",
620 &autocal->pull_up_sdr104);
622 autocal->pull_up_sdr104 = autocal->pull_up_1v8;
624 err = device_property_read_u32(mmc_dev(host->mmc),
625 "nvidia,pad-autocal-pull-down-offset-sdr104",
626 &autocal->pull_down_sdr104);
628 autocal->pull_down_sdr104 = autocal->pull_down_1v8;
630 err = device_property_read_u32(mmc_dev(host->mmc),
631 "nvidia,pad-autocal-pull-up-offset-hs400",
632 &autocal->pull_up_hs400);
634 autocal->pull_up_hs400 = autocal->pull_up_1v8;
636 err = device_property_read_u32(mmc_dev(host->mmc),
637 "nvidia,pad-autocal-pull-down-offset-hs400",
638 &autocal->pull_down_hs400);
640 autocal->pull_down_hs400 = autocal->pull_down_1v8;
643 * Different fail-safe drive strength values based on the signaling
648 if (!(tegra_host->soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL))
651 err = device_property_read_u32(mmc_dev(host->mmc),
652 "nvidia,pad-autocal-pull-up-offset-3v3-timeout",
653 &autocal->pull_up_3v3_timeout);
655 if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
656 (tegra_host->pinctrl_state_3v3_drv == NULL))
657 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
658 mmc_hostname(host->mmc));
659 autocal->pull_up_3v3_timeout = 0;
662 err = device_property_read_u32(mmc_dev(host->mmc),
663 "nvidia,pad-autocal-pull-down-offset-3v3-timeout",
664 &autocal->pull_down_3v3_timeout);
666 if (!IS_ERR(tegra_host->pinctrl_state_3v3) &&
667 (tegra_host->pinctrl_state_3v3_drv == NULL))
668 pr_warn("%s: Missing autocal timeout 3v3-pad drvs\n",
669 mmc_hostname(host->mmc));
670 autocal->pull_down_3v3_timeout = 0;
673 err = device_property_read_u32(mmc_dev(host->mmc),
674 "nvidia,pad-autocal-pull-up-offset-1v8-timeout",
675 &autocal->pull_up_1v8_timeout);
677 if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
678 (tegra_host->pinctrl_state_1v8_drv == NULL))
679 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
680 mmc_hostname(host->mmc));
681 autocal->pull_up_1v8_timeout = 0;
684 err = device_property_read_u32(mmc_dev(host->mmc),
685 "nvidia,pad-autocal-pull-down-offset-1v8-timeout",
686 &autocal->pull_down_1v8_timeout);
688 if (!IS_ERR(tegra_host->pinctrl_state_1v8) &&
689 (tegra_host->pinctrl_state_1v8_drv == NULL))
690 pr_warn("%s: Missing autocal timeout 1v8-pad drvs\n",
691 mmc_hostname(host->mmc));
692 autocal->pull_down_1v8_timeout = 0;
701 ktime_t since_calib = ktime_sub(ktime_get(), tegra_host->last_calib);
706 tegra_host->last_calib = ktime_get();
718 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-tap",
719 &tegra_host->default_tap);
721 tegra_host->default_tap = 0;
723 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,default-trim",
724 &tegra_host->default_trim);
726 tegra_host->default_trim = 0;
728 err = device_property_read_u32(mmc_dev(host->mmc), "nvidia,dqs-trim",
729 &tegra_host->dqs_trim);
731 tegra_host->dqs_trim = 0x11;
739 if (device_property_read_bool(mmc_dev(host->mmc), "supports-cqe"))
740 tegra_host->enable_hwcq = true;
742 tegra_host->enable_hwcq = false;
752 struct device *dev = mmc_dev(host->mmc);
763 * sdhci_calc_clk(). The divider is calculated from host->max_clk and
766 * By setting the host->max_clk to clock * 2 the divider calculation
771 host_clk = tegra_host->ddr_signaling ? clock * 2 : clock;
778 tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk);
779 if (tegra_host->ddr_signaling)
780 host->max_clk = host_clk;
782 host->max_clk = clk_get_rate(pltfm_host->clk);
786 if (tegra_host->pad_calib_required) {
788 tegra_host->pad_calib_required = false;
800 if (ios->enhanced_strobe) {
822 return clk_round_rate(pltfm_host->clk, UINT_MAX);
845 err = readl_poll_timeout(host->ioaddr + SDHCI_TEGRA_VENDOR_DLLCAL_STA,
849 dev_err(mmc_dev(host->mmc),
870 u8 total_tuning_words = host->tuning_loop_count / TUNING_WORD_BIT_SIZE;
873 * Read auto-tuned results and extract good valid passing window by
874 * filtering out un-wanted bubble/partial/merged windows.
903 end_pass_tap = tap - 1;
907 window = end_pass_tap - start_pass_tap;
915 tegra_host->tuned_tap_delay = tap;
928 edge1 = first_fail_tap + (first_pass_tap - first_fail_tap) / 2;
929 if (edge1 - 1 > fixed_tap)
930 tegra_host->tuned_tap_delay = edge1 - fixed_tap;
932 tegra_host->tuned_tap_delay = edge1 + fixed_tap;
940 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
949 tegra_host->tuned_tap_delay = (val & SDHCI_CLOCK_CTRL_TAP_MASK) >>
951 if (soc_data->min_tap_delay && soc_data->max_tap_delay) {
952 min_tap_dly = soc_data->min_tap_delay;
953 max_tap_dly = soc_data->max_tap_delay;
954 clk_rate_mhz = tegra_host->curr_clk_rate / USEC_PER_SEC;
975 window_width = end_tap - start_tap;
976 num_iter = host->tuning_loop_count;
982 if (start_tap == 0 || (end_tap == (num_iter - 1)) ||
983 (end_tap == num_iter - 2) || window_width >= thdupper) {
985 mmc_hostname(host->mmc));
991 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
1000 if (!err && !host->tuning_err)
1017 tegra_host->ddr_signaling = false;
1033 tegra_host->ddr_signaling = true;
1051 host->tuning_loop_count = (iter == TRIES_128) ? 128 : 256;
1057 if (tegra_host->tuned_tap_delay && !set_default_tap)
1058 tegra_sdhci_set_tap(host, tegra_host->tuned_tap_delay);
1060 tegra_sdhci_set_tap(host, tegra_host->default_tap);
1063 tegra_sdhci_set_dqs_trim(host, tegra_host->dqs_trim);
1081 if (!mmc_send_tuning(host->mmc, opcode, NULL))
1090 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1091 max--;
1098 tegra_sdhci_set_tap(host, min + ((max - min) * 3 / 4));
1100 return mmc_send_tuning(host->mmc, opcode, NULL);
1111 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1112 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
1116 } else if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
1120 ret = tegra_sdhci_set_padctrl(host, ios->signal_voltage, true);
1123 if (tegra_host->pad_calib_required)
1132 tegra_host->pinctrl_sdmmc = devm_pinctrl_get(dev);
1133 if (IS_ERR(tegra_host->pinctrl_sdmmc)) {
1135 PTR_ERR(tegra_host->pinctrl_sdmmc));
1136 return -1;
1139 tegra_host->pinctrl_state_1v8_drv = pinctrl_lookup_state(
1140 tegra_host->pinctrl_sdmmc, "sdmmc-1v8-drv");
1141 if (IS_ERR(tegra_host->pinctrl_state_1v8_drv)) {
1142 if (PTR_ERR(tegra_host->pinctrl_state_1v8_drv) == -ENODEV)
1143 tegra_host->pinctrl_state_1v8_drv = NULL;
1146 tegra_host->pinctrl_state_3v3_drv = pinctrl_lookup_state(
1147 tegra_host->pinctrl_sdmmc, "sdmmc-3v3-drv");
1148 if (IS_ERR(tegra_host->pinctrl_state_3v3_drv)) {
1149 if (PTR_ERR(tegra_host->pinctrl_state_3v3_drv) == -ENODEV)
1150 tegra_host->pinctrl_state_3v3_drv = NULL;
1153 tegra_host->pinctrl_state_3v3 =
1154 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-3v3");
1155 if (IS_ERR(tegra_host->pinctrl_state_3v3)) {
1157 PTR_ERR(tegra_host->pinctrl_state_3v3));
1158 return -1;
1161 tegra_host->pinctrl_state_1v8 =
1162 pinctrl_lookup_state(tegra_host->pinctrl_sdmmc, "sdmmc-1v8");
1163 if (IS_ERR(tegra_host->pinctrl_state_1v8)) {
1165 PTR_ERR(tegra_host->pinctrl_state_1v8));
1166 return -1;
1169 tegra_host->pad_control_available = true;
1178 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1180 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1181 tegra_host->pad_calib_required = true;
1186 struct mmc_host *mmc = cq_host->mmc;
1195 * to be re-configured.
1204 writel(val, cq_host->mmio + reg);
1217 writel(val, cq_host->mmio + reg);
1219 writel(val, cq_host->mmio + reg);
1228 const struct sdhci_tegra_soc_data *soc_data = tegra_host->soc_data;
1230 if (soc_data->nvquirks & NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING &&
1231 mrq->cmd->flags & MMC_RSP_R1B)
1237 struct cqhci_host *cq_host = mmc->cqe_private;
1247 if (!cq_host->activated) {
1283 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1307 if (cmd && cmd->busy_timeout >= 11 * MSEC_PER_SEC)
1318 struct cqhci_host *cq_host = mmc->cqe_private;
1328 struct cqhci_host *cq_host = mmc->cqe_private;
1352 const struct sdhci_tegra_soc_data *soc = tegra->soc_data;
1353 struct device *dev = mmc_dev(host->mmc);
1355 if (soc->dma_mask)
1356 return dma_set_mask_and_coherent(dev, soc->dma_mask);
1402 * Auto-CMD23 leads to "Got command interrupt 0x00010000 even
1576 { .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 },
1577 { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 },
1578 { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 },
1579 { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 },
1580 { .compatible = "nvidia,tegra124-sdhci", .data = &soc_data_tegra124 },
1581 { .compatible = "nvidia,tegra114-sdhci", .data = &soc_data_tegra114 },
1582 { .compatible = "nvidia,tegra30-sdhci", .data = &soc_data_tegra30 },
1583 { .compatible = "nvidia,tegra20-sdhci", .data = &soc_data_tegra20 },
1596 if (!tegra_host->enable_hwcq)
1605 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1607 cq_host = devm_kzalloc(mmc_dev(host->mmc),
1610 ret = -ENOMEM;
1614 cq_host->mmio = host->ioaddr + SDHCI_TEGRA_CQE_BASE_ADDR;
1615 cq_host->ops = &sdhci_tegra_cqhci_ops;
1617 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1619 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1621 ret = cqhci_init(cq_host, host->mmc, dma64);
1636 /* Program MC streamID for DMA transfers */
1642 if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) {
1643 tegra_sdhci_writel(host, FIELD_PREP(GENMASK(15, 8), tegra_host->stream_id) |
1644 FIELD_PREP(GENMASK(7, 0), tegra_host->stream_id),
1658 soc_data = of_device_get_match_data(&pdev->dev);
1660 return -EINVAL;
1662 host = sdhci_pltfm_init(pdev, soc_data->pdata, sizeof(*tegra_host));
1668 tegra_host->ddr_signaling = false;
1669 tegra_host->pad_calib_required = false;
1670 tegra_host->pad_control_available = false;
1671 tegra_host->soc_data = soc_data;
1673 if (soc_data->nvquirks & NVQUIRK_HAS_ANDROID_GPT_SECTOR)
1674 host->mmc->caps2 |= MMC_CAP2_ALT_GPT_TEGRA;
1676 if (soc_data->nvquirks & NVQUIRK_NEEDS_PAD_CONTROL) {
1677 rc = tegra_sdhci_init_pinctrl_info(&pdev->dev, tegra_host);
1679 host->mmc_host_ops.start_signal_voltage_switch =
1684 if (soc_data->nvquirks & NVQUIRK_HAS_PADCALIB)
1685 host->mmc_host_ops.request = tegra_sdhci_request;
1687 host->mmc_host_ops.hs400_enhanced_strobe =
1690 if (!host->ops->platform_execute_tuning)
1691 host->mmc_host_ops.execute_tuning =
1694 rc = mmc_of_parse(host->mmc);
1698 if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50)
1699 host->mmc->caps |= MMC_CAP_1_8V_DDR;
1702 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;
1705 host->mmc->caps |= MMC_CAP_CD_WAKE;
1709 if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID &&
1710 !tegra_dev_iommu_get_stream_id(&pdev->dev, &tegra_host->stream_id)) {
1711 dev_warn(mmc_dev(host->mmc), "missing IOMMU stream ID\n");
1712 tegra_host->stream_id = 0x7f;
1715 tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power",
1717 if (IS_ERR(tegra_host->power_gpio)) {
1718 rc = PTR_ERR(tegra_host->power_gpio);
1737 if (soc_data->nvquirks & NVQUIRK_HAS_TMCLK) {
1738 clk = devm_clk_get(&pdev->dev, "tmclk");
1741 if (rc == -EPROBE_DEFER)
1744 dev_warn(&pdev->dev, "failed to get tmclk: %d\n", rc);
1751 dev_err(&pdev->dev,
1756 tegra_host->tmclk = clk;
1759 clk = devm_clk_get(mmc_dev(host->mmc), NULL);
1761 rc = dev_err_probe(&pdev->dev, PTR_ERR(clk),
1765 pltfm_host->clk = clk;
1767 tegra_host->rst = devm_reset_control_get_exclusive(&pdev->dev,
1769 if (IS_ERR(tegra_host->rst)) {
1770 rc = PTR_ERR(tegra_host->rst);
1771 dev_err(&pdev->dev, "failed to get reset control: %d\n", rc);
1775 rc = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
1779 pm_runtime_enable(&pdev->dev);
1780 rc = pm_runtime_resume_and_get(&pdev->dev);
1784 rc = reset_control_assert(tegra_host->rst);
1790 rc = reset_control_deassert(tegra_host->rst);
1805 reset_control_assert(tegra_host->rst);
1807 pm_runtime_put_sync_suspend(&pdev->dev);
1809 pm_runtime_disable(&pdev->dev);
1812 clk_disable_unprepare(tegra_host->tmclk);
1827 reset_control_assert(tegra_host->rst);
1830 pm_runtime_put_sync_suspend(&pdev->dev);
1831 pm_runtime_force_suspend(&pdev->dev);
1833 clk_disable_unprepare(tegra_host->tmclk);
1842 clk_disable_unprepare(pltfm_host->clk);
1852 return clk_prepare_enable(pltfm_host->clk);
1861 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1862 ret = cqhci_suspend(host->mmc);
1869 cqhci_resume(host->mmc);
1876 cqhci_resume(host->mmc);
1880 return mmc_gpio_set_cd_wake(host->mmc, true);
1888 ret = mmc_gpio_set_cd_wake(host->mmc, false);
1902 if (host->mmc->caps2 & MMC_CAP2_CQE) {
1903 ret = cqhci_resume(host->mmc);
1926 .name = "sdhci-tegra",