Lines Matching refs:value
75 static void sparx5_set_cacheable(struct sdhci_host *host, u32 value) in sparx5_set_cacheable() argument
80 pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value); in sparx5_set_cacheable()
84 CPU_REGS_PROC_CTRL, ACP_CACHE_MASK, value); in sparx5_set_cacheable()
87 static void sparx5_set_delay(struct sdhci_host *host, u8 value) in sparx5_set_delay() argument
92 pr_debug("%s: Set DLY_CC = %u\n", mmc_hostname(host->mmc), value); in sparx5_set_delay()
98 (value << MSHC_DLY_CC_SHIFT)); in sparx5_set_delay()
104 u8 value; in sdhci_sparx5_set_emmc() local
106 value = sdhci_readb(host, MSHC2_EMMC_CTRL); in sdhci_sparx5_set_emmc()
107 if (!(value & MSHC2_EMMC_CTRL_IS_EMMC)) { in sdhci_sparx5_set_emmc()
108 value |= MSHC2_EMMC_CTRL_IS_EMMC; in sdhci_sparx5_set_emmc()
110 mmc_hostname(host->mmc), value); in sdhci_sparx5_set_emmc()
111 sdhci_writeb(host, value, MSHC2_EMMC_CTRL); in sdhci_sparx5_set_emmc()
118 u8 value; in sdhci_sparx5_reset_emmc() local
121 value = sdhci_readb(host, MSHC2_EMMC_CTRL) & in sdhci_sparx5_reset_emmc()
123 sdhci_writeb(host, value, MSHC2_EMMC_CTRL); in sdhci_sparx5_reset_emmc()
126 sdhci_writeb(host, value | MSHC2_EMMC_CTRL_EMMC_RST_N, in sdhci_sparx5_reset_emmc()
166 u32 value; in sdhci_sparx5_probe() local
194 if (!of_property_read_u32(np, "microchip,clock-delay", &value) && in sdhci_sparx5_probe()
195 (value > 0 && value <= MSHC_DLY_CC_MAX)) in sdhci_sparx5_probe()
196 sdhci_sparx5->delay_clock = value; in sdhci_sparx5_probe()