Lines Matching +full:mt6779 +full:- +full:pinctrl
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
11 #include <linux/dma-mapping.h>
17 #include <linux/pinctrl/consumer.h>
34 #include <linux/mmc/slot-gpio.h>
41 /*--------------------------------------------------------------------------*/
43 /*--------------------------------------------------------------------------*/
50 /*--------------------------------------------------------------------------*/
52 /*--------------------------------------------------------------------------*/
89 /*--------------------------------------------------------------------------*/
91 /*--------------------------------------------------------------------------*/
96 /*--------------------------------------------------------------------------*/
98 /*--------------------------------------------------------------------------*/
329 /*--------------------------------------------------------------------------*/
331 /*--------------------------------------------------------------------------*/
439 struct pinctrl *pinctrl; member
468 bool internal_cd; /* Use internal card-detect logic */
619 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
620 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
621 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
622 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
623 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
624 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
625 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
626 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
627 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
628 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
629 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
656 tv |= ((val) << (ffs((unsigned int)field) - 1)); in sdr_set_field()
664 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); in sdr_get_field()
671 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); in msdc_reset_hw()
672 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); in msdc_reset_hw()
674 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); in msdc_reset_hw()
675 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val, in msdc_reset_hw()
678 val = readl(host->base + MSDC_INT); in msdc_reset_hw()
679 writel(val, host->base + MSDC_INT); in msdc_reset_hw()
699 return 0xff - (u8) sum; in msdc_dma_calcs()
712 sg = data->sg; in msdc_dma_setup()
714 gpd = dma->gpd; in msdc_dma_setup()
715 bd = dma->bd; in msdc_dma_setup()
718 gpd->gpd_info |= GPDMA_DESC_HWO; in msdc_dma_setup()
719 gpd->gpd_info |= GPDMA_DESC_BDP; in msdc_dma_setup()
721 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; in msdc_dma_setup()
722 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; in msdc_dma_setup()
725 for_each_sg(data->sg, sg, data->sg_count, j) { in msdc_dma_setup()
733 if (host->dev_comp->support_64g) { in msdc_dma_setup()
739 if (host->dev_comp->support_64g) { in msdc_dma_setup()
747 if (j == data->sg_count - 1) /* the last bd */ in msdc_dma_setup()
757 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); in msdc_dma_setup()
758 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
761 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
762 if (host->dev_comp->support_64g) in msdc_dma_setup()
763 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, in msdc_dma_setup()
764 upper_32_bits(dma->gpd_addr) & 0xf); in msdc_dma_setup()
765 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); in msdc_dma_setup()
770 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { in msdc_prepare_data()
771 data->host_cookie |= MSDC_PREPARE_FLAG; in msdc_prepare_data()
772 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, in msdc_prepare_data()
779 if (data->host_cookie & MSDC_ASYNC_FLAG) in msdc_unprepare_data()
782 if (data->host_cookie & MSDC_PREPARE_FLAG) { in msdc_unprepare_data()
783 dma_unmap_sg(host->dev, data->sg, data->sg_len, in msdc_unprepare_data()
785 data->host_cookie &= ~MSDC_PREPARE_FLAG; in msdc_unprepare_data()
795 if (mmc->actual_clock == 0) { in msdc_timeout_cal()
799 do_div(clk_ns, mmc->actual_clock); in msdc_timeout_cal()
800 timeout = ns + clk_ns - 1; in msdc_timeout_cal()
805 if (host->dev_comp->clk_div_bits == 8) in msdc_timeout_cal()
806 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
809 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
813 timeout = timeout > 1 ? timeout - 1 : 0; in msdc_timeout_cal()
823 host->timeout_ns = ns; in msdc_set_timeout()
824 host->timeout_clks = clks; in msdc_set_timeout()
827 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, in msdc_set_timeout()
836 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, in msdc_set_busy_timeout()
842 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_gate_clock()
843 clk_disable_unprepare(host->crypto_clk); in msdc_gate_clock()
844 clk_disable_unprepare(host->src_clk_cg); in msdc_gate_clock()
845 clk_disable_unprepare(host->src_clk); in msdc_gate_clock()
846 clk_disable_unprepare(host->bus_clk); in msdc_gate_clock()
847 clk_disable_unprepare(host->h_clk); in msdc_gate_clock()
855 clk_prepare_enable(host->h_clk); in msdc_ungate_clock()
856 clk_prepare_enable(host->bus_clk); in msdc_ungate_clock()
857 clk_prepare_enable(host->src_clk); in msdc_ungate_clock()
858 clk_prepare_enable(host->src_clk_cg); in msdc_ungate_clock()
859 clk_prepare_enable(host->crypto_clk); in msdc_ungate_clock()
860 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_ungate_clock()
862 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); in msdc_ungate_clock()
866 return readl_poll_timeout(host->base + MSDC_CFG, val, in msdc_ungate_clock()
877 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_mclk()
881 dev_dbg(host->dev, "set mclk to 0\n"); in msdc_set_mclk()
882 host->mclk = 0; in msdc_set_mclk()
883 mmc->actual_clock = 0; in msdc_set_mclk()
884 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
888 flags = readl(host->base + MSDC_INTEN); in msdc_set_mclk()
889 sdr_clr_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
890 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
891 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); in msdc_set_mclk()
893 sdr_clr_bits(host->base + MSDC_CFG, in msdc_set_mclk()
903 if (hz >= (host->src_clk_freq >> 2)) { in msdc_set_mclk()
905 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
907 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
908 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
913 hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
914 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
915 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
918 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
920 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
923 } else if (hz >= host->src_clk_freq) { in msdc_set_mclk()
926 sclk = host->src_clk_freq; in msdc_set_mclk()
929 if (hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
931 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ in msdc_set_mclk()
933 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
934 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
937 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
939 clk_disable_unprepare(host->src_clk_cg); in msdc_set_mclk()
940 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
941 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
945 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
949 clk_prepare_enable(host->src_clk_cg); in msdc_set_mclk()
950 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); in msdc_set_mclk()
951 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
952 mmc->actual_clock = sclk; in msdc_set_mclk()
953 host->mclk = hz; in msdc_set_mclk()
954 host->timing = timing; in msdc_set_mclk()
956 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); in msdc_set_mclk()
957 sdr_set_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
963 if (mmc->actual_clock <= 52000000) { in msdc_set_mclk()
964 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
965 if (host->top_base) { in msdc_set_mclk()
966 writel(host->def_tune_para.emmc_top_control, in msdc_set_mclk()
967 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
968 writel(host->def_tune_para.emmc_top_cmd, in msdc_set_mclk()
969 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
971 writel(host->def_tune_para.pad_tune, in msdc_set_mclk()
972 host->base + tune_reg); in msdc_set_mclk()
975 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
976 writel(host->saved_tune_para.pad_cmd_tune, in msdc_set_mclk()
977 host->base + PAD_CMD_TUNE); in msdc_set_mclk()
978 if (host->top_base) { in msdc_set_mclk()
979 writel(host->saved_tune_para.emmc_top_control, in msdc_set_mclk()
980 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
981 writel(host->saved_tune_para.emmc_top_cmd, in msdc_set_mclk()
982 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
984 writel(host->saved_tune_para.pad_tune, in msdc_set_mclk()
985 host->base + tune_reg); in msdc_set_mclk()
990 host->dev_comp->hs400_tune) in msdc_set_mclk()
991 sdr_set_field(host->base + tune_reg, in msdc_set_mclk()
993 host->hs400_cmd_int_delay); in msdc_set_mclk()
994 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, in msdc_set_mclk()
1034 u32 opcode = cmd->opcode; in msdc_cmd_prepare_raw_cmd()
1038 host->cmd_rsp = resp; in msdc_cmd_prepare_raw_cmd()
1040 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || in msdc_cmd_prepare_raw_cmd()
1052 if (cmd->data) { in msdc_cmd_prepare_raw_cmd()
1053 struct mmc_data *data = cmd->data; in msdc_cmd_prepare_raw_cmd()
1056 if (mmc_card_mmc(mmc->card) && mrq->sbc && in msdc_cmd_prepare_raw_cmd()
1057 !(mrq->sbc->arg & 0xFFFF0000)) in msdc_cmd_prepare_raw_cmd()
1061 rawcmd |= ((data->blksz & 0xFFF) << 16); in msdc_cmd_prepare_raw_cmd()
1062 if (data->flags & MMC_DATA_WRITE) in msdc_cmd_prepare_raw_cmd()
1064 if (data->blocks > 1) in msdc_cmd_prepare_raw_cmd()
1069 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); in msdc_cmd_prepare_raw_cmd()
1071 if (host->timeout_ns != data->timeout_ns || in msdc_cmd_prepare_raw_cmd()
1072 host->timeout_clks != data->timeout_clks) in msdc_cmd_prepare_raw_cmd()
1073 msdc_set_timeout(host, data->timeout_ns, in msdc_cmd_prepare_raw_cmd()
1074 data->timeout_clks); in msdc_cmd_prepare_raw_cmd()
1076 writel(data->blocks, host->base + SDC_BLK_NUM); in msdc_cmd_prepare_raw_cmd()
1086 WARN_ON(host->data); in msdc_start_data()
1087 host->data = data; in msdc_start_data()
1088 read = data->flags & MMC_DATA_READ; in msdc_start_data()
1090 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_data()
1091 msdc_dma_setup(host, &host->dma, data); in msdc_start_data()
1092 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_start_data()
1093 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); in msdc_start_data()
1094 dev_dbg(host->dev, "DMA start\n"); in msdc_start_data()
1095 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", in msdc_start_data()
1096 __func__, cmd->opcode, data->blocks, read); in msdc_start_data()
1102 u32 *rsp = cmd->resp; in msdc_auto_cmd_done()
1104 rsp[0] = readl(host->base + SDC_ACMD_RESP); in msdc_auto_cmd_done()
1107 cmd->error = 0; in msdc_auto_cmd_done()
1111 cmd->error = -EILSEQ; in msdc_auto_cmd_done()
1112 host->error |= REQ_STOP_EIO; in msdc_auto_cmd_done()
1114 cmd->error = -ETIMEDOUT; in msdc_auto_cmd_done()
1115 host->error |= REQ_STOP_TMO; in msdc_auto_cmd_done()
1117 dev_err(host->dev, in msdc_auto_cmd_done()
1119 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); in msdc_auto_cmd_done()
1121 return cmd->error; in msdc_auto_cmd_done()
1125 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1136 if (mmc->caps & MMC_CAP_SDIO_IRQ) { in msdc_recheck_sdio_irq()
1137 reg_inten = readl(host->base + MSDC_INTEN); in msdc_recheck_sdio_irq()
1139 reg_int = readl(host->base + MSDC_INT); in msdc_recheck_sdio_irq()
1140 reg_ps = readl(host->base + MSDC_PS); in msdc_recheck_sdio_irq()
1152 if (host->error) in msdc_track_cmd_data()
1153 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", in msdc_track_cmd_data()
1154 __func__, cmd->opcode, cmd->arg, host->error); in msdc_track_cmd_data()
1165 cancel_delayed_work(&host->req_timeout); in msdc_request_done()
1167 spin_lock_irqsave(&host->lock, flags); in msdc_request_done()
1168 host->mrq = NULL; in msdc_request_done()
1169 spin_unlock_irqrestore(&host->lock, flags); in msdc_request_done()
1171 msdc_track_cmd_data(host, mrq->cmd); in msdc_request_done()
1172 if (mrq->data) in msdc_request_done()
1173 msdc_unprepare_data(host, mrq->data); in msdc_request_done()
1174 if (host->error) in msdc_request_done()
1177 if (host->dev_comp->recheck_sdio_irq) in msdc_request_done()
1190 if (mrq->sbc && cmd == mrq->cmd && in msdc_cmd_done()
1193 msdc_auto_cmd_done(host, events, mrq->sbc); in msdc_cmd_done()
1195 sbc_error = mrq->sbc && mrq->sbc->error; in msdc_cmd_done()
1202 spin_lock_irqsave(&host->lock, flags); in msdc_cmd_done()
1203 done = !host->cmd; in msdc_cmd_done()
1204 host->cmd = NULL; in msdc_cmd_done()
1205 spin_unlock_irqrestore(&host->lock, flags); in msdc_cmd_done()
1209 rsp = cmd->resp; in msdc_cmd_done()
1211 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_cmd_done()
1213 if (cmd->flags & MMC_RSP_PRESENT) { in msdc_cmd_done()
1214 if (cmd->flags & MMC_RSP_136) { in msdc_cmd_done()
1215 rsp[0] = readl(host->base + SDC_RESP3); in msdc_cmd_done()
1216 rsp[1] = readl(host->base + SDC_RESP2); in msdc_cmd_done()
1217 rsp[2] = readl(host->base + SDC_RESP1); in msdc_cmd_done()
1218 rsp[3] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1220 rsp[0] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1225 if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) || in msdc_cmd_done()
1226 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) in msdc_cmd_done()
1234 cmd->error = -EILSEQ; in msdc_cmd_done()
1235 host->error |= REQ_CMD_EIO; in msdc_cmd_done()
1237 cmd->error = -ETIMEDOUT; in msdc_cmd_done()
1238 host->error |= REQ_CMD_TMO; in msdc_cmd_done()
1241 if (cmd->error) in msdc_cmd_done()
1242 dev_dbg(host->dev, in msdc_cmd_done()
1244 __func__, cmd->opcode, cmd->arg, rsp[0], in msdc_cmd_done()
1245 cmd->error); in msdc_cmd_done()
1262 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1265 dev_err(host->dev, "CMD bus busy detected\n"); in msdc_cmd_is_ready()
1266 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1271 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { in msdc_cmd_is_ready()
1273 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1276 dev_err(host->dev, "Controller busy detected\n"); in msdc_cmd_is_ready()
1277 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1291 WARN_ON(host->cmd); in msdc_start_command()
1292 host->cmd = cmd; in msdc_start_command()
1294 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_command()
1298 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || in msdc_start_command()
1299 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { in msdc_start_command()
1300 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); in msdc_start_command()
1304 cmd->error = 0; in msdc_start_command()
1307 spin_lock_irqsave(&host->lock, flags); in msdc_start_command()
1308 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_start_command()
1309 spin_unlock_irqrestore(&host->lock, flags); in msdc_start_command()
1311 writel(cmd->arg, host->base + SDC_ARG); in msdc_start_command()
1312 writel(rawcmd, host->base + SDC_CMD); in msdc_start_command()
1318 if ((cmd->error && !host->hs400_tuning && in msdc_cmd_next()
1319 !(cmd->error == -EILSEQ && in msdc_cmd_next()
1320 mmc_op_tuning(cmd->opcode))) || in msdc_cmd_next()
1321 (mrq->sbc && mrq->sbc->error)) in msdc_cmd_next()
1323 else if (cmd == mrq->sbc) in msdc_cmd_next()
1324 msdc_start_command(host, mrq, mrq->cmd); in msdc_cmd_next()
1325 else if (!cmd->data) in msdc_cmd_next()
1328 msdc_start_data(host, cmd, cmd->data); in msdc_cmd_next()
1335 host->error = 0; in msdc_ops_request()
1336 WARN_ON(host->mrq); in msdc_ops_request()
1337 host->mrq = mrq; in msdc_ops_request()
1339 if (mrq->data) in msdc_ops_request()
1340 msdc_prepare_data(host, mrq->data); in msdc_ops_request()
1346 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || in msdc_ops_request()
1347 (mrq->sbc->arg & 0xFFFF0000))) in msdc_ops_request()
1348 msdc_start_command(host, mrq, mrq->sbc); in msdc_ops_request()
1350 msdc_start_command(host, mrq, mrq->cmd); in msdc_ops_request()
1356 struct mmc_data *data = mrq->data; in msdc_pre_req()
1362 data->host_cookie |= MSDC_ASYNC_FLAG; in msdc_pre_req()
1369 struct mmc_data *data = mrq->data; in msdc_post_req()
1374 if (data->host_cookie) { in msdc_post_req()
1375 data->host_cookie &= ~MSDC_ASYNC_FLAG; in msdc_post_req()
1382 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && in msdc_data_xfer_next()
1383 !mrq->sbc) in msdc_data_xfer_next()
1384 msdc_start_command(host, mrq, mrq->stop); in msdc_data_xfer_next()
1402 spin_lock_irqsave(&host->lock, flags); in msdc_data_xfer_done()
1403 done = !host->data; in msdc_data_xfer_done()
1405 host->data = NULL; in msdc_data_xfer_done()
1406 spin_unlock_irqrestore(&host->lock, flags); in msdc_data_xfer_done()
1410 stop = data->stop; in msdc_data_xfer_done()
1412 if (check_data || (stop && stop->error)) { in msdc_data_xfer_done()
1413 dev_dbg(host->dev, "DMA status: 0x%8X\n", in msdc_data_xfer_done()
1414 readl(host->base + MSDC_DMA_CFG)); in msdc_data_xfer_done()
1415 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, in msdc_data_xfer_done()
1418 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, in msdc_data_xfer_done()
1421 dev_dbg(host->dev, "DMA stop timed out\n"); in msdc_data_xfer_done()
1423 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, in msdc_data_xfer_done()
1426 dev_dbg(host->dev, "DMA inactive timed out\n"); in msdc_data_xfer_done()
1428 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_data_xfer_done()
1429 dev_dbg(host->dev, "DMA stop\n"); in msdc_data_xfer_done()
1431 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { in msdc_data_xfer_done()
1432 data->bytes_xfered = data->blocks * data->blksz; in msdc_data_xfer_done()
1434 dev_dbg(host->dev, "interrupt events: %x\n", events); in msdc_data_xfer_done()
1436 host->error |= REQ_DAT_ERR; in msdc_data_xfer_done()
1437 data->bytes_xfered = 0; in msdc_data_xfer_done()
1440 data->error = -ETIMEDOUT; in msdc_data_xfer_done()
1442 data->error = -EILSEQ; in msdc_data_xfer_done()
1444 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", in msdc_data_xfer_done()
1445 __func__, mrq->cmd->opcode, data->blocks); in msdc_data_xfer_done()
1446 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", in msdc_data_xfer_done()
1447 (int)data->error, data->bytes_xfered); in msdc_data_xfer_done()
1456 u32 val = readl(host->base + SDC_CFG); in msdc_set_buswidth()
1473 writel(val, host->base + SDC_CFG); in msdc_set_buswidth()
1474 dev_dbg(host->dev, "Bus Width = %d", width); in msdc_set_buswidth()
1482 if (!IS_ERR(mmc->supply.vqmmc)) { in msdc_ops_switch_volt()
1483 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && in msdc_ops_switch_volt()
1484 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { in msdc_ops_switch_volt()
1485 dev_err(host->dev, "Unsupported signal voltage!\n"); in msdc_ops_switch_volt()
1486 return -EINVAL; in msdc_ops_switch_volt()
1491 dev_dbg(host->dev, "Regulator set error %d (%d)\n", in msdc_ops_switch_volt()
1492 ret, ios->signal_voltage); in msdc_ops_switch_volt()
1496 /* Apply different pinctrl settings for different signal voltage */ in msdc_ops_switch_volt()
1497 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in msdc_ops_switch_volt()
1498 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_ops_switch_volt()
1500 pinctrl_select_state(host->pinctrl, host->pins_default); in msdc_ops_switch_volt()
1508 u32 status = readl(host->base + MSDC_PS); in msdc_card_busy()
1520 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); in msdc_request_timeout()
1521 if (host->mrq) { in msdc_request_timeout()
1522 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, in msdc_request_timeout()
1523 host->mrq, host->mrq->cmd->opcode); in msdc_request_timeout()
1524 if (host->cmd) { in msdc_request_timeout()
1525 dev_err(host->dev, "%s: aborting cmd=%d\n", in msdc_request_timeout()
1526 __func__, host->cmd->opcode); in msdc_request_timeout()
1527 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, in msdc_request_timeout()
1528 host->cmd); in msdc_request_timeout()
1529 } else if (host->data) { in msdc_request_timeout()
1530 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", in msdc_request_timeout()
1531 __func__, host->mrq->cmd->opcode, in msdc_request_timeout()
1532 host->data->blocks); in msdc_request_timeout()
1533 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, in msdc_request_timeout()
1534 host->data); in msdc_request_timeout()
1542 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1543 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1544 if (host->dev_comp->recheck_sdio_irq) in __msdc_enable_sdio_irq()
1547 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1548 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1558 spin_lock_irqsave(&host->lock, flags); in msdc_enable_sdio_irq()
1560 spin_unlock_irqrestore(&host->lock, flags); in msdc_enable_sdio_irq()
1562 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { in msdc_enable_sdio_irq()
1567 * Since the current pinstate is pins_uhs, to ensure pinctrl select take in msdc_enable_sdio_irq()
1570 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_enable_sdio_irq()
1571 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); in msdc_enable_sdio_irq()
1574 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); in msdc_enable_sdio_irq()
1575 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1576 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1578 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); in msdc_enable_sdio_irq()
1581 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_enable_sdio_irq()
1583 dev_pm_clear_wake_irq(host->dev); in msdc_enable_sdio_irq()
1587 /* Ensure host->pins_eint is NULL */ in msdc_enable_sdio_irq()
1588 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1589 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1591 pm_runtime_put_noidle(host->dev); in msdc_enable_sdio_irq()
1602 cmd_err = -EILSEQ; in msdc_cmdq_irq()
1603 dev_err(host->dev, "%s: CMD CRC ERR", __func__); in msdc_cmdq_irq()
1605 cmd_err = -ETIMEDOUT; in msdc_cmdq_irq()
1606 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1610 dat_err = -EILSEQ; in msdc_cmdq_irq()
1611 dev_err(host->dev, "%s: DATA CRC ERR", __func__); in msdc_cmdq_irq()
1613 dat_err = -ETIMEDOUT; in msdc_cmdq_irq()
1614 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1618 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", in msdc_cmdq_irq()
1636 spin_lock(&host->lock); in msdc_irq()
1637 events = readl(host->base + MSDC_INT); in msdc_irq()
1638 event_mask = readl(host->base + MSDC_INTEN); in msdc_irq()
1642 writel(events & event_mask, host->base + MSDC_INT); in msdc_irq()
1644 mrq = host->mrq; in msdc_irq()
1645 cmd = host->cmd; in msdc_irq()
1646 data = host->data; in msdc_irq()
1647 spin_unlock(&host->lock); in msdc_irq()
1653 if (host->internal_cd) in msdc_irq()
1661 if ((mmc->caps2 & MMC_CAP2_CQE) && in msdc_irq()
1665 writel(events, host->base + MSDC_INT); in msdc_irq()
1670 dev_err(host->dev, in msdc_irq()
1677 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); in msdc_irq()
1691 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_init_hw()
1694 if (host->reset) { in msdc_init_hw()
1695 reset_control_assert(host->reset); in msdc_init_hw()
1697 reset_control_deassert(host->reset); in msdc_init_hw()
1701 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); in msdc_init_hw()
1707 writel(0, host->base + MSDC_INTEN); in msdc_init_hw()
1708 val = readl(host->base + MSDC_INT); in msdc_init_hw()
1709 writel(val, host->base + MSDC_INT); in msdc_init_hw()
1712 if (host->internal_cd) { in msdc_init_hw()
1713 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, in msdc_init_hw()
1715 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1716 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1717 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1719 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1720 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1721 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1724 if (host->top_base) { in msdc_init_hw()
1725 writel(0, host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1726 writel(0, host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1728 writel(0, host->base + tune_reg); in msdc_init_hw()
1730 writel(0, host->base + MSDC_IOCON); in msdc_init_hw()
1731 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); in msdc_init_hw()
1732 writel(0x403c0046, host->base + MSDC_PATCH_BIT); in msdc_init_hw()
1733 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); in msdc_init_hw()
1734 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); in msdc_init_hw()
1735 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); in msdc_init_hw()
1737 if (host->dev_comp->stop_clk_fix) { in msdc_init_hw()
1738 sdr_set_field(host->base + MSDC_PATCH_BIT1, in msdc_init_hw()
1740 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1742 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1746 if (host->dev_comp->busy_check) in msdc_init_hw()
1747 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); in msdc_init_hw()
1749 if (host->dev_comp->async_fifo) { in msdc_init_hw()
1750 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1752 if (host->dev_comp->enhance_rx) { in msdc_init_hw()
1753 if (host->top_base) in msdc_init_hw()
1754 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1757 sdr_set_bits(host->base + SDC_ADV_CFG0, in msdc_init_hw()
1760 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1762 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1766 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1768 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1772 if (host->dev_comp->support_64g) in msdc_init_hw()
1773 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1775 if (host->dev_comp->data_tune) { in msdc_init_hw()
1776 if (host->top_base) { in msdc_init_hw()
1777 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1779 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1781 sdr_set_bits(host->top_base + EMMC_TOP_CMD, in msdc_init_hw()
1784 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1790 if (host->top_base) in msdc_init_hw()
1791 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1794 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1798 if (mmc->caps2 & MMC_CAP2_NO_SDIO) { in msdc_init_hw()
1799 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1800 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in msdc_init_hw()
1801 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1804 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1807 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in msdc_init_hw()
1808 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1812 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); in msdc_init_hw()
1814 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1815 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1816 if (host->top_base) { in msdc_init_hw()
1817 host->def_tune_para.emmc_top_control = in msdc_init_hw()
1818 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1819 host->def_tune_para.emmc_top_cmd = in msdc_init_hw()
1820 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1821 host->saved_tune_para.emmc_top_control = in msdc_init_hw()
1822 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1823 host->saved_tune_para.emmc_top_cmd = in msdc_init_hw()
1824 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1826 host->def_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1827 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1829 dev_dbg(host->dev, "init hardware done!"); in msdc_init_hw()
1836 if (host->internal_cd) { in msdc_deinit_hw()
1837 /* Disabled card-detect */ in msdc_deinit_hw()
1838 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_deinit_hw()
1839 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_deinit_hw()
1843 writel(0, host->base + MSDC_INTEN); in msdc_deinit_hw()
1845 val = readl(host->base + MSDC_INT); in msdc_deinit_hw()
1846 writel(val, host->base + MSDC_INT); in msdc_deinit_hw()
1852 struct mt_gpdma_desc *gpd = dma->gpd; in msdc_init_gpd_bd()
1853 struct mt_bdma_desc *bd = dma->bd; in msdc_init_gpd_bd()
1859 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); in msdc_init_gpd_bd()
1860 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ in msdc_init_gpd_bd()
1861 /* gpd->next is must set for desc DMA in msdc_init_gpd_bd()
1864 gpd->next = lower_32_bits(dma_addr); in msdc_init_gpd_bd()
1865 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1866 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; in msdc_init_gpd_bd()
1868 dma_addr = dma->bd_addr; in msdc_init_gpd_bd()
1869 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ in msdc_init_gpd_bd()
1870 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1871 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; in msdc_init_gpd_bd()
1874 for (i = 0; i < (MAX_BD_NUM - 1); i++) { in msdc_init_gpd_bd()
1875 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); in msdc_init_gpd_bd()
1877 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1887 msdc_set_buswidth(host, ios->bus_width); in msdc_ops_set_ios()
1890 switch (ios->power_mode) { in msdc_ops_set_ios()
1892 if (!IS_ERR(mmc->supply.vmmc)) { in msdc_ops_set_ios()
1894 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, in msdc_ops_set_ios()
1895 ios->vdd); in msdc_ops_set_ios()
1897 dev_err(host->dev, "Failed to set vmmc power!\n"); in msdc_ops_set_ios()
1903 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { in msdc_ops_set_ios()
1904 ret = regulator_enable(mmc->supply.vqmmc); in msdc_ops_set_ios()
1906 dev_err(host->dev, "Failed to set vqmmc power!\n"); in msdc_ops_set_ios()
1908 host->vqmmc_enabled = true; in msdc_ops_set_ios()
1912 if (!IS_ERR(mmc->supply.vmmc)) in msdc_ops_set_ios()
1913 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in msdc_ops_set_ios()
1915 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { in msdc_ops_set_ios()
1916 regulator_disable(mmc->supply.vqmmc); in msdc_ops_set_ios()
1917 host->vqmmc_enabled = false; in msdc_ops_set_ios()
1924 if (host->mclk != ios->clock || host->timing != ios->timing) in msdc_ops_set_ios()
1925 msdc_set_mclk(host, ios->timing, ios->clock); in msdc_ops_set_ios()
1938 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { in get_delay_len()
1942 return PAD_DELAY_MAX - start_bit; in get_delay_len()
1953 dev_err(host->dev, "phase error: [map:%x]\n", delay); in get_best_delay()
1974 dev_dbg(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", in get_best_delay()
1985 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_cmd_delay()
1987 if (host->top_base) in msdc_set_cmd_delay()
1988 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, in msdc_set_cmd_delay()
1991 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, in msdc_set_cmd_delay()
1997 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_data_delay()
1999 if (host->top_base) in msdc_set_data_delay()
2000 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2003 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, in msdc_set_data_delay()
2015 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_tune_response()
2019 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in msdc_tune_response()
2020 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in msdc_tune_response()
2021 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2023 host->hs200_cmd_int_delay); in msdc_tune_response()
2025 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2049 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2074 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2077 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2082 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) in msdc_tune_response()
2086 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2092 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); in msdc_tune_response()
2094 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, in msdc_tune_response()
2097 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in msdc_tune_response()
2098 return final_delay == 0xff ? -EIO : 0; in msdc_tune_response()
2111 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); in hs400_tune_response()
2112 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); in hs400_tune_response()
2114 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in hs400_tune_response()
2115 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in hs400_tune_response()
2116 sdr_set_field(host->base + MSDC_PAD_TUNE, in hs400_tune_response()
2118 host->hs200_cmd_int_delay); in hs400_tune_response()
2120 if (host->hs400_cmd_resp_sel_rising) in hs400_tune_response()
2121 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2123 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2125 sdr_set_field(host->base + PAD_CMD_TUNE, in hs400_tune_response()
2143 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, in hs400_tune_response()
2147 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in hs400_tune_response()
2148 return final_delay == 0xff ? -EIO : 0; in hs400_tune_response()
2159 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_data()
2160 host->latch_ck); in msdc_tune_data()
2161 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2162 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2175 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2176 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2188 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2189 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2192 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2193 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2198 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); in msdc_tune_data()
2199 return final_delay == 0xff ? -EIO : 0; in msdc_tune_data()
2214 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_together()
2215 host->latch_ck); in msdc_tune_together()
2217 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2218 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2233 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2234 sdr_set_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2248 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2249 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2253 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2254 sdr_set_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2262 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); in msdc_tune_together()
2263 return final_delay == 0xff ? -EIO : 0; in msdc_tune_together()
2270 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_execute_tuning()
2272 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { in msdc_execute_tuning()
2274 if (host->hs400_mode) { in msdc_execute_tuning()
2275 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_execute_tuning()
2281 if (host->hs400_mode && in msdc_execute_tuning()
2282 host->dev_comp->hs400_tune) in msdc_execute_tuning()
2286 if (ret == -EIO) { in msdc_execute_tuning()
2287 dev_err(host->dev, "Tune response fail!\n"); in msdc_execute_tuning()
2290 if (host->hs400_mode == false) { in msdc_execute_tuning()
2292 if (ret == -EIO) in msdc_execute_tuning()
2293 dev_err(host->dev, "Tune data fail!\n"); in msdc_execute_tuning()
2297 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_execute_tuning()
2298 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_execute_tuning()
2299 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_execute_tuning()
2300 if (host->top_base) { in msdc_execute_tuning()
2301 host->saved_tune_para.emmc_top_control = readl(host->top_base + in msdc_execute_tuning()
2303 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + in msdc_execute_tuning()
2312 host->hs400_mode = true; in msdc_prepare_hs400_tuning()
2314 if (host->top_base) in msdc_prepare_hs400_tuning()
2315 writel(host->hs400_ds_delay, in msdc_prepare_hs400_tuning()
2316 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2318 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2320 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); in msdc_prepare_hs400_tuning()
2322 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); in msdc_prepare_hs400_tuning()
2335 if (host->top_base) { in msdc_execute_hs400_tuning()
2336 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2338 if (host->hs400_ds_dly3) in msdc_execute_hs400_tuning()
2339 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2340 PAD_DS_DLY3, host->hs400_ds_dly3); in msdc_execute_hs400_tuning()
2342 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); in msdc_execute_hs400_tuning()
2343 if (host->hs400_ds_dly3) in msdc_execute_hs400_tuning()
2344 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2345 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); in msdc_execute_hs400_tuning()
2348 host->hs400_tuning = true; in msdc_execute_hs400_tuning()
2350 if (host->top_base) in msdc_execute_hs400_tuning()
2351 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2354 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2362 host->hs400_tuning = false; in msdc_execute_hs400_tuning()
2366 dev_err(host->dev, "Failed to get DLY1 delay!\n"); in msdc_execute_hs400_tuning()
2369 if (host->top_base) in msdc_execute_hs400_tuning()
2370 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2373 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2376 if (host->top_base) in msdc_execute_hs400_tuning()
2377 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2379 val = readl(host->base + PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2381 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); in msdc_execute_hs400_tuning()
2386 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); in msdc_execute_hs400_tuning()
2387 return -EIO; in msdc_execute_hs400_tuning()
2394 sdr_set_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2396 sdr_clr_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2404 spin_lock_irqsave(&host->lock, flags); in msdc_ack_sdio_irq()
2406 spin_unlock_irqrestore(&host->lock, flags); in msdc_ack_sdio_irq()
2414 if (mmc->caps & MMC_CAP_NONREMOVABLE) in msdc_get_cd()
2417 if (!host->internal_cd) in msdc_get_cd()
2420 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; in msdc_get_cd()
2421 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) in msdc_get_cd()
2432 if (ios->enhanced_strobe) { in msdc_hs400_enhanced_strobe()
2434 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); in msdc_hs400_enhanced_strobe()
2435 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); in msdc_hs400_enhanced_strobe()
2436 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); in msdc_hs400_enhanced_strobe()
2438 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2439 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2440 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); in msdc_hs400_enhanced_strobe()
2442 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); in msdc_hs400_enhanced_strobe()
2443 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); in msdc_hs400_enhanced_strobe()
2444 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); in msdc_hs400_enhanced_strobe()
2446 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2447 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2448 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); in msdc_hs400_enhanced_strobe()
2455 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_cit_cal()
2464 hclk_freq = (u64)clk_get_rate(host->h_clk); in msdc_cqe_cit_cal()
2482 host->cq_ssc1_time = 0x40; in msdc_cqe_cit_cal()
2488 host->cq_ssc1_time = value; in msdc_cqe_cit_cal()
2494 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_enable()
2497 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); in msdc_cqe_enable()
2499 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_enable()
2506 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1); in msdc_cqe_enable()
2515 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); in msdc_cqe_disable()
2517 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_disable()
2519 val = readl(host->base + MSDC_INT); in msdc_cqe_disable()
2520 writel(val, host->base + MSDC_INT); in msdc_cqe_disable()
2523 sdr_set_field(host->base + MSDC_DMA_CTRL, in msdc_cqe_disable()
2525 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, in msdc_cqe_disable()
2528 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, in msdc_cqe_disable()
2537 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_pre_enable()
2547 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_post_disable()
2583 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", in msdc_of_property_parse()
2584 &host->latch_ck); in msdc_of_property_parse()
2586 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", in msdc_of_property_parse()
2587 &host->hs400_ds_delay); in msdc_of_property_parse()
2589 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", in msdc_of_property_parse()
2590 &host->hs400_ds_dly3); in msdc_of_property_parse()
2592 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", in msdc_of_property_parse()
2593 &host->hs200_cmd_int_delay); in msdc_of_property_parse()
2595 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", in msdc_of_property_parse()
2596 &host->hs400_cmd_int_delay); in msdc_of_property_parse()
2598 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2599 "mediatek,hs400-cmd-resp-sel-rising")) in msdc_of_property_parse()
2600 host->hs400_cmd_resp_sel_rising = true; in msdc_of_property_parse()
2602 host->hs400_cmd_resp_sel_rising = false; in msdc_of_property_parse()
2604 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2605 "supports-cqe")) in msdc_of_property_parse()
2606 host->cqhci = true; in msdc_of_property_parse()
2608 host->cqhci = false; in msdc_of_property_parse()
2616 host->src_clk = devm_clk_get(&pdev->dev, "source"); in msdc_of_clock_parse()
2617 if (IS_ERR(host->src_clk)) in msdc_of_clock_parse()
2618 return PTR_ERR(host->src_clk); in msdc_of_clock_parse()
2620 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); in msdc_of_clock_parse()
2621 if (IS_ERR(host->h_clk)) in msdc_of_clock_parse()
2622 return PTR_ERR(host->h_clk); in msdc_of_clock_parse()
2624 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); in msdc_of_clock_parse()
2625 if (IS_ERR(host->bus_clk)) in msdc_of_clock_parse()
2626 host->bus_clk = NULL; in msdc_of_clock_parse()
2629 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); in msdc_of_clock_parse()
2630 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2631 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2634 * Fallback for legacy device-trees: src_clk and HCLK use the same in msdc_of_clock_parse()
2640 if (!host->src_clk_cg) { in msdc_of_clock_parse()
2641 host->src_clk_cg = clk_get_parent(host->src_clk); in msdc_of_clock_parse()
2642 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2643 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2647 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg"); in msdc_of_clock_parse()
2648 if (IS_ERR(host->sys_clk_cg)) in msdc_of_clock_parse()
2649 host->sys_clk_cg = NULL; in msdc_of_clock_parse()
2651 host->bulk_clks[0].id = "pclk_cg"; in msdc_of_clock_parse()
2652 host->bulk_clks[1].id = "axi_cg"; in msdc_of_clock_parse()
2653 host->bulk_clks[2].id = "ahb_cg"; in msdc_of_clock_parse()
2654 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, in msdc_of_clock_parse()
2655 host->bulk_clks); in msdc_of_clock_parse()
2657 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); in msdc_of_clock_parse()
2671 if (!pdev->dev.of_node) { in msdc_drv_probe()
2672 dev_err(&pdev->dev, "No DT found\n"); in msdc_drv_probe()
2673 return -EINVAL; in msdc_drv_probe()
2677 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct msdc_host)); in msdc_drv_probe()
2679 return -ENOMEM; in msdc_drv_probe()
2686 host->base = devm_platform_ioremap_resource(pdev, 0); in msdc_drv_probe()
2687 if (IS_ERR(host->base)) in msdc_drv_probe()
2688 return PTR_ERR(host->base); in msdc_drv_probe()
2692 host->top_base = devm_ioremap_resource(&pdev->dev, res); in msdc_drv_probe()
2693 if (IS_ERR(host->top_base)) in msdc_drv_probe()
2694 host->top_base = NULL; in msdc_drv_probe()
2705 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, in msdc_drv_probe()
2707 if (IS_ERR(host->reset)) in msdc_drv_probe()
2708 return PTR_ERR(host->reset); in msdc_drv_probe()
2711 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { in msdc_drv_probe()
2712 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); in msdc_drv_probe()
2713 if (IS_ERR(host->crypto_clk)) in msdc_drv_probe()
2714 return PTR_ERR(host->crypto_clk); in msdc_drv_probe()
2715 else if (host->crypto_clk) in msdc_drv_probe()
2716 mmc->caps2 |= MMC_CAP2_CRYPTO; in msdc_drv_probe()
2719 host->irq = platform_get_irq(pdev, 0); in msdc_drv_probe()
2720 if (host->irq < 0) in msdc_drv_probe()
2721 return host->irq; in msdc_drv_probe()
2723 host->pinctrl = devm_pinctrl_get(&pdev->dev); in msdc_drv_probe()
2724 if (IS_ERR(host->pinctrl)) in msdc_drv_probe()
2725 return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl), in msdc_drv_probe()
2726 "Cannot find pinctrl"); in msdc_drv_probe()
2728 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); in msdc_drv_probe()
2729 if (IS_ERR(host->pins_default)) { in msdc_drv_probe()
2730 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); in msdc_drv_probe()
2731 return PTR_ERR(host->pins_default); in msdc_drv_probe()
2734 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); in msdc_drv_probe()
2735 if (IS_ERR(host->pins_uhs)) { in msdc_drv_probe()
2736 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); in msdc_drv_probe()
2737 return PTR_ERR(host->pins_uhs); in msdc_drv_probe()
2741 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) { in msdc_drv_probe()
2742 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup"); in msdc_drv_probe()
2743 if (host->eint_irq > 0) { in msdc_drv_probe()
2744 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); in msdc_drv_probe()
2745 if (IS_ERR(host->pins_eint)) { in msdc_drv_probe()
2746 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); in msdc_drv_probe()
2747 host->pins_eint = NULL; in msdc_drv_probe()
2749 device_init_wakeup(&pdev->dev, true); in msdc_drv_probe()
2756 host->dev = &pdev->dev; in msdc_drv_probe()
2757 host->dev_comp = of_device_get_match_data(&pdev->dev); in msdc_drv_probe()
2758 host->src_clk_freq = clk_get_rate(host->src_clk); in msdc_drv_probe()
2760 mmc->ops = &mt_msdc_ops; in msdc_drv_probe()
2761 if (host->dev_comp->clk_div_bits == 8) in msdc_drv_probe()
2762 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); in msdc_drv_probe()
2764 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); in msdc_drv_probe()
2766 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && in msdc_drv_probe()
2768 host->dev_comp->use_internal_cd) { in msdc_drv_probe()
2773 host->internal_cd = true; in msdc_drv_probe()
2776 if (mmc->caps & MMC_CAP_SDIO_IRQ) in msdc_drv_probe()
2777 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in msdc_drv_probe()
2779 mmc->caps |= MMC_CAP_CMD23; in msdc_drv_probe()
2780 if (host->cqhci) in msdc_drv_probe()
2781 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in msdc_drv_probe()
2783 mmc->max_segs = MAX_BD_NUM; in msdc_drv_probe()
2784 if (host->dev_comp->support_64g) in msdc_drv_probe()
2785 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; in msdc_drv_probe()
2787 mmc->max_seg_size = BDMA_DESC_BUFLEN; in msdc_drv_probe()
2788 mmc->max_blk_size = 2048; in msdc_drv_probe()
2789 mmc->max_req_size = 512 * 1024; in msdc_drv_probe()
2790 mmc->max_blk_count = mmc->max_req_size / 512; in msdc_drv_probe()
2791 if (host->dev_comp->support_64g) in msdc_drv_probe()
2792 host->dma_mask = DMA_BIT_MASK(36); in msdc_drv_probe()
2794 host->dma_mask = DMA_BIT_MASK(32); in msdc_drv_probe()
2795 mmc_dev(mmc)->dma_mask = &host->dma_mask; in msdc_drv_probe()
2797 host->timeout_clks = 3 * 1048576; in msdc_drv_probe()
2798 host->dma.gpd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2800 &host->dma.gpd_addr, GFP_KERNEL); in msdc_drv_probe()
2801 host->dma.bd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2803 &host->dma.bd_addr, GFP_KERNEL); in msdc_drv_probe()
2804 if (!host->dma.gpd || !host->dma.bd) { in msdc_drv_probe()
2805 ret = -ENOMEM; in msdc_drv_probe()
2808 msdc_init_gpd_bd(host, &host->dma); in msdc_drv_probe()
2809 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); in msdc_drv_probe()
2810 spin_lock_init(&host->lock); in msdc_drv_probe()
2815 dev_err(&pdev->dev, "Cannot ungate clocks!\n"); in msdc_drv_probe()
2820 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_drv_probe()
2821 host->cq_host = devm_kzalloc(mmc->parent, in msdc_drv_probe()
2822 sizeof(*host->cq_host), in msdc_drv_probe()
2824 if (!host->cq_host) { in msdc_drv_probe()
2825 ret = -ENOMEM; in msdc_drv_probe()
2828 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in msdc_drv_probe()
2829 host->cq_host->mmio = host->base + 0x800; in msdc_drv_probe()
2830 host->cq_host->ops = &msdc_cmdq_ops; in msdc_drv_probe()
2831 ret = cqhci_init(host->cq_host, mmc, true); in msdc_drv_probe()
2834 mmc->max_segs = 128; in msdc_drv_probe()
2836 /* 0 size, means 65536 so we don't have to -1 here */ in msdc_drv_probe()
2837 mmc->max_seg_size = 64 * 1024; in msdc_drv_probe()
2842 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, in msdc_drv_probe()
2843 IRQF_TRIGGER_NONE, pdev->name, host); in msdc_drv_probe()
2847 pm_runtime_set_active(host->dev); in msdc_drv_probe()
2848 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); in msdc_drv_probe()
2849 pm_runtime_use_autosuspend(host->dev); in msdc_drv_probe()
2850 pm_runtime_enable(host->dev); in msdc_drv_probe()
2858 pm_runtime_disable(host->dev); in msdc_drv_probe()
2865 device_init_wakeup(&pdev->dev, false); in msdc_drv_probe()
2866 if (host->dma.gpd) in msdc_drv_probe()
2867 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
2869 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_probe()
2870 if (host->dma.bd) in msdc_drv_probe()
2871 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
2873 host->dma.bd, host->dma.bd_addr); in msdc_drv_probe()
2885 pm_runtime_get_sync(host->dev); in msdc_drv_remove()
2892 pm_runtime_disable(host->dev); in msdc_drv_remove()
2893 pm_runtime_put_noidle(host->dev); in msdc_drv_remove()
2894 dma_free_coherent(&pdev->dev, in msdc_drv_remove()
2896 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_remove()
2897 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), in msdc_drv_remove()
2898 host->dma.bd, host->dma.bd_addr); in msdc_drv_remove()
2899 device_init_wakeup(&pdev->dev, false); in msdc_drv_remove()
2904 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_save_reg()
2906 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); in msdc_save_reg()
2907 host->save_para.iocon = readl(host->base + MSDC_IOCON); in msdc_save_reg()
2908 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); in msdc_save_reg()
2909 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); in msdc_save_reg()
2910 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); in msdc_save_reg()
2911 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); in msdc_save_reg()
2912 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); in msdc_save_reg()
2913 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_save_reg()
2914 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); in msdc_save_reg()
2915 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); in msdc_save_reg()
2916 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); in msdc_save_reg()
2917 if (host->top_base) { in msdc_save_reg()
2918 host->save_para.emmc_top_control = in msdc_save_reg()
2919 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_save_reg()
2920 host->save_para.emmc_top_cmd = in msdc_save_reg()
2921 readl(host->top_base + EMMC_TOP_CMD); in msdc_save_reg()
2922 host->save_para.emmc50_pad_ds_tune = in msdc_save_reg()
2923 readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_save_reg()
2925 host->save_para.pad_tune = readl(host->base + tune_reg); in msdc_save_reg()
2932 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_restore_reg()
2934 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); in msdc_restore_reg()
2935 writel(host->save_para.iocon, host->base + MSDC_IOCON); in msdc_restore_reg()
2936 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); in msdc_restore_reg()
2937 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); in msdc_restore_reg()
2938 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); in msdc_restore_reg()
2939 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); in msdc_restore_reg()
2940 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); in msdc_restore_reg()
2941 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); in msdc_restore_reg()
2942 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); in msdc_restore_reg()
2943 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); in msdc_restore_reg()
2944 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); in msdc_restore_reg()
2945 if (host->top_base) { in msdc_restore_reg()
2946 writel(host->save_para.emmc_top_control, in msdc_restore_reg()
2947 host->top_base + EMMC_TOP_CONTROL); in msdc_restore_reg()
2948 writel(host->save_para.emmc_top_cmd, in msdc_restore_reg()
2949 host->top_base + EMMC_TOP_CMD); in msdc_restore_reg()
2950 writel(host->save_para.emmc50_pad_ds_tune, in msdc_restore_reg()
2951 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_restore_reg()
2953 writel(host->save_para.pad_tune, host->base + tune_reg); in msdc_restore_reg()
2968 if (host->pins_eint) { in msdc_runtime_suspend()
2969 disable_irq(host->irq); in msdc_runtime_suspend()
2970 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_runtime_suspend()
2991 if (sdio_irq_claimed(mmc) && host->pins_eint) { in msdc_runtime_resume()
2992 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_runtime_resume()
2993 enable_irq(host->irq); in msdc_runtime_resume()
3005 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_suspend()
3009 val = readl(host->base + MSDC_INT); in msdc_suspend()
3010 writel(val, host->base + MSDC_INT); in msdc_suspend()
3014 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will in msdc_suspend()
3017 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_suspend()
3028 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_resume()
3043 .name = "mtk-msdc",