Lines Matching +full:mmci +full:- +full:gpio +full:- +full:supply
1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
6 * Copyright (C) 2010 ST-Ericsson SA
26 #include <linux/mmc/slot-gpio.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/amba/mmci.h>
39 #include <linux/gpio/consumer.h>
45 #include "mmci.h"
47 #define DRIVER_NAME "mmci-pl18x"
373 spin_lock_irqsave(&host->lock, flags); in mmci_card_busy()
374 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) in mmci_card_busy()
376 spin_unlock_irqrestore(&host->lock, flags); in mmci_card_busy()
390 if (host->cclk < 25000000) in mmci_reg_delay()
397 * This must be called with host->lock held
401 if (host->clk_reg != clk) { in mmci_write_clkreg()
402 host->clk_reg = clk; in mmci_write_clkreg()
403 writel(clk, host->base + MMCICLOCK); in mmci_write_clkreg()
408 * This must be called with host->lock held
412 if (host->pwr_reg != pwr) { in mmci_write_pwrreg()
413 host->pwr_reg = pwr; in mmci_write_pwrreg()
414 writel(pwr, host->base + MMCIPOWER); in mmci_write_pwrreg()
419 * This must be called with host->lock held
424 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; in mmci_write_datactrlreg()
426 if (host->datactrl_reg != datactrl) { in mmci_write_datactrlreg()
427 host->datactrl_reg = datactrl; in mmci_write_datactrlreg()
428 writel(datactrl, host->base + MMCIDATACTRL); in mmci_write_datactrlreg()
433 * This must be called with host->lock held
437 struct variant_data *variant = host->variant; in mmci_set_clkreg()
438 u32 clk = variant->clkreg; in mmci_set_clkreg()
441 host->cclk = 0; in mmci_set_clkreg()
444 if (variant->explicit_mclk_control) { in mmci_set_clkreg()
445 host->cclk = host->mclk; in mmci_set_clkreg()
446 } else if (desired >= host->mclk) { in mmci_set_clkreg()
448 if (variant->st_clkdiv) in mmci_set_clkreg()
450 host->cclk = host->mclk; in mmci_set_clkreg()
451 } else if (variant->st_clkdiv) { in mmci_set_clkreg()
454 * => clkdiv = (mclk / f) - 2 in mmci_set_clkreg()
458 clk = DIV_ROUND_UP(host->mclk, desired) - 2; in mmci_set_clkreg()
461 host->cclk = host->mclk / (clk + 2); in mmci_set_clkreg()
465 * => clkdiv = mclk / (2 * f) - 1 in mmci_set_clkreg()
467 clk = host->mclk / (2 * desired) - 1; in mmci_set_clkreg()
470 host->cclk = host->mclk / (2 * (clk + 1)); in mmci_set_clkreg()
473 clk |= variant->clkreg_enable; in mmci_set_clkreg()
480 host->mmc->actual_clock = host->cclk; in mmci_set_clkreg()
482 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) in mmci_set_clkreg()
484 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) in mmci_set_clkreg()
485 clk |= variant->clkreg_8bit_bus_enable; in mmci_set_clkreg()
487 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || in mmci_set_clkreg()
488 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) in mmci_set_clkreg()
489 clk |= variant->clkreg_neg_edge_enable; in mmci_set_clkreg()
496 if (host->ops && host->ops->dma_release) in mmci_dma_release()
497 host->ops->dma_release(host); in mmci_dma_release()
499 host->use_dma = false; in mmci_dma_release()
504 if (!host->ops || !host->ops->dma_setup) in mmci_dma_setup()
507 if (host->ops->dma_setup(host)) in mmci_dma_setup()
511 host->next_cookie = 1; in mmci_dma_setup()
513 host->use_dma = true; in mmci_dma_setup()
522 struct variant_data *variant = host->variant; in mmci_validate_data()
526 if (!is_power_of_2(data->blksz) && !variant->datactrl_any_blocksz) { in mmci_validate_data()
527 dev_err(mmc_dev(host->mmc), in mmci_validate_data()
528 "unsupported block size (%d bytes)\n", data->blksz); in mmci_validate_data()
529 return -EINVAL; in mmci_validate_data()
532 if (host->ops && host->ops->validate_data) in mmci_validate_data()
533 return host->ops->validate_data(host, data); in mmci_validate_data()
542 if (!host->ops || !host->ops->prep_data) in mmci_prep_data()
545 err = host->ops->prep_data(host, data, next); in mmci_prep_data()
548 data->host_cookie = ++host->next_cookie < 0 ? in mmci_prep_data()
549 1 : host->next_cookie; in mmci_prep_data()
557 if (host->ops && host->ops->unprep_data) in mmci_unprep_data()
558 host->ops->unprep_data(host, data, err); in mmci_unprep_data()
560 data->host_cookie = 0; in mmci_unprep_data()
565 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); in mmci_get_next_data()
567 if (host->ops && host->ops->get_next_data) in mmci_get_next_data()
568 host->ops->get_next_data(host, data); in mmci_get_next_data()
573 struct mmc_data *data = host->data; in mmci_dma_start()
576 if (!host->use_dma) in mmci_dma_start()
577 return -EINVAL; in mmci_dma_start()
583 if (!host->ops || !host->ops->dma_start) in mmci_dma_start()
584 return -EINVAL; in mmci_dma_start()
587 dev_vdbg(mmc_dev(host->mmc), in mmci_dma_start()
588 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", in mmci_dma_start()
589 data->sg_len, data->blksz, data->blocks, data->flags); in mmci_dma_start()
591 ret = host->ops->dma_start(host, &datactrl); in mmci_dma_start()
599 * Let the MMCI say when the data is ended and it's time in mmci_dma_start()
600 * to fire next DMA request. When that happens, MMCI will in mmci_dma_start()
603 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, in mmci_dma_start()
604 host->base + MMCIMASK0); in mmci_dma_start()
610 if (!host->use_dma) in mmci_dma_finalize()
613 if (host->ops && host->ops->dma_finalize) in mmci_dma_finalize()
614 host->ops->dma_finalize(host, data); in mmci_dma_finalize()
619 if (!host->use_dma) in mmci_dma_error()
622 if (host->ops && host->ops->dma_error) in mmci_dma_error()
623 host->ops->dma_error(host); in mmci_dma_error()
629 writel(0, host->base + MMCICOMMAND); in mmci_request_end()
631 BUG_ON(host->data); in mmci_request_end()
633 host->mrq = NULL; in mmci_request_end()
634 host->cmd = NULL; in mmci_request_end()
636 mmc_request_done(host->mmc, mrq); in mmci_request_end()
641 void __iomem *base = host->base; in mmci_set_mask1()
642 struct variant_data *variant = host->variant; in mmci_set_mask1()
644 if (host->singleirq) { in mmci_set_mask1()
647 mask0 &= ~variant->irq_pio_mask; in mmci_set_mask1()
653 if (variant->mmcimask1) in mmci_set_mask1()
656 host->mask1_reg = mask; in mmci_set_mask1()
663 host->data = NULL; in mmci_stop_data()
670 if (data->flags & MMC_DATA_READ) in mmci_init_sg()
675 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); in mmci_init_sg()
685 return MCI_DPSM_ENABLE | (host->data->blksz << 16); in ux500v2_get_dctrl_cfg()
690 void __iomem *base = host->base; in ux500_busy_clear_mask_done()
692 writel(host->variant->busy_detect_mask, base + MMCICLEAR); in ux500_busy_clear_mask_done()
694 ~host->variant->busy_detect_mask, base + MMCIMASK0); in ux500_busy_clear_mask_done()
695 host->busy_state = MMCI_BUSY_DONE; in ux500_busy_clear_mask_done()
696 host->busy_status = 0; in ux500_busy_clear_mask_done()
700 * ux500_busy_complete() - this will wait until the busy status
702 * host->busy_status until we know the card is not busy any more.
708 * DAT0 busy +-----------------+
710 * DAT0 not busy ----+ +--------
719 void __iomem *base = host->base; in ux500_busy_complete()
732 switch (host->busy_state) { in ux500_busy_complete()
737 * command in-progress, waiting for busy signaling to end, in ux500_busy_complete()
738 * store the status in host->busy_status. in ux500_busy_complete()
741 * it starts signaling busy on DAT0, hence re-read the in ux500_busy_complete()
749 * host->busy_status, which is what it should be in IDLE. in ux500_busy_complete()
751 host->busy_status = status & (MCI_CMDSENT | MCI_CMDRESPEND); in ux500_busy_complete()
755 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); in ux500_busy_complete()
756 if (status & host->variant->busy_detect_flag) { in ux500_busy_complete()
758 host->variant->busy_detect_mask, in ux500_busy_complete()
760 host->busy_state = MMCI_BUSY_WAITING_FOR_START_IRQ; in ux500_busy_complete()
761 schedule_delayed_work(&host->ux500_busy_timeout_work, in ux500_busy_complete()
762 msecs_to_jiffies(cmd->busy_timeout)); in ux500_busy_complete()
765 retries--; in ux500_busy_complete()
767 dev_dbg(mmc_dev(host->mmc), in ux500_busy_complete()
768 "no busy signalling in time CMD%02x\n", cmd->opcode); in ux500_busy_complete()
773 * If there is a command in-progress that has been successfully in ux500_busy_complete()
784 if (status & host->variant->busy_detect_flag) { in ux500_busy_complete()
785 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); in ux500_busy_complete()
786 writel(host->variant->busy_detect_mask, base + MMCICLEAR); in ux500_busy_complete()
787 host->busy_state = MMCI_BUSY_WAITING_FOR_END_IRQ; in ux500_busy_complete()
789 dev_dbg(mmc_dev(host->mmc), in ux500_busy_complete()
791 cmd->opcode); in ux500_busy_complete()
792 cancel_delayed_work(&host->ux500_busy_timeout_work); in ux500_busy_complete()
798 if (!(status & host->variant->busy_detect_flag)) { in ux500_busy_complete()
799 host->busy_status |= status & (MCI_CMDSENT | MCI_CMDRESPEND); in ux500_busy_complete()
800 writel(host->variant->busy_detect_mask, base + MMCICLEAR); in ux500_busy_complete()
801 cancel_delayed_work(&host->ux500_busy_timeout_work); in ux500_busy_complete()
804 dev_dbg(mmc_dev(host->mmc), in ux500_busy_complete()
805 "busy status still asserted when handling busy end IRQ - will keep waiting CMD%02x\n", in ux500_busy_complete()
806 cmd->opcode); in ux500_busy_complete()
811 dev_dbg(mmc_dev(host->mmc), "fell through on state %d, CMD%02x\n", in ux500_busy_complete()
812 host->busy_state, cmd->opcode); in ux500_busy_complete()
817 return (host->busy_state == MMCI_BUSY_DONE); in ux500_busy_complete()
844 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); in mmci_dmae_setup()
846 return -ENOMEM; in mmci_dmae_setup()
848 host->dma_priv = dmae; in mmci_dmae_setup()
850 dmae->rx_channel = dma_request_chan(mmc_dev(host->mmc), "rx"); in mmci_dmae_setup()
851 if (IS_ERR(dmae->rx_channel)) { in mmci_dmae_setup()
852 int ret = PTR_ERR(dmae->rx_channel); in mmci_dmae_setup()
853 dmae->rx_channel = NULL; in mmci_dmae_setup()
857 dmae->tx_channel = dma_request_chan(mmc_dev(host->mmc), "tx"); in mmci_dmae_setup()
858 if (IS_ERR(dmae->tx_channel)) { in mmci_dmae_setup()
859 if (PTR_ERR(dmae->tx_channel) == -EPROBE_DEFER) in mmci_dmae_setup()
860 dev_warn(mmc_dev(host->mmc), in mmci_dmae_setup()
862 dmae->tx_channel = NULL; in mmci_dmae_setup()
870 if (dmae->rx_channel && !dmae->tx_channel) in mmci_dmae_setup()
871 dmae->tx_channel = dmae->rx_channel; in mmci_dmae_setup()
873 if (dmae->rx_channel) in mmci_dmae_setup()
874 rxname = dma_chan_name(dmae->rx_channel); in mmci_dmae_setup()
878 if (dmae->tx_channel) in mmci_dmae_setup()
879 txname = dma_chan_name(dmae->tx_channel); in mmci_dmae_setup()
883 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", in mmci_dmae_setup()
890 if (dmae->tx_channel) { in mmci_dmae_setup()
891 struct device *dev = dmae->tx_channel->device->dev; in mmci_dmae_setup()
894 if (max_seg_size < host->mmc->max_seg_size) in mmci_dmae_setup()
895 host->mmc->max_seg_size = max_seg_size; in mmci_dmae_setup()
897 if (dmae->rx_channel) { in mmci_dmae_setup()
898 struct device *dev = dmae->rx_channel->device->dev; in mmci_dmae_setup()
901 if (max_seg_size < host->mmc->max_seg_size) in mmci_dmae_setup()
902 host->mmc->max_seg_size = max_seg_size; in mmci_dmae_setup()
905 if (!dmae->tx_channel || !dmae->rx_channel) { in mmci_dmae_setup()
907 return -EINVAL; in mmci_dmae_setup()
919 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_release()
921 if (dmae->rx_channel) in mmci_dmae_release()
922 dma_release_channel(dmae->rx_channel); in mmci_dmae_release()
923 if (dmae->tx_channel) in mmci_dmae_release()
924 dma_release_channel(dmae->tx_channel); in mmci_dmae_release()
925 dmae->rx_channel = dmae->tx_channel = NULL; in mmci_dmae_release()
930 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dma_unmap()
933 if (data->flags & MMC_DATA_READ) in mmci_dma_unmap()
934 chan = dmae->rx_channel; in mmci_dma_unmap()
936 chan = dmae->tx_channel; in mmci_dma_unmap()
938 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, in mmci_dma_unmap()
944 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_error()
949 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); in mmci_dmae_error()
950 dmaengine_terminate_all(dmae->cur); in mmci_dmae_error()
951 host->dma_in_progress = false; in mmci_dmae_error()
952 dmae->cur = NULL; in mmci_dmae_error()
953 dmae->desc_current = NULL; in mmci_dmae_error()
954 host->data->host_cookie = 0; in mmci_dmae_error()
956 mmci_dma_unmap(host, host->data); in mmci_dmae_error()
961 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_finalize()
970 status = readl(host->base + MMCISTATUS); in mmci_dmae_finalize()
977 * Check to see whether we still have some data left in the FIFO - in mmci_dmae_finalize()
979 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- in mmci_dmae_finalize()
984 if (!data->error) in mmci_dmae_finalize()
985 data->error = -EIO; in mmci_dmae_finalize()
986 } else if (!data->host_cookie) { in mmci_dmae_finalize()
991 * Use of DMA with scatter-gather is impossible. in mmci_dmae_finalize()
995 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); in mmci_dmae_finalize()
999 host->dma_in_progress = false; in mmci_dmae_finalize()
1000 dmae->cur = NULL; in mmci_dmae_finalize()
1001 dmae->desc_current = NULL; in mmci_dmae_finalize()
1004 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
1009 struct mmci_dmae_priv *dmae = host->dma_priv; in _mmci_dmae_prep_data()
1010 struct variant_data *variant = host->variant; in _mmci_dmae_prep_data()
1012 .src_addr = host->phybase + MMCIFIFO, in _mmci_dmae_prep_data()
1013 .dst_addr = host->phybase + MMCIFIFO, in _mmci_dmae_prep_data()
1016 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ in _mmci_dmae_prep_data()
1017 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ in _mmci_dmae_prep_data()
1026 if (data->flags & MMC_DATA_READ) { in _mmci_dmae_prep_data()
1028 chan = dmae->rx_channel; in _mmci_dmae_prep_data()
1031 chan = dmae->tx_channel; in _mmci_dmae_prep_data()
1036 return -EINVAL; in _mmci_dmae_prep_data()
1039 if (data->blksz * data->blocks <= variant->fifosize) in _mmci_dmae_prep_data()
1040 return -EINVAL; in _mmci_dmae_prep_data()
1045 * - The Ux500 DMA controller (DMA40) in _mmci_dmae_prep_data()
1046 * - The MMCI DMA interface on the Ux500 in _mmci_dmae_prep_data()
1051 if (host->variant->dma_power_of_2 && !is_power_of_2(data->blksz)) in _mmci_dmae_prep_data()
1052 return -EINVAL; in _mmci_dmae_prep_data()
1054 device = chan->device; in _mmci_dmae_prep_data()
1055 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, in _mmci_dmae_prep_data()
1058 return -EINVAL; in _mmci_dmae_prep_data()
1060 if (host->variant->qcom_dml) in _mmci_dmae_prep_data()
1064 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, in _mmci_dmae_prep_data()
1075 dma_unmap_sg(device->dev, data->sg, data->sg_len, in _mmci_dmae_prep_data()
1077 return -ENOMEM; in _mmci_dmae_prep_data()
1084 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_prep_data()
1085 struct mmci_dmae_next *nd = &dmae->next_data; in mmci_dmae_prep_data()
1087 if (!host->use_dma) in mmci_dmae_prep_data()
1088 return -EINVAL; in mmci_dmae_prep_data()
1091 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); in mmci_dmae_prep_data()
1093 if (dmae->cur && dmae->desc_current) in mmci_dmae_prep_data()
1097 return _mmci_dmae_prep_data(host, data, &dmae->cur, in mmci_dmae_prep_data()
1098 &dmae->desc_current); in mmci_dmae_prep_data()
1103 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_start()
1106 host->dma_in_progress = true; in mmci_dmae_start()
1107 ret = dma_submit_error(dmaengine_submit(dmae->desc_current)); in mmci_dmae_start()
1109 host->dma_in_progress = false; in mmci_dmae_start()
1112 dma_async_issue_pending(dmae->cur); in mmci_dmae_start()
1121 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_get_next_data()
1122 struct mmci_dmae_next *next = &dmae->next_data; in mmci_dmae_get_next_data()
1124 if (!host->use_dma) in mmci_dmae_get_next_data()
1127 WARN_ON(!data->host_cookie && (next->desc || next->chan)); in mmci_dmae_get_next_data()
1129 dmae->desc_current = next->desc; in mmci_dmae_get_next_data()
1130 dmae->cur = next->chan; in mmci_dmae_get_next_data()
1131 next->desc = NULL; in mmci_dmae_get_next_data()
1132 next->chan = NULL; in mmci_dmae_get_next_data()
1139 struct mmci_dmae_priv *dmae = host->dma_priv; in mmci_dmae_unprep_data()
1141 if (!host->use_dma) in mmci_dmae_unprep_data()
1147 struct mmci_dmae_next *next = &dmae->next_data; in mmci_dmae_unprep_data()
1149 if (data->flags & MMC_DATA_READ) in mmci_dmae_unprep_data()
1150 chan = dmae->rx_channel; in mmci_dmae_unprep_data()
1152 chan = dmae->tx_channel; in mmci_dmae_unprep_data()
1155 if (dmae->desc_current == next->desc) in mmci_dmae_unprep_data()
1156 dmae->desc_current = NULL; in mmci_dmae_unprep_data()
1158 if (dmae->cur == next->chan) { in mmci_dmae_unprep_data()
1159 host->dma_in_progress = false; in mmci_dmae_unprep_data()
1160 dmae->cur = NULL; in mmci_dmae_unprep_data()
1163 next->desc = NULL; in mmci_dmae_unprep_data()
1164 next->chan = NULL; in mmci_dmae_unprep_data()
1187 host->ops = &mmci_variant_ops; in mmci_variant_init()
1192 host->ops = &mmci_variant_ops; in ux500_variant_init()
1193 host->ops->busy_complete = ux500_busy_complete; in ux500_variant_init()
1198 host->ops = &mmci_variant_ops; in ux500v2_variant_init()
1199 host->ops->busy_complete = ux500_busy_complete; in ux500v2_variant_init()
1200 host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg; in ux500v2_variant_init()
1206 struct mmc_data *data = mrq->data; in mmci_pre_request()
1211 WARN_ON(data->host_cookie); in mmci_pre_request()
1223 struct mmc_data *data = mrq->data; in mmci_post_request()
1225 if (!data || !data->host_cookie) in mmci_post_request()
1233 struct variant_data *variant = host->variant; in mmci_start_data()
1238 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", in mmci_start_data()
1239 data->blksz, data->blocks, data->flags); in mmci_start_data()
1241 host->data = data; in mmci_start_data()
1242 host->size = data->blksz * data->blocks; in mmci_start_data()
1243 data->bytes_xfered = 0; in mmci_start_data()
1245 clks = (unsigned long long)data->timeout_ns * host->cclk; in mmci_start_data()
1248 timeout = data->timeout_clks + (unsigned int)clks; in mmci_start_data()
1250 base = host->base; in mmci_start_data()
1252 writel(host->size, base + MMCIDATALENGTH); in mmci_start_data()
1254 datactrl = host->ops->get_datactrl_cfg(host); in mmci_start_data()
1255 datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0; in mmci_start_data()
1257 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { in mmci_start_data()
1260 datactrl |= variant->datactrl_mask_sdio; in mmci_start_data()
1268 if (variant->st_sdio && data->flags & MMC_DATA_WRITE && in mmci_start_data()
1269 (host->size < 8 || in mmci_start_data()
1270 (host->size <= 8 && host->mclk > 50000000))) in mmci_start_data()
1271 clk = host->clk_reg & ~variant->clkreg_enable; in mmci_start_data()
1273 clk = host->clk_reg | variant->clkreg_enable; in mmci_start_data()
1278 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || in mmci_start_data()
1279 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) in mmci_start_data()
1280 datactrl |= variant->datactrl_mask_ddrmode; in mmci_start_data()
1292 if (data->flags & MMC_DATA_READ) { in mmci_start_data()
1296 * If we have less than the fifo 'half-full' threshold to in mmci_start_data()
1300 if (host->size < variant->fifohalfsize) in mmci_start_data()
1318 void __iomem *base = host->base; in mmci_start_command()
1319 bool busy_resp = cmd->flags & MMC_RSP_BUSY; in mmci_start_command()
1322 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", in mmci_start_command()
1323 cmd->opcode, cmd->arg, cmd->flags); in mmci_start_command()
1325 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { in mmci_start_command()
1330 if (host->variant->cmdreg_stop && in mmci_start_command()
1331 cmd->opcode == MMC_STOP_TRANSMISSION) in mmci_start_command()
1332 c |= host->variant->cmdreg_stop; in mmci_start_command()
1334 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; in mmci_start_command()
1335 if (cmd->flags & MMC_RSP_PRESENT) { in mmci_start_command()
1336 if (cmd->flags & MMC_RSP_136) in mmci_start_command()
1337 c |= host->variant->cmdreg_lrsp_crc; in mmci_start_command()
1338 else if (cmd->flags & MMC_RSP_CRC) in mmci_start_command()
1339 c |= host->variant->cmdreg_srsp_crc; in mmci_start_command()
1341 c |= host->variant->cmdreg_srsp; in mmci_start_command()
1344 host->busy_status = 0; in mmci_start_command()
1345 host->busy_state = MMCI_BUSY_DONE; in mmci_start_command()
1348 if (busy_resp && !cmd->busy_timeout) in mmci_start_command()
1349 cmd->busy_timeout = 10 * MSEC_PER_SEC; in mmci_start_command()
1351 if (busy_resp && host->variant->busy_timeout) { in mmci_start_command()
1352 if (cmd->busy_timeout > host->mmc->max_busy_timeout) in mmci_start_command()
1353 clks = (unsigned long long)host->mmc->max_busy_timeout * host->cclk; in mmci_start_command()
1355 clks = (unsigned long long)cmd->busy_timeout * host->cclk; in mmci_start_command()
1358 writel_relaxed(clks, host->base + MMCIDATATIMER); in mmci_start_command()
1361 if (host->ops->pre_sig_volt_switch && cmd->opcode == SD_SWITCH_VOLTAGE) in mmci_start_command()
1362 host->ops->pre_sig_volt_switch(host); in mmci_start_command()
1368 c |= host->variant->data_cmd_enable; in mmci_start_command()
1370 host->cmd = cmd; in mmci_start_command()
1372 writel(cmd->arg, base + MMCIARGUMENT); in mmci_start_command()
1378 host->stop_abort.error = 0; in mmci_stop_command()
1379 mmci_start_command(host, &host->stop_abort, 0); in mmci_stop_command()
1393 status_err = status & (host->variant->start_err | in mmci_data_irq()
1407 * can be as much as a FIFO-worth of data ahead. This in mmci_data_irq()
1410 if (!host->variant->datacnt_useless) { in mmci_data_irq()
1411 remain = readl(host->base + MMCIDATACNT); in mmci_data_irq()
1412 success = data->blksz * data->blocks - remain; in mmci_data_irq()
1417 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", in mmci_data_irq()
1421 success -= 1; in mmci_data_irq()
1422 data->error = -EILSEQ; in mmci_data_irq()
1424 data->error = -ETIMEDOUT; in mmci_data_irq()
1426 data->error = -ECOMM; in mmci_data_irq()
1428 data->error = -EIO; in mmci_data_irq()
1430 if (success > host->variant->fifosize) in mmci_data_irq()
1431 success -= host->variant->fifosize; in mmci_data_irq()
1434 data->error = -EIO; in mmci_data_irq()
1436 data->bytes_xfered = round_down(success, data->blksz); in mmci_data_irq()
1440 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); in mmci_data_irq()
1442 if (status & MCI_DATAEND || data->error) { in mmci_data_irq()
1447 if (!data->error) in mmci_data_irq()
1449 data->bytes_xfered = data->blksz * data->blocks; in mmci_data_irq()
1451 if (!data->stop) { in mmci_data_irq()
1452 if (host->variant->cmdreg_stop && data->error) in mmci_data_irq()
1455 mmci_request_end(host, data->mrq); in mmci_data_irq()
1456 } else if (host->mrq->sbc && !data->error) { in mmci_data_irq()
1457 mmci_request_end(host, data->mrq); in mmci_data_irq()
1459 mmci_start_command(host, data->stop, 0); in mmci_data_irq()
1469 void __iomem *base = host->base; in mmci_cmd_irq()
1475 sbc = (cmd == host->mrq->sbc); in mmci_cmd_irq()
1476 busy_resp = !!(cmd->flags & MMC_RSP_BUSY); in mmci_cmd_irq()
1483 if (host->variant->busy_timeout && busy_resp) in mmci_cmd_irq()
1486 if (!((status | host->busy_status) & in mmci_cmd_irq()
1491 if (busy_resp && host->variant->busy_detect) in mmci_cmd_irq()
1492 if (!host->ops->busy_complete(host, cmd, status, err_msk)) in mmci_cmd_irq()
1495 host->cmd = NULL; in mmci_cmd_irq()
1498 cmd->error = -ETIMEDOUT; in mmci_cmd_irq()
1499 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { in mmci_cmd_irq()
1500 cmd->error = -EILSEQ; in mmci_cmd_irq()
1501 } else if (host->variant->busy_timeout && busy_resp && in mmci_cmd_irq()
1503 cmd->error = -ETIMEDOUT; in mmci_cmd_irq()
1506 * a hardware reset of the MMCI block. in mmci_cmd_irq()
1508 host->irq_action = IRQ_WAKE_THREAD; in mmci_cmd_irq()
1510 cmd->resp[0] = readl(base + MMCIRESPONSE0); in mmci_cmd_irq()
1511 cmd->resp[1] = readl(base + MMCIRESPONSE1); in mmci_cmd_irq()
1512 cmd->resp[2] = readl(base + MMCIRESPONSE2); in mmci_cmd_irq()
1513 cmd->resp[3] = readl(base + MMCIRESPONSE3); in mmci_cmd_irq()
1516 if ((!sbc && !cmd->data) || cmd->error) { in mmci_cmd_irq()
1517 if (host->data) { in mmci_cmd_irq()
1522 if (host->variant->cmdreg_stop && cmd->error) { in mmci_cmd_irq()
1528 if (host->irq_action != IRQ_WAKE_THREAD) in mmci_cmd_irq()
1529 mmci_request_end(host, host->mrq); in mmci_cmd_irq()
1532 mmci_start_command(host, host->mrq->cmd, 0); in mmci_cmd_irq()
1533 } else if (!host->variant->datactrl_first && in mmci_cmd_irq()
1534 !(cmd->data->flags & MMC_DATA_READ)) { in mmci_cmd_irq()
1535 mmci_start_data(host, cmd->data); in mmci_cmd_irq()
1541 switch (host->busy_state) { in ux500_state_str()
1565 spin_lock_irqsave(&host->lock, flags); in ux500_busy_timeout_work()
1567 if (host->cmd) { in ux500_busy_timeout_work()
1568 /* If we are still busy let's tag on a cmd-timeout error. */ in ux500_busy_timeout_work()
1569 status = readl(host->base + MMCISTATUS); in ux500_busy_timeout_work()
1570 if (status & host->variant->busy_detect_flag) { in ux500_busy_timeout_work()
1572 dev_err(mmc_dev(host->mmc), in ux500_busy_timeout_work()
1574 ux500_state_str(host), host->cmd->opcode); in ux500_busy_timeout_work()
1576 dev_err(mmc_dev(host->mmc), in ux500_busy_timeout_work()
1578 ux500_state_str(host), host->cmd->opcode); in ux500_busy_timeout_work()
1581 mmci_cmd_irq(host, host->cmd, status); in ux500_busy_timeout_work()
1584 spin_unlock_irqrestore(&host->lock, flags); in ux500_busy_timeout_work()
1589 return remain - (readl(host->base + MMCIFIFOCNT) << 2); in mmci_get_rx_fifocnt()
1599 return host->variant->fifohalfsize; in mmci_qcom_get_rx_fifocnt()
1608 void __iomem *base = host->base; in mmci_pio_read()
1610 u32 status = readl(host->base + MMCISTATUS); in mmci_pio_read()
1611 int host_remain = host->size; in mmci_pio_read()
1614 int count = host->get_rx_fifocnt(host, status, host_remain); in mmci_pio_read()
1626 * while only doing full 32-bit reads towards the FIFO. in mmci_pio_read()
1642 remain -= count; in mmci_pio_read()
1643 host_remain -= count; in mmci_pio_read()
1651 return ptr - buffer; in mmci_pio_read()
1656 struct variant_data *variant = host->variant; in mmci_pio_write()
1657 void __iomem *base = host->base; in mmci_pio_write()
1664 variant->fifosize : variant->fifohalfsize; in mmci_pio_write()
1670 * etc), and the FIFO only accept full 32-bit writes. in mmci_pio_write()
1678 remain -= count; in mmci_pio_write()
1686 return ptr - buffer; in mmci_pio_write()
1695 struct sg_mapping_iter *sg_miter = &host->sg_miter; in mmci_pio_irq()
1696 struct variant_data *variant = host->variant; in mmci_pio_irq()
1697 void __iomem *base = host->base; in mmci_pio_irq()
1702 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); in mmci_pio_irq()
1709 * For write, we only need to test the half-empty flag in mmci_pio_irq()
1710 * here - if the FIFO is completely empty, then by in mmci_pio_irq()
1721 buffer = sg_miter->addr; in mmci_pio_irq()
1722 remain = sg_miter->length; in mmci_pio_irq()
1730 sg_miter->consumed = len; in mmci_pio_irq()
1732 host->size -= len; in mmci_pio_irq()
1733 remain -= len; in mmci_pio_irq()
1744 * If we have less than the fifo 'half-full' threshold to transfer, in mmci_pio_irq()
1747 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) in mmci_pio_irq()
1756 if (host->size == 0) { in mmci_pio_irq()
1772 spin_lock(&host->lock); in mmci_irq()
1773 host->irq_action = IRQ_HANDLED; in mmci_irq()
1776 status = readl(host->base + MMCISTATUS); in mmci_irq()
1780 if (host->singleirq) { in mmci_irq()
1781 if (status & host->mask1_reg) in mmci_irq()
1784 status &= ~host->variant->irq_pio_mask; in mmci_irq()
1791 status &= readl(host->base + MMCIMASK0); in mmci_irq()
1792 if (host->variant->busy_detect) in mmci_irq()
1793 writel(status & ~host->variant->busy_detect_mask, in mmci_irq()
1794 host->base + MMCICLEAR); in mmci_irq()
1796 writel(status, host->base + MMCICLEAR); in mmci_irq()
1798 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); in mmci_irq()
1800 if (host->variant->reversed_irq_handling) { in mmci_irq()
1801 mmci_data_irq(host, host->data, status); in mmci_irq()
1802 mmci_cmd_irq(host, host->cmd, status); in mmci_irq()
1804 mmci_cmd_irq(host, host->cmd, status); in mmci_irq()
1805 mmci_data_irq(host, host->data, status); in mmci_irq()
1812 if (host->variant->busy_detect_flag) in mmci_irq()
1813 status &= ~host->variant->busy_detect_flag; in mmci_irq()
1817 spin_unlock(&host->lock); in mmci_irq()
1819 return host->irq_action; in mmci_irq()
1823 * mmci_irq_thread() - A threaded IRQ handler that manages a reset of the HW.
1826 * causes the DPSM to stay busy (non-functional).
1833 if (host->rst) { in mmci_irq_thread()
1834 reset_control_assert(host->rst); in mmci_irq_thread()
1836 reset_control_deassert(host->rst); in mmci_irq_thread()
1839 spin_lock_irqsave(&host->lock, flags); in mmci_irq_thread()
1840 writel(host->clk_reg, host->base + MMCICLOCK); in mmci_irq_thread()
1841 writel(host->pwr_reg, host->base + MMCIPOWER); in mmci_irq_thread()
1842 writel(MCI_IRQENABLE | host->variant->start_err, in mmci_irq_thread()
1843 host->base + MMCIMASK0); in mmci_irq_thread()
1845 host->irq_action = IRQ_HANDLED; in mmci_irq_thread()
1846 mmci_request_end(host, host->mrq); in mmci_irq_thread()
1847 spin_unlock_irqrestore(&host->lock, flags); in mmci_irq_thread()
1849 return host->irq_action; in mmci_irq_thread()
1857 WARN_ON(host->mrq != NULL); in mmci_request()
1859 mrq->cmd->error = mmci_validate_data(host, mrq->data); in mmci_request()
1860 if (mrq->cmd->error) { in mmci_request()
1865 spin_lock_irqsave(&host->lock, flags); in mmci_request()
1867 host->mrq = mrq; in mmci_request()
1869 if (mrq->data) in mmci_request()
1870 mmci_get_next_data(host, mrq->data); in mmci_request()
1872 if (mrq->data && in mmci_request()
1873 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) in mmci_request()
1874 mmci_start_data(host, mrq->data); in mmci_request()
1876 if (mrq->sbc) in mmci_request()
1877 mmci_start_command(host, mrq->sbc, 0); in mmci_request()
1879 mmci_start_command(host, mrq->cmd, 0); in mmci_request()
1881 spin_unlock_irqrestore(&host->lock, flags); in mmci_request()
1889 if (!host->variant->busy_detect) in mmci_set_max_busy_timeout()
1892 if (host->variant->busy_timeout && mmc->actual_clock) in mmci_set_max_busy_timeout()
1893 max_busy_timeout = U32_MAX / DIV_ROUND_UP(mmc->actual_clock, in mmci_set_max_busy_timeout()
1896 mmc->max_busy_timeout = max_busy_timeout; in mmci_set_max_busy_timeout()
1902 struct variant_data *variant = host->variant; in mmci_set_ios()
1907 switch (ios->power_mode) { in mmci_set_ios()
1909 if (!IS_ERR(mmc->supply.vmmc)) in mmci_set_ios()
1910 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in mmci_set_ios()
1912 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { in mmci_set_ios()
1913 regulator_disable(mmc->supply.vqmmc); in mmci_set_ios()
1914 host->vqmmc_enabled = false; in mmci_set_ios()
1919 if (!IS_ERR(mmc->supply.vmmc)) in mmci_set_ios()
1920 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); in mmci_set_ios()
1927 pwr |= variant->pwrreg_powerup; in mmci_set_ios()
1931 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { in mmci_set_ios()
1932 ret = regulator_enable(mmc->supply.vqmmc); in mmci_set_ios()
1937 host->vqmmc_enabled = true; in mmci_set_ios()
1944 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { in mmci_set_ios()
1948 * the SD/MMC bus and feedback-clock usage. in mmci_set_ios()
1950 pwr |= host->pwr_reg_add; in mmci_set_ios()
1952 if (ios->bus_width == MMC_BUS_WIDTH_4) in mmci_set_ios()
1954 else if (ios->bus_width == MMC_BUS_WIDTH_1) in mmci_set_ios()
1960 if (variant->opendrain) { in mmci_set_ios()
1961 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) in mmci_set_ios()
1962 pwr |= variant->opendrain; in mmci_set_ios()
1968 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) in mmci_set_ios()
1969 pinctrl_select_state(host->pinctrl, host->pins_opendrain); in mmci_set_ios()
1978 if (!ios->clock && variant->pwrreg_clkgate) in mmci_set_ios()
1981 if (host->variant->explicit_mclk_control && in mmci_set_ios()
1982 ios->clock != host->clock_cache) { in mmci_set_ios()
1983 ret = clk_set_rate(host->clk, ios->clock); in mmci_set_ios()
1985 dev_err(mmc_dev(host->mmc), in mmci_set_ios()
1988 host->mclk = clk_get_rate(host->clk); in mmci_set_ios()
1990 host->clock_cache = ios->clock; in mmci_set_ios()
1992 spin_lock_irqsave(&host->lock, flags); in mmci_set_ios()
1994 if (host->ops && host->ops->set_clkreg) in mmci_set_ios()
1995 host->ops->set_clkreg(host, ios->clock); in mmci_set_ios()
1997 mmci_set_clkreg(host, ios->clock); in mmci_set_ios()
2001 if (host->ops && host->ops->set_pwrreg) in mmci_set_ios()
2002 host->ops->set_pwrreg(host, pwr); in mmci_set_ios()
2008 spin_unlock_irqrestore(&host->lock, flags); in mmci_set_ios()
2014 struct mmci_platform_data *plat = host->plat; in mmci_get_cd()
2017 if (status == -ENOSYS) { in mmci_get_cd()
2018 if (!plat->status) in mmci_get_cd()
2021 status = plat->status(mmc_dev(host->mmc)); in mmci_get_cd()
2033 if (!ret && host->ops && host->ops->post_sig_volt_switch) in mmci_sig_volt_switch()
2034 ret = host->ops->post_sig_volt_switch(host, ios); in mmci_sig_volt_switch()
2064 * Assume the level translator is present if st,use-ckin is set. in mmci_probe_level_translator()
2067 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; in mmci_probe_level_translator()
2098 host->clk_reg_add &= ~MCI_STM32_CLK_SELCKIN; in mmci_probe_level_translator()
2121 if (of_property_read_bool(np, "st,sig-dir-dat0")) in mmci_of_parse()
2122 host->pwr_reg_add |= MCI_ST_DATA0DIREN; in mmci_of_parse()
2123 if (of_property_read_bool(np, "st,sig-dir-dat2")) in mmci_of_parse()
2124 host->pwr_reg_add |= MCI_ST_DATA2DIREN; in mmci_of_parse()
2125 if (of_property_read_bool(np, "st,sig-dir-dat31")) in mmci_of_parse()
2126 host->pwr_reg_add |= MCI_ST_DATA31DIREN; in mmci_of_parse()
2127 if (of_property_read_bool(np, "st,sig-dir-dat74")) in mmci_of_parse()
2128 host->pwr_reg_add |= MCI_ST_DATA74DIREN; in mmci_of_parse()
2129 if (of_property_read_bool(np, "st,sig-dir-cmd")) in mmci_of_parse()
2130 host->pwr_reg_add |= MCI_ST_CMDDIREN; in mmci_of_parse()
2131 if (of_property_read_bool(np, "st,sig-pin-fbclk")) in mmci_of_parse()
2132 host->pwr_reg_add |= MCI_ST_FBCLKEN; in mmci_of_parse()
2133 if (of_property_read_bool(np, "st,sig-dir")) in mmci_of_parse()
2134 host->pwr_reg_add |= MCI_STM32_DIRPOL; in mmci_of_parse()
2135 if (of_property_read_bool(np, "st,neg-edge")) in mmci_of_parse()
2136 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; in mmci_of_parse()
2137 if (of_property_read_bool(np, "st,use-ckin")) in mmci_of_parse()
2140 if (of_property_read_bool(np, "mmc-cap-mmc-highspeed")) in mmci_of_parse()
2141 mmc->caps |= MMC_CAP_MMC_HIGHSPEED; in mmci_of_parse()
2142 if (of_property_read_bool(np, "mmc-cap-sd-highspeed")) in mmci_of_parse()
2143 mmc->caps |= MMC_CAP_SD_HIGHSPEED; in mmci_of_parse()
2151 struct mmci_platform_data *plat = dev->dev.platform_data; in mmci_probe()
2152 struct device_node *np = dev->dev.of_node; in mmci_probe()
2153 struct variant_data *variant = id->data; in mmci_probe()
2160 dev_err(&dev->dev, "No plat data or DT found\n"); in mmci_probe()
2161 return -EINVAL; in mmci_probe()
2165 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); in mmci_probe()
2167 return -ENOMEM; in mmci_probe()
2170 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); in mmci_probe()
2172 return -ENOMEM; in mmci_probe()
2175 host->mmc = mmc; in mmci_probe()
2176 host->mmc_ops = &mmci_ops; in mmci_probe()
2177 mmc->ops = &mmci_ops; in mmci_probe()
2187 if (!variant->opendrain) { in mmci_probe()
2188 host->pinctrl = devm_pinctrl_get(&dev->dev); in mmci_probe()
2189 if (IS_ERR(host->pinctrl)) { in mmci_probe()
2190 dev_err(&dev->dev, "failed to get pinctrl"); in mmci_probe()
2191 ret = PTR_ERR(host->pinctrl); in mmci_probe()
2195 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, in mmci_probe()
2197 if (IS_ERR(host->pins_opendrain)) { in mmci_probe()
2199 ret = PTR_ERR(host->pins_opendrain); in mmci_probe()
2204 host->hw_designer = amba_manf(dev); in mmci_probe()
2205 host->hw_revision = amba_rev(dev); in mmci_probe()
2206 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); in mmci_probe()
2207 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); in mmci_probe()
2209 host->clk = devm_clk_get(&dev->dev, NULL); in mmci_probe()
2210 if (IS_ERR(host->clk)) { in mmci_probe()
2211 ret = PTR_ERR(host->clk); in mmci_probe()
2215 ret = clk_prepare_enable(host->clk); in mmci_probe()
2219 if (variant->qcom_fifo) in mmci_probe()
2220 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; in mmci_probe()
2222 host->get_rx_fifocnt = mmci_get_rx_fifocnt; in mmci_probe()
2224 host->plat = plat; in mmci_probe()
2225 host->variant = variant; in mmci_probe()
2226 host->mclk = clk_get_rate(host->clk); in mmci_probe()
2232 if (host->mclk > variant->f_max) { in mmci_probe()
2233 ret = clk_set_rate(host->clk, variant->f_max); in mmci_probe()
2236 host->mclk = clk_get_rate(host->clk); in mmci_probe()
2238 host->mclk); in mmci_probe()
2241 host->phybase = dev->res.start; in mmci_probe()
2242 host->base = devm_ioremap_resource(&dev->dev, &dev->res); in mmci_probe()
2243 if (IS_ERR(host->base)) { in mmci_probe()
2244 ret = PTR_ERR(host->base); in mmci_probe()
2248 if (variant->init) in mmci_probe()
2249 variant->init(host); in mmci_probe()
2257 if (variant->st_clkdiv) in mmci_probe()
2258 mmc->f_min = DIV_ROUND_UP(host->mclk, 257); in mmci_probe()
2259 else if (variant->stm32_clkdiv) in mmci_probe()
2260 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); in mmci_probe()
2261 else if (variant->explicit_mclk_control) in mmci_probe()
2262 mmc->f_min = clk_round_rate(host->clk, 100000); in mmci_probe()
2264 mmc->f_min = DIV_ROUND_UP(host->mclk, 512); in mmci_probe()
2271 if (mmc->f_max) in mmci_probe()
2272 mmc->f_max = variant->explicit_mclk_control ? in mmci_probe()
2273 min(variant->f_max, mmc->f_max) : in mmci_probe()
2274 min(host->mclk, mmc->f_max); in mmci_probe()
2276 mmc->f_max = variant->explicit_mclk_control ? in mmci_probe()
2277 fmax : min(host->mclk, fmax); in mmci_probe()
2280 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); in mmci_probe()
2282 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); in mmci_probe()
2283 if (IS_ERR(host->rst)) { in mmci_probe()
2284 ret = PTR_ERR(host->rst); in mmci_probe()
2287 ret = reset_control_deassert(host->rst); in mmci_probe()
2289 dev_err(mmc_dev(mmc), "failed to de-assert reset\n"); in mmci_probe()
2296 if (!mmc->ocr_avail) in mmci_probe()
2297 mmc->ocr_avail = plat->ocr_mask; in mmci_probe()
2298 else if (plat->ocr_mask) in mmci_probe()
2302 mmc->caps |= MMC_CAP_CMD23; in mmci_probe()
2307 if (variant->busy_detect) { in mmci_probe()
2313 if (variant->busy_dpsm_flag) in mmci_probe()
2315 host->variant->busy_dpsm_flag); in mmci_probe()
2316 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in mmci_probe()
2320 if (variant->busy_timeout) in mmci_probe()
2321 mmc->caps |= MMC_CAP_NEED_RSP_BUSY; in mmci_probe()
2323 /* Prepare a CMD12 - needed to clear the DPSM on some variants. */ in mmci_probe()
2324 host->stop_abort.opcode = MMC_STOP_TRANSMISSION; in mmci_probe()
2325 host->stop_abort.arg = 0; in mmci_probe()
2326 host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC; in mmci_probe()
2329 mmc->pm_caps |= MMC_PM_KEEP_POWER; in mmci_probe()
2334 mmc->max_segs = NR_SG; in mmci_probe()
2338 * register, we must ensure that we don't exceed 2^num-1 bytes in a in mmci_probe()
2341 mmc->max_req_size = (1 << variant->datalength_bits) - 1; in mmci_probe()
2347 mmc->max_seg_size = mmc->max_req_size; in mmci_probe()
2352 mmc->max_blk_size = 1 << variant->datactrl_blocksz; in mmci_probe()
2358 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; in mmci_probe()
2360 spin_lock_init(&host->lock); in mmci_probe()
2362 writel(0, host->base + MMCIMASK0); in mmci_probe()
2364 if (variant->mmcimask1) in mmci_probe()
2365 writel(0, host->base + MMCIMASK1); in mmci_probe()
2367 writel(0xfff, host->base + MMCICLEAR); in mmci_probe()
2371 * - not using DT but using a descriptor table, or in mmci_probe()
2372 * - using a table of descriptors ALONGSIDE DT, or in mmci_probe()
2378 if (ret == -EPROBE_DEFER) in mmci_probe()
2382 if (ret == -EPROBE_DEFER) in mmci_probe()
2386 ret = devm_request_threaded_irq(&dev->dev, dev->irq[0], mmci_irq, in mmci_probe()
2392 if (!dev->irq[1]) in mmci_probe()
2393 host->singleirq = true; in mmci_probe()
2395 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, in mmci_probe()
2401 if (host->variant->busy_detect) in mmci_probe()
2402 INIT_DELAYED_WORK(&host->ux500_busy_timeout_work, in mmci_probe()
2405 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); in mmci_probe()
2409 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", in mmci_probe()
2411 amba_rev(dev), (unsigned long long)dev->res.start, in mmci_probe()
2412 dev->irq[0], dev->irq[1]); in mmci_probe()
2416 pm_runtime_set_autosuspend_delay(&dev->dev, 50); in mmci_probe()
2417 pm_runtime_use_autosuspend(&dev->dev); in mmci_probe()
2423 pm_runtime_put(&dev->dev); in mmci_probe()
2427 clk_disable_unprepare(host->clk); in mmci_probe()
2439 struct variant_data *variant = host->variant; in mmci_remove()
2445 pm_runtime_get_sync(&dev->dev); in mmci_remove()
2449 writel(0, host->base + MMCIMASK0); in mmci_remove()
2451 if (variant->mmcimask1) in mmci_remove()
2452 writel(0, host->base + MMCIMASK1); in mmci_remove()
2454 writel(0, host->base + MMCICOMMAND); in mmci_remove()
2455 writel(0, host->base + MMCIDATACTRL); in mmci_remove()
2458 clk_disable_unprepare(host->clk); in mmci_remove()
2468 spin_lock_irqsave(&host->lock, flags); in mmci_save()
2470 writel(0, host->base + MMCIMASK0); in mmci_save()
2471 if (host->variant->pwrreg_nopower) { in mmci_save()
2472 writel(0, host->base + MMCIDATACTRL); in mmci_save()
2473 writel(0, host->base + MMCIPOWER); in mmci_save()
2474 writel(0, host->base + MMCICLOCK); in mmci_save()
2478 spin_unlock_irqrestore(&host->lock, flags); in mmci_save()
2485 spin_lock_irqsave(&host->lock, flags); in mmci_restore()
2487 if (host->variant->pwrreg_nopower) { in mmci_restore()
2488 writel(host->clk_reg, host->base + MMCICLOCK); in mmci_restore()
2489 writel(host->datactrl_reg, host->base + MMCIDATACTRL); in mmci_restore()
2490 writel(host->pwr_reg, host->base + MMCIPOWER); in mmci_restore()
2492 writel(MCI_IRQENABLE | host->variant->start_err, in mmci_restore()
2493 host->base + MMCIMASK0); in mmci_restore()
2496 spin_unlock_irqrestore(&host->lock, flags); in mmci_restore()
2508 clk_disable_unprepare(host->clk); in mmci_runtime_suspend()
2521 clk_prepare_enable(host->clk); in mmci_runtime_resume()